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-rw-r--r--2004/n/fpga/src/decodisa/decodisa.vhd97
1 files changed, 61 insertions, 36 deletions
diff --git a/2004/n/fpga/src/decodisa/decodisa.vhd b/2004/n/fpga/src/decodisa/decodisa.vhd
index e75005f..463e767 100644
--- a/2004/n/fpga/src/decodisa/decodisa.vhd
+++ b/2004/n/fpga/src/decodisa/decodisa.vhd
@@ -1,36 +1,61 @@
--- Décodeur de bus ISA pour le fpga robot
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-
-entity decodisa is
-generic(
- myISA_adress: integer :=1234;
- adr_bus_bit: integer :=10
- );
-port(
- ISA_clk: in std_logic;
- ISA_RW: in std_logic; -- 1=read 0=write
- ISA_adr_bus: in std_logic_vector(20 downto 0);
-
- clk: out std_logic;
- RW: out std_logic;
- adr_bus: out std_logic_vector(20 downto 0);
- );
-end entity;
-
-
---
-architecture rtl of decodisa is
-signal myAdr: std_logic_vector(10 downto 0) := conv_std_logic_vector(integer(myISA_adress));
-
-begin
-process(ISA_adr_bus)
- if(ISA_adr_bus=myAdr) then
- adr_bus<=ISA_adr_bus;
- else
- adr_bus<=(others <= '0');
- end if;
-end process;
-
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+
+entity decodisa is
+port(
+ adr_bus: in std_logic_vector(23 downto 0);
+ AEN:in std_logic;
+ IOR:in std_logic;
+ IOW:in std_logic;
+
+ cs: out std_logic_vector(255 downto 0);
+ rw: out std_logic;
+ clk: out std_logic
+);
+constant adr_reseau:std_logic_vector:="0000000000000001";
+constant W_reseau:integer:=16;
+constant W_sous_reseau:integer:=8; -- Attention : si changement sur ces valeurs,=> modifier le core !!!
+end decodisa;
+
+architecture rtl of decodisa is
+
+component decodadr
+ port (
+ S: IN std_logic_VECTOR((W_sous_reseau-1) downto 0);
+ O: OUT std_logic_VECTOR(255 downto 0);
+ EN: IN std_logic);
+end component;
+
+component decodsig
+port(
+ AEN:in std_logic;
+ IOR:in std_logic;
+ IOW:in std_logic;
+ rw: out std_logic;
+ clk: out std_logic);
+end component;
+
+signal reg_select : std_logic;
+
+begin
+dsig:decodsig
+port map(
+ AEN=>AEN,
+ IOR=>IOR,
+ IOW=>IOW,
+ rw=>rw,
+ clk=>clk);
+
+dadrL:decodadr
+port map(
+ S=>adr_bus((W_sous_reseau - 1) downto 0),
+ O=>cs,
+ EN=>reg_select);
+
+reg_select<='1' when (adr_bus((W_reseau - 1) downto W_sous_reseau)=adr_reseau) else '0';
+
+end rtl;