summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/decodisa/bch_decodisa.vhd
diff options
context:
space:
mode:
Diffstat (limited to '2004/n/fpga/src/decodisa/bch_decodisa.vhd')
-rw-r--r--2004/n/fpga/src/decodisa/bch_decodisa.vhd59
1 files changed, 59 insertions, 0 deletions
diff --git a/2004/n/fpga/src/decodisa/bch_decodisa.vhd b/2004/n/fpga/src/decodisa/bch_decodisa.vhd
new file mode 100644
index 0000000..5457481
--- /dev/null
+++ b/2004/n/fpga/src/decodisa/bch_decodisa.vhd
@@ -0,0 +1,59 @@
+
+-- VHDL Test Bench Created from source file decodisa.vhd -- 02:25:56 03/17/2004
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+ENTITY decodisa_bch IS
+END decodisa_bch;
+
+ARCHITECTURE behavior OF decodisa_bch IS
+
+ COMPONENT decodisa
+ PORT(
+ adr_bus : IN std_logic_vector(23 downto 0);
+ AEN : IN std_logic;
+ IOR : IN std_logic;
+ IOW : IN std_logic;
+ cs : OUT std_logic_vector(255 downto 0);
+ rw : OUT std_logic;
+ clk : OUT std_logic
+ );
+ END COMPONENT;
+
+ SIGNAL adr_bus : std_logic_vector(23 downto 0):=(others => '0');
+ SIGNAL AEN : std_logic:='0';
+ SIGNAL IOR : std_logic:='0';
+ SIGNAL IOW : std_logic:='0';
+ SIGNAL cs : std_logic_vector(255 downto 0);
+ SIGNAL rw : std_logic;
+ SIGNAL clk : std_logic;
+
+BEGIN
+
+ uut: decodisa PORT MAP(
+ adr_bus => adr_bus,
+ AEN => AEN,
+ IOR => IOR,
+ IOW => IOW,
+ cs => cs,
+ rw => rw,
+ clk => clk
+ );
+
+adr_bus <= conv_std_logic_vector(unsigned(adr_bus) + 1 , 24) after 120 ns;
+aen<= not aen after 1500 ns;
+ior<= not ior after 70 ns;
+iow<= not iow after 50 ns;
+
+
+END;