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authorKen Sarkies2012-08-20 17:19:20 +0930
committerKen Sarkies2012-08-20 17:19:20 +0930
commit52533a6e3d2e3a1936ce76692774557a354d3569 (patch)
tree6f6670d0e80882175befff2e3aa0da7e279f8595 /lib/stm32/iwdg.c
parenta2c5b6391d82684838e923c6d7437367110f5480 (diff)
STM32F1xx: Changed markup to get more control over documentation, each
file having its own group module rather than using @file. No code changes except for the following: gpio: Added function to map the eventout signal plus two Remap functions dma: Prevent changing base addresses while channel enabled (see datasheet) pwr: Added pwr.c (new file) timer: Removed the last function that I introduced recently; there is already an equivalent function present. Changed some parameter names for consistency.
Diffstat (limited to 'lib/stm32/iwdg.c')
-rw-r--r--lib/stm32/iwdg.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/lib/stm32/iwdg.c b/lib/stm32/iwdg.c
index 0968e7f..84304ad 100644
--- a/lib/stm32/iwdg.c
+++ b/lib/stm32/iwdg.c
@@ -1,6 +1,6 @@
-/** @file
+/** @defgroup STM32F-iwdg-file IWDG
-@ingroup STM32F
+@ingroup STM32F-files
@brief <b>libopencm3 STM32F1xx Independent Watchdog Timer</b>
@@ -8,7 +8,7 @@
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
-@date 11 June 2012
+@date 18 August 2012
This library supports the Independent Watchdog Timer System in the STM32F1xx
series of ARM Cortex Microcontrollers by ST Microelectronics.
@@ -22,8 +22,6 @@ Note that the User Configuration option byte provides a means of automatically
enabling the IWDG timer at power on (with counter value 0xFFF). If the
relevant bit is not set, the IWDG timer must be enabled by software.
-@bugs None known
-
@note: Tested: CPU STM32F103RET6, Board ET-ARM Stamp STM32
LGPL License Terms @ref lgpl_license
@@ -45,9 +43,13 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
+/**@{*/
+
#include <libopencm3/stm32/iwdg.h>
#define LSI_FREQUENCY 32000
+#define COUNT_LENGTH 12
+#define COUNT_MASK ((1 << COUNT_LENGTH)-1)
/*-----------------------------------------------------------------------------*/
/** @brief IWDG Enable Watchdog Timer
@@ -73,13 +75,10 @@ A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds)
can occasionally occur if the prescale or preload registers are currently busy
loading a previous value.
-@param[in] u32 Period in milliseconds (< 32760) from a watchdog reset until
+@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset until
a system reset is issued.
*/
-#define COUNT_LENGTH 12
-#define COUNT_MASK ((1 << COUNT_LENGTH)-1)
-
void iwdg_set_period_ms(u32 period)
{
u32 count, prescale, reload, exponent;
@@ -141,4 +140,5 @@ void iwdg_reset(void)
{
IWDG_KR = IWDG_KR_RESET;
}
+/**@}*/