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authorFergus Noble2012-01-25 22:09:54 -0800
committerUwe Hermann2012-02-06 23:08:06 +0100
commit5dce4172a8ce3c80b37f4b45706c3a6032e9c34d (patch)
tree30ba15dc26fb1681a5eec1ccfc54896b0149679e /lib/stm32/f4
parentfae83c43c105bb51326ab9d1464df9b912447b48 (diff)
Fix bug with F4 clock settings, change HPRE to PPRE.
Diffstat (limited to 'lib/stm32/f4')
-rw-r--r--lib/stm32/f4/rcc.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
index e10ef21..1a5d868 100644
--- a/lib/stm32/f4/rcc.c
+++ b/lib/stm32/f4/rcc.c
@@ -35,8 +35,8 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
- .ppre1 = RCC_CFGR_HPRE_DIV_4,
- .ppre2 = RCC_CFGR_HPRE_DIV_2,
+ .ppre1 = RCC_CFGR_PPRE_DIV_4,
+ .ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS,
.apb1_frequency = 30000000,
@@ -48,8 +48,8 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] =
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
- .ppre1 = RCC_CFGR_HPRE_DIV_4,
- .ppre2 = RCC_CFGR_HPRE_DIV_2,
+ .ppre1 = RCC_CFGR_PPRE_DIV_4,
+ .ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ICE | FLASH_DCE | FLASH_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,