aboutsummaryrefslogtreecommitdiff
path: root/lib/stm32/f1/ethernet.c
diff options
context:
space:
mode:
authorStephen Caudle2011-10-28 15:44:29 -0400
committerStephen Caudle2011-10-30 17:42:49 -0400
commitb3a710b0bcc8e765b32cc255dc5047323933d22e (patch)
treeb77acc4dfa1a0b7170121124f0563faac906a0ee /lib/stm32/f1/ethernet.c
parent3900d16740b790ea2603b8fa7f627da7ff5a9753 (diff)
Rename stm32 lib folders to be consistent with include
Diffstat (limited to 'lib/stm32/f1/ethernet.c')
-rw-r--r--lib/stm32/f1/ethernet.c53
1 files changed, 53 insertions, 0 deletions
diff --git a/lib/stm32/f1/ethernet.c b/lib/stm32/f1/ethernet.c
new file mode 100644
index 0000000..fc65ec2
--- /dev/null
+++ b/lib/stm32/f1/ethernet.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/f1/ethernet.h>
+
+void eth_smi_write(u8 phy, u8 reg, u16 data)
+{
+ /* Set PHY and register addresses for write access. */
+ ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA);
+ ETH_MACMIIAR |= (phy << 11) | (reg << 6) | ETH_MACMIIAR_MW;
+
+ /* Set register value. */
+ ETH_MACMIIDR = data;
+
+ /* Begin transaction. */
+ ETH_MACMIIAR |= ETH_MACMIIAR_MB;
+
+ /* Wait for not busy. */
+ while (ETH_MACMIIAR & ETH_MACMIIAR_MB);
+}
+
+u16 eth_smi_read(u8 phy, u8 reg)
+{
+ /* Set PHY and register addresses for write access. */
+ ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA |
+ ETH_MACMIIAR_MW);
+ ETH_MACMIIAR |= (phy << 11) | (reg << 6);
+
+ /* Begin transaction. */
+ ETH_MACMIIAR |= ETH_MACMIIAR_MB;
+
+ /* Wait for not busy. */
+ while (ETH_MACMIIAR & ETH_MACMIIAR_MB);
+
+ /* Set register value. */
+ return (u16)(ETH_MACMIIDR);
+}