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authorUwe Hermann2010-12-31 18:18:39 +0100
committerUwe Hermann2010-12-31 18:18:39 +0100
commit8f251e8a9d46634be4741f7f1aef3d52fb1b7dba (patch)
treefb3c17756e0b18fe19ca28f0f67b2ae636cac807 /include/libopencm3/stm32
parent95793aa6cedeef06db9592602ecf3dc00edec610 (diff)
Some more file/path restructuring.
All #includes now explicitly use the "<libopencm3/stm32/rcc.h>" format. If you want to get rid of the "libopencm3" prefix in your local project you can add a respective -I entry in your Makefile (not recommended though). All .ld files and .a libs are installed in $(TOOLCHAIN_DIR)/lib directly (as before), but are now renamed to avoid potential conflicts now or in the future. Examples: libopencm3_lpc13xx.a libopencm3_lpc13xx.ld libopencm3_stm32.a libopencm3_stm32.ld
Diffstat (limited to 'include/libopencm3/stm32')
-rw-r--r--include/libopencm3/stm32/adc.h418
-rw-r--r--include/libopencm3/stm32/bkp.h208
-rw-r--r--include/libopencm3/stm32/can.h642
-rw-r--r--include/libopencm3/stm32/crc.h52
-rw-r--r--include/libopencm3/stm32/dma.h723
-rw-r--r--include/libopencm3/stm32/ethernet.h203
-rw-r--r--include/libopencm3/stm32/exti.h70
-rw-r--r--include/libopencm3/stm32/flash.h113
-rw-r--r--include/libopencm3/stm32/fsmc.h284
-rw-r--r--include/libopencm3/stm32/gpio.h555
-rw-r--r--include/libopencm3/stm32/i2c.h333
-rw-r--r--include/libopencm3/stm32/iwdg.h75
-rw-r--r--include/libopencm3/stm32/memorymap.h100
-rw-r--r--include/libopencm3/stm32/nvic.h154
-rw-r--r--include/libopencm3/stm32/pwr.h81
-rw-r--r--include/libopencm3/stm32/rcc.h407
-rw-r--r--include/libopencm3/stm32/rtc.h146
-rw-r--r--include/libopencm3/stm32/scb.h300
-rw-r--r--include/libopencm3/stm32/spi.h331
-rw-r--r--include/libopencm3/stm32/systick.h82
-rw-r--r--include/libopencm3/stm32/timer.h807
-rw-r--r--include/libopencm3/stm32/tools.h64
-rw-r--r--include/libopencm3/stm32/usart.h312
-rw-r--r--include/libopencm3/stm32/usb.h258
-rw-r--r--include/libopencm3/stm32/usb_desc.h101
-rw-r--r--include/libopencm3/stm32/wwdg.h74
26 files changed, 6893 insertions, 0 deletions
diff --git a/include/libopencm3/stm32/adc.h b/include/libopencm3/stm32/adc.h
new file mode 100644
index 0000000..6e35d59
--- /dev/null
+++ b/include/libopencm3/stm32/adc.h
@@ -0,0 +1,418 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_ADC_H
+#define LIBOPENCM3_ADC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* ADC port base addresses (for convenience) */
+#define ADC1 ADC1_BASE
+#define ADC2 ADC2_BASE
+#define ADC3 ADC3_BASE
+
+/* --- ADC registers ------------------------------------------------------- */
+
+/* ADC status register (ADC_SR) */
+#define ADC_SR(block) MMIO32(block + 0x00)
+#define ADC1_SR ADC_SR(ADC1)
+#define ADC2_SR ADC_SR(ADC2)
+#define ADC3_SR ADC_SR(ADC3)
+
+/* ADC control register 1 (ADC_CR1) */
+#define ADC_CR1(block) MMIO32(block + 0x04)
+#define ADC1_CR1 ADC_CR1(ADC1)
+#define ADC2_CR1 ADC_CR1(ADC2)
+#define ADC3_CR1 ADC_CR1(ADC3)
+
+/* ADC control register 2 (ADC_CR2) */
+#define ADC_CR2(block) MMIO32(block + 0x08)
+#define ADC1_CR2 ADC_CR2(ADC1)
+#define ADC2_CR2 ADC_CR2(ADC2)
+#define ADC3_CR2 ADC_CR2(ADC3)
+
+/* ADC sample time register 1 (ADC_SMPR1) */
+#define ADC_SMPR1(block) MMIO32(block + 0x0c)
+#define ADC1_SMPR1 ADC_SMPR1(ADC1)
+#define ADC2_SMPR1 ADC_SMPR1(ADC2)
+#define ADC3_SMPR1 ADC_SMPR1(ADC3)
+
+/* ADC sample time register 2 (ADC_SMPR2) */
+#define ADC_SMPR2(block) MMIO32(block + 0x10)
+#define ADC1_SMPR2 ADC_SMPR2(ADC1)
+#define ADC2_SMPR2 ADC_SMPR2(ADC2)
+#define ADC3_SMPR2 ADC_SMPR2(ADC3)
+
+/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */
+#define ADC_JOFR1(block) MMIO32(block + 0x14)
+#define ADC_JOFR2(block) MMIO32(block + 0x18)
+#define ADC_JOFR3(block) MMIO32(block + 0x1c)
+#define ADC_JOFR4(block) MMIO32(block + 0x20)
+#define ADC1_JOFR1 ADC_JOFR1(ADC1)
+#define ADC2_JOFR1 ADC_JOFR1(ADC2)
+#define ADC3_JOFR1 ADC_JOFR1(ADC3)
+#define ADC1_JOFR2 ADC_JOFR2(ADC1)
+#define ADC2_JOFR2 ADC_JOFR2(ADC2)
+#define ADC3_JOFR2 ADC_JOFR2(ADC3)
+#define ADC1_JOFR3 ADC_JOFR3(ADC1)
+#define ADC2_JOFR3 ADC_JOFR3(ADC2)
+#define ADC3_JOFR3 ADC_JOFR3(ADC3)
+#define ADC1_JOFR4 ADC_JOFR4(ADC1)
+#define ADC2_JOFR4 ADC_JOFR4(ADC2)
+#define ADC3_JOFR4 ADC_JOFR4(ADC3)
+
+/* ADC watchdog high threshold register (ADC_HTR) */
+#define ADC_HTR(block) MMIO32(block + 0x24)
+#define ADC1_HTR ADC_HTR(ADC1)
+#define ADC2_HTR ADC_HTR(ADC2)
+#define ADC3_HTR ADC_HTR(ADC3)
+
+/* ADC watchdog low threshold register (ADC_LTR) */
+#define ADC_LTR(block) MMIO32(block + 0x28)
+#define ADC1_LTR ADC_LTR(ADC1_BASE)
+#define ADC2_LTR ADC_LTR(ADC2_BASE)
+#define ADC3_LTR ADC_LTR(ADC3_BASE)
+
+/* ADC regular sequence register 1 (ADC_SQR1) */
+#define ADC_SQR1(block) MMIO32(block + 0x2c)
+#define ADC1_SQR1 ADC_SQR1(ADC1)
+#define ADC2_SQR1 ADC_SQR1(ADC2)
+#define ADC3_SQR1 ADC_SQR1(ADC3)
+
+/* ADC regular sequence register 2 (ADC_SQR2) */
+#define ADC_SQR2(block) MMIO32(block + 0x30)
+#define ADC1_SQR2 ADC_SQR2(ADC1)
+#define ADC2_SQR2 ADC_SQR2(ADC2)
+#define ADC3_SQR2 ADC_SQR2(ADC3)
+
+/* ADC regular sequence register 3 (ADC_SQR3) */
+#define ADC_SQR3(block) MMIO32(block + 0x34)
+#define ADC1_SQR3 ADC_SQR3(ADC1)
+#define ADC2_SQR3 ADC_SQR3(ADC2)
+#define ADC3_SQR3 ADC_SQR3(ADC3)
+
+/* ADC injected sequence register (ADC_JSQR) */
+#define ADC_JSQR(block) MMIO32(block + 0x38)
+#define ADC1_JSQR ADC_JSQR(ADC1_BASE)
+#define ADC2_JSQR ADC_JSQR(ADC2_BASE)
+#define ADC3_JSQR ADC_JSQR(ADC3_BASE)
+
+/* ADC injected data register x (ADC_JDRx) (x=1..4) */
+#define ADC_JDR1(block) MMIO32(block + 0x3c)
+#define ADC_JDR2(block) MMIO32(block + 0x40)
+#define ADC_JDR3(block) MMIO32(block + 0x44)
+#define ADC_JDR4(block) MMIO32(block + 0x48)
+#define ADC1_JDR1 ADC_JDR1(ADC1)
+#define ADC2_JDR1 ADC_JDR1(ADC2)
+#define ADC3_JDR1 ADC_JDR1(ADC3)
+#define ADC1_JDR2 ADC_JDR2(ADC1)
+#define ADC2_JDR2 ADC_JDR2(ADC2)
+#define ADC3_JDR2 ADC_JDR2(ADC3)
+#define ADC1_JDR3 ADC_JDR3(ADC1)
+#define ADC2_JDR3 ADC_JDR3(ADC2)
+#define ADC3_JDR3 ADC_JDR3(ADC3)
+#define ADC1_JDR4 ADC_JDR4(ADC1)
+#define ADC2_JDR4 ADC_JDR4(ADC2)
+#define ADC3_JDR4 ADC_JDR4(ADC3)
+
+/* ADC regular data register (ADC_DR) */
+#define ADC_DR(block) MMIO32(block + 0x4c)
+#define ADC1_DR ADC_DR(ADC1)
+#define ADC2_DR ADC_DR(ADC2)
+#define ADC3_DR ADC_DR(ADC3)
+
+/* --- ADC_SR values ------------------------------------------------------- */
+
+#define ADC_SR_STRT (1 << 4)
+#define ADC_SR_JSTRT (1 << 3)
+#define ADC_SR_JEOC (1 << 2)
+#define ADC_SR_EOC (1 << 1)
+#define ADC_SR_AWD (1 << 0)
+
+/* --- ADC_CR1 values ------------------------------------------------------ */
+
+#define ADC_CR1_AWDEN (1 << 23)
+#define ADC_CR1_JAWDEN (1 << 22)
+#define ADC_CR1_DUALMOD_LSB 16
+#define ADC_CR1_DUALMOD_MSK (0xf << ADC_DUALMOD_LSB) /* ADC1 only */
+#define ADC_CR1_DISCNUM_LSB 13
+#define ADC_CR1_DISCNUM_MSK (0x7 << ADC_DISCNUM_LSB)
+#define ADC_CR1_JDISCEN (1 << 12)
+#define ADC_CR1_DISCEN (1 << 11)
+#define ADC_CR1_JAUTO (1 << 10)
+#define ADC_CR1_AWDSGL (1 << 9)
+#define ADC_CR1_SCAN (1 << 8)
+#define ADC_CR1_JEOCIE (1 << 7)
+#define ADC_CR1_AWDIE (1 << 6)
+#define ADC_CR1_EOCIE (1 << 5)
+#define ADC_CR1_AWDCH_LSB 0
+#define ADC_CR1_AWDCH_MSK (0x1f << ADC_AWDCH_LSB)
+
+/* --- ADC_CR2 values ------------------------------------------------------ */
+
+#define ADC_CR2_TSVREFE (1 << 23) /* ADC1 only! */
+#define ADC_CR2_SWSTART (1 << 22)
+#define ADC_CR2_JSWSTART (1 << 21)
+#define ADC_CR2_EXTTRIG (1 << 20)
+#define ADC_CR2_EXTSEL_LSB 17
+#define ADC_CR2_EXTSEL_MSK (0x7 << ADC_EXTSEL_LSB)
+/* The following are only valid for ADC1 and ADC2. */
+#define ADC_CR2_EXTSEL_TIM1_CC1 0x0
+#define ADC_CR2_EXTSEL_TIM1_CC2 0x1
+#define ADC_CR2_EXTSEL_TIM1_CC3 0x2
+#define ADC_CR2_EXTSEL_TIM2_CC2 0x3
+#define ADC_CR2_EXTSEL_TIM3_TRGO 0x4
+#define ADC_CR2_EXTSEL_TIM4_CC4 0x5
+#define ADC_CR2_EXTSEL_EXTI11 0x6
+#define ADC_CR2_EXTSEL_SWSTART 0x7
+
+/* The following are only valid for ADC3 */
+#define ADC_CR2_EXTSEL_TIM3_CC1 0x0
+#define ADC_CR2_EXTSEL_TIM2_CC3 0x1
+#define ADC_CR2_EXTSEL_TIM8_CC1 0x3
+#define ADC_CR2_EXTSEL_TIM8_TRGO 0x4
+#define ADC_CR2_EXTSEL_TIM5_CC1 0x5
+#define ADC_CR2_EXTSEL_TIM5_CC3 0x6
+
+/* Bit 16: reserved, must be kept cleared */
+#define ADC_CR2_JEXTTRIG (1 << 15)
+#define ADC_CR2_JEXTSEL_LSB 12
+#define ADC_CR2_JEXTSEL_MSK (0x7 << ADC_JEXTSEL_LSB)
+/* The following are only valid for ADC1 and ADC2. */
+#define ADC_CR2_JEXTSEL_TIM1_TRGO 0x0
+#define ADC_CR2_JEXTSEL_TIM1_CC4 0x1
+#define ADC_CR2_JEXTSEL_TIM2_TRGO 0x2
+#define ADC_CR2_JEXTSEL_TIM2_CC1 0x3
+#define ADC_CR2_JEXTSEL_TIM3_CC4 0x4
+#define ADC_CR2_JEXTSEL_TIM4_TRGO 0x5
+#define ADC_CR2_JEXTSEL_EXTI15 0x6
+#define ADC_CR2_JEXTSEL_JSWSTART 0x7
+
+/* The following are the different meanings for ADC3 only. */
+#define ADC_CR2_JEXTSEL_TIM4_CC3 0x2
+#define ADC_CR2_JEXTSEL_TIM8_CC2 0x3
+#define ADC_CR2_JEXTSEL_TIM8_CC4 0x4
+#define ADC_CR2_JEXTSEL_TIM5_TRGO 0x5
+#define ADC_CR2_JEXTSEL_TIM5_CC4 0x6
+
+#define ADC_CR2_ALIGN (1 << 11)
+#define ADC_CR2_DMA (1 << 8) /* ADC 1 & 3 only! */
+/* Bits [7:4] have to be kept 0. */
+#define ADC_CR2_RSTCAL (1 << 3)
+#define ADC_CR2_CAL (1 << 2)
+#define ADC_CR2_CONT (1 << 1)
+#define ADC_CR2_ADON (1 << 0) /* Must be separately written. */
+
+/* --- ADC_SMPR1 values ---------------------------------------------------- */
+
+#define ADC_SMPR1_SMP17_LSB 21
+#define ADC_SMPR1_SMP16_LSB 18
+#define ADC_SMPR1_SMP15_LSB 15
+#define ADC_SMPR1_SMP14_LSB 12
+#define ADC_SMPR1_SMP13_LSB 9
+#define ADC_SMPR1_SMP12_LSB 6
+#define ADC_SMPR1_SMP11_LSB 3
+#define ADC_SMPR1_SMP10_LSB 0
+#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB)
+#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB)
+#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB)
+#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB)
+#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB)
+#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB)
+#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB)
+#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB)
+#define ADC_SMPR1_SMP_1DOT5CYC 0x0
+#define ADC_SMPR1_SMP_7DOT5CYC 0x1
+#define ADC_SMPR1_SMP_13DOT5CYC 0x2
+#define ADC_SMPR1_SMP_28DOT5CYC 0x3
+#define ADC_SMPR1_SMP_41DOT5CYC 0x4
+#define ADC_SMPR1_SMP_55DOT5CYC 0x5
+#define ADC_SMPR1_SMP_71DOT5CYC 0x6
+#define ADC_SMPR1_SMP_239DOT5CYC 0x7
+
+/* --- ADC_SMPR2 values ---------------------------------------------------- */
+
+#define ADC_SMPR2_SMP9_LSB 27
+#define ADC_SMPR2_SMP8_LSB 24
+#define ADC_SMPR2_SMP7_LSB 21
+#define ADC_SMPR2_SMP6_LSB 18
+#define ADC_SMPR2_SMP5_LSB 15
+#define ADC_SMPR2_SMP4_LSB 12
+#define ADC_SMPR2_SMP3_LSB 9
+#define ADC_SMPR2_SMP2_LSB 6
+#define ADC_SMPR2_SMP1_LSB 3
+#define ADC_SMPR2_SMP0_LSB 0
+#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB)
+#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB)
+#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB)
+#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB)
+#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB)
+#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB)
+#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB)
+#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB)
+#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB)
+#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB)
+#define ADC_SMPR2_SMP_1DOT5CYC 0x0
+#define ADC_SMPR2_SMP_7DOT5CYC 0x1
+#define ADC_SMPR2_SMP_13DOT5CYC 0x2
+#define ADC_SMPR2_SMP_28DOT5CYC 0x3
+#define ADC_SMPR2_SMP_41DOT5CYC 0x4
+#define ADC_SMPR2_SMP_55DOT5CYC 0x5
+#define ADC_SMPR2_SMP_71DOT5CYC 0x6
+#define ADC_SMPR2_SMP_239DOT5CYC 0x7
+
+/* --- ADC_SMPRx generic values -------------------------------------------- */
+
+#define ADC_SMPR_SMP_1DOT5CYC 0x0
+#define ADC_SMPR_SMP_7DOT5CYC 0x1
+#define ADC_SMPR_SMP_13DOT5CYC 0x2
+#define ADC_SMPR_SMP_28DOT5CYC 0x3
+#define ADC_SMPR_SMP_41DOT5CYC 0x4
+#define ADC_SMPR_SMP_55DOT5CYC 0x5
+#define ADC_SMPR_SMP_71DOT5CYC 0x6
+#define ADC_SMPR_SMP_239DOT5CYC 0x7
+
+/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
+
+#define ADC_JOFFSET_LSB 0
+#define ADC_JOFFSET_MSK (0x7ff << 0)
+#define ADC_HT_LSB 0
+#define ADC_HT_MSK (0x7ff << 0)
+#define ADC_LT_LSB 0
+#define ADC_LT_MSK (0x7ff << 0)
+
+/* --- ADC_SQR1 values ----------------------------------------------------- */
+
+#define ADC_SQR1_L_LSB 20
+#define ADC_SQR1_SQ16_LSB 15
+#define ADC_SQR1_SQ15_LSB 10
+#define ADC_SQR1_SQ14_LSB 5
+#define ADC_SQR1_SQ13_LSB 0
+#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB)
+#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB)
+#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB)
+#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB)
+#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB)
+
+/* --- ADC_SQR2 values ----------------------------------------------------- */
+
+#define ADC_SQR2_SQ12_LSB 25
+#define ADC_SQR2_SQ11_LSB 20
+#define ADC_SQR2_SQ10_LSB 15
+#define ADC_SQR2_SQ9_LSB 10
+#define ADC_SQR2_SQ8_LSB 5
+#define ADC_SQR2_SQ7_LSB 0
+#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB)
+#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB)
+#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB)
+#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB)
+#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB)
+#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB)
+
+/* --- ADC_SQR3 values ----------------------------------------------------- */
+
+#define ADC_SQR3_SQ6_LSB 25
+#define ADC_SQR3_SQ5_LSB 20
+#define ADC_SQR3_SQ4_LSB 15
+#define ADC_SQR3_SQ3_LSB 10
+#define ADC_SQR3_SQ2_LSB 5
+#define ADC_SQR3_SQ1_LSB 0
+#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB)
+#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB)
+#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB)
+#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB)
+#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB)
+#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB)
+
+/* --- ADC_JSQR values ----------------------------------------------------- */
+
+#define ADC_JSQR_JL_LSB 20
+#define ADC_JSQR_JSQ4_LSB 15
+#define ADC_JSQR_JSQ3_LSB 10
+#define ADC_JSQR_JSQ2_LSB 5
+#define ADC_JSQR_JSQ1_LSB 0
+#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB)
+#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB)
+#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB)
+#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB)
+#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB)
+
+/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
+
+#define ADC_JDATA_LSB 0
+#define ADC_DATA_LSB 0
+#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */
+#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
+#define ADC_DATA_MSK (0xffff << ADC_DA)
+#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)
+ /* ADC1 only (dual mode) */
+
+/* --- Function prototypes ------------------------------------------------- */
+
+
+/* TODO */
+void adc_enable_analog_watchdog_regular(u32 adc);
+void adc_disable_analog_watchdog_regular(u32 adc);
+void adc_enable_analog_watchdog_injected(u32 adc);
+void adc_disable_analog_watchdog_injected(u32 adc);
+void adc_enable_discontinous_mode_regular(u32 adc);
+void adc_disable_discontinous_mode_regular(u32 adc);
+void adc_enable_discontinous_mode_injected(u32 adc);
+void adc_disable_discontinous_mode_injected(u32 adc);
+void adc_enable_automatic_injected_group_conversion(u32 adc);
+void adc_disable_automatic_injected_group_conversion(u32 adc);
+void adc_enable_analog_watchdog_on_all_channels(u32 adc);
+void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
+void adc_enable_scan_mode(u32 adc);
+void adc_disable_scan_mode(u32 adc);
+void adc_enable_jeoc_interrupt(u32 adc);
+void adc_disable_jeoc_interrupt(u32 adc);
+void adc_enable_awd_interrupt(u32 adc);
+void adc_disable_awd_interrupt(u32 adc);
+void adc_enable_eoc_interrupt(u32 adc);
+void adc_disable_eoc_interrupt(u32 adc);
+void adc_enable_temperature_sensor(u32 adc);
+void adc_disable_temperature_sensor(u32 adc);
+void adc_start_conversion_regular(u32 adc);
+void adc_start_conversion_injected(u32 adc);
+void adc_enable_external_trigger_regular(u32 adc, u8 trigger);
+void adc_disable_external_trigger_regular(u32 adc);
+void adc_enable_external_trigger_injected(u32 adc, u8 trigger);
+void adc_disable_external_trigger_injected(u32 adc);
+void adc_set_left_aligned(u32 adc);
+void adc_set_right_aligned(u32 adc);
+void adc_enable_dma(u32 adc);
+void adc_disable_dma(u32 adc);
+void adc_reset_calibration(u32 adc);
+void adc_calibration(u32 adc);
+void adc_set_continous_conversion_mode(u32 adc);
+void adc_set_single_conversion_mode(u32 adc);
+void adc_on(u32 adc);
+void adc_off(u32 adc);
+void adc_set_conversion_time(u32 adc, u8 channel, u8 time);
+void adc_set_conversion_time_on_all_channels(u32 adc, u8 time);
+void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
+void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
+void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
+void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
+
+#endif
diff --git a/include/libopencm3/stm32/bkp.h b/include/libopencm3/stm32/bkp.h
new file mode 100644
index 0000000..d700f9b
--- /dev/null
+++ b/include/libopencm3/stm32/bkp.h
@@ -0,0 +1,208 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_BKP_H
+#define LIBOPENCM3_BKP_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- BKP registers ------------------------------------------------------- */
+
+/* Backup data register 1 (BKP_DR1) */
+#define BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04)
+
+/* Backup data register 2 (BKP_DR2) */
+#define BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08)
+
+/* Backup data register 3 (BKP_DR3) */
+#define BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C)
+
+/* Backup data register 4 (BKP_DR4) */
+#define BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10)
+
+/* Backup data register 5 (BKP_DR5) */
+#define BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14)
+
+/* Backup data register 6 (BKP_DR6) */
+#define BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18)
+
+/* Backup data register 7 (BKP_DR7) */
+#define BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C)
+
+/* Backup data register 8 (BKP_DR8) */
+#define BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20)
+
+/* Backup data register 9 (BKP_DR9) */
+#define BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24)
+
+/* Backup data register 10 (BKP_DR10) */
+#define BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28)
+
+/* RTC clock calibration register (BKP_RTCCR) */
+#define BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C)
+
+/* Backup control register (BKP_CR) */
+#define BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30)
+
+/* Backup control/status register (BKP_CSR) */
+#define BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34)
+
+/* Backup data register 11 (BKP_DR11) */
+#define BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40)
+
+/* Backup data register 12 (BKP_DR12) */
+#define BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44)
+
+/* Backup data register 13 (BKP_DR13) */
+#define BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48)
+
+/* Backup data register 14 (BKP_DR14) */
+#define BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C)
+
+/* Backup data register 15 (BKP_DR15) */
+#define BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50)
+
+/* Backup data register 16 (BKP_DR16) */
+#define BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54)
+
+/* Backup data register 17 (BKP_DR17) */
+#define BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58)
+
+/* Backup data register 18 (BKP_DR18) */
+#define BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C)
+
+/* Backup data register 19 (BKP_DR19) */
+#define BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60)
+
+/* Backup data register 20 (BKP_DR20) */
+#define BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64)
+
+/* Backup data register 21 (BKP_DR21) */
+#define BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68)
+
+/* Backup data register 22 (BKP_DR22) */
+#define BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C)
+
+/* Backup data register 23 (BKP_DR23) */
+#define BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70)
+
+/* Backup data register 24 (BKP_DR24) */
+#define BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74)
+
+/* Backup data register 25 (BKP_DR25) */
+#define BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78)
+
+/* Backup data register 26 (BKP_DR26) */
+#define BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C)
+
+/* Backup data register 27 (BKP_DR27) */
+#define BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80)
+
+/* Backup data register 28 (BKP_DR28) */
+#define BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84)
+
+/* Backup data register 29 (BKP_DR29) */
+#define BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88)
+
+/* Backup data register 30 (BKP_DR30) */
+#define BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C)
+
+/* Backup data register 31 (BKP_DR31) */
+#define BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90)
+
+/* Backup data register 32 (BKP_DR32) */
+#define BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94)
+
+/* Backup data register 33 (BKP_DR33) */
+#define BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98)
+
+/* Backup data register 34 (BKP_DR34) */
+#define BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C)
+
+/* Backup data register 35 (BKP_DR35) */
+#define BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0)
+
+/* Backup data register 36 (BKP_DR36) */
+#define BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4)
+
+/* Backup data register 37 (BKP_DR37) */
+#define BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8)
+
+/* Backup data register 38 (BKP_DR38) */
+#define BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC)
+
+/* Backup data register 39 (BKP_DR39) */
+#define BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0)
+
+/* Backup data register 40 (BKP_DR40) */
+#define BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4)
+
+/* Backup data register 41 (BKP_DR41) */
+#define BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8)
+
+/* Backup data register 42 (BKP_DR42) */
+#define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC)
+
+/* --- BKP_RTCCR values ---------------------------------------------------- */
+
+/* ASOS: Alarm or second output selection */
+#define BKP_RTCCR_ASOS (1 << 9)
+
+/* ASOE: Alarm or second output enable */
+#define BKP_RTCCR_ASOE (1 << 8)
+
+/* CCO: Calibration clock output */
+#define BKP_RTCCR_CCO (1 << 7)
+
+/* CAL[6:0]: Calibration value */
+#define BKP_RTCCR_CAL_LSB 0
+
+/* --- BKP_CR values ------------------------------------------------------- */
+
+/* TPAL: TAMPER pin active level */
+#define BKP_CR_TAL (1 << 1)
+
+/* TPE: TAMPER pin enable */
+#define BKP_CR_TPE (1 << 0)
+
+/* --- BKP_CSR values ------------------------------------------------------ */
+
+/* TIF: Tamper interrupt flag */
+#define BKP_CSR_TIF (1 << 9)
+
+/* TEF: Tamper event flag */
+#define BKP_CSR_TEF (1 << 8)
+
+/* TPIE: TAMPER pin interrupt enable */
+#define BKP_CSR_TPIE (1 << 2)
+
+/* CTI: Clear tamper interrupt */
+#define BKP_CSR_CTI (1 << 1)
+
+/* CTE: Clear tamper event */
+#define BKP_CSR_CTE (1 << 0)
+
+/* --- BKP_DRx values ------------------------------------------------------ */
+
+/* Bits[15:0]: Backup data */
+
+/* --- BKP function prototypes --------------------------------------------- */
+
+#endif
diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h
new file mode 100644
index 0000000..1aa95a1
--- /dev/null
+++ b/include/libopencm3/stm32/can.h
@@ -0,0 +1,642 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CAN_H
+#define LIBOPENCM3_CAN_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* CAN register base adresses (for convenience) */
+#define CAN1 BX_CAN1_BASE
+#define CAN2 BX_CAN2_BASE
+
+/* --- CAN registers ------------------------------------------------------- */
+
+/* CAN master control register (CAN_MCR) */
+#define CAN_MCR(can_base) MMIO32(can_base + 0x000)
+/* CAN master status register (CAN_MSR) */
+#define CAN_MSR(can_base) MMIO32(can_base + 0x004)
+/* CAN transmit status register (CAN_TSR) */
+#define CAN_TSR(can_base) MMIO32(can_base + 0x008)
+
+/* CAN receive FIFO 0 register (CAN_RF0R) */
+#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C)
+/* CAN receive FIFO 1 register (CAN_RF1R) */
+#define CAN_RF1R(can_base) MMIO32(can_base + 0x010)
+
+/* CAN interrupt enable register (CAN_IER) */
+#define CAN_IER(can_base) MMIO32(can_base + 0x014)
+/* CAN error status register (CAN_ESR) */
+#define CAN_ESR(can_base) MMIO32(can_base + 0x018)
+/* CAN bit timing register (CAN_BTR) */
+#define CAN_BTR(can_base) MMIO32(can_base + 0x01C)
+
+/* Registers in the offset range 0x020 to 0x17F are reserved. */
+
+/* --- CAN mailbox registers ----------------------------------------------- */
+
+/* CAN mailbox / FIFO register offsets */
+#define CAN_MBOX0 0x180
+#define CAN_MBOX1 0x190
+#define CAN_MBOX2 0x1A0
+#define CAN_FIFO0 0x1B0
+#define CAN_FIFO1 0x1C0
+
+/* CAN TX mailbox identifier register (CAN_TIxR) */
+#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0)
+#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0)
+#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1)
+#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2)
+
+/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */
+#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4)
+#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0)
+#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1)
+#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2)
+
+/* CAN mailbox data low register (CAN_TDLxR) */
+#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8)
+#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0)
+#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1)
+#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2)
+
+/* CAN mailbox data high register (CAN_TDHxR) */
+#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC)
+#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0)
+#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1)
+#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2)
+
+/* CAN RX FIFO identifier register (CAN_RIxR) */
+#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0)
+#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0)
+#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1)
+
+/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */
+#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4)
+#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0)
+#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1)
+
+/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */
+#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8)
+#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0)
+#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1)
+
+/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */
+#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC)
+#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0)
+#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1)
+
+/* --- CAN filter registers ------------------------------------------------ */
+
+/* CAN filter master register (CAN_FMR) */
+#define CAN_FMR(can_base) MMIO32(can_base + 0x200)
+
+/* CAN filter mode register (CAN_FM1R) */
+#define CAN_FM1R(can_base) MMIO32(can_base + 0x204)
+
+/* Register offset 0x208 is reserved. */
+
+/* CAN filter scale register (CAN_FS1R) */
+#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C)
+
+/* Register offset 0x210 is reserved. */
+
+/* CAN filter FIFO assignement register (CAN_FFA1R) */
+#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214)
+
+/* Register offset 0x218 is reserved. */
+
+/* CAN filter activation register (CAN_FA1R) */
+#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C)
+
+/* Register offset 0x220 is reserved. */
+
+/* Registers with offset 0x224 to 0x23F are reserved. */
+
+/* CAN filter bank registers (CAN_FiRx) */
+/*
+ * Connectivity line devices have 28 banks so the bank ID spans 0..27
+ * all other devices have 14 banks so the bank ID spans 0..13.
+ */
+#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0)
+#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4)
+
+/* --- CAN_MCR values ------------------------------------------------------ */
+
+/* 31:17 Reserved, forced by hardware to 0 */
+
+/* DBF: Debug freeze */
+#define CAN_MCR_DBF (1 << 16)
+
+/* RESET: bxCAN software master reset */
+#define CAN_MCR_RESET (1 << 15)
+
+/* 14:8 Reserved, forced by hardware to 0 */
+
+/* TTCM: Time triggered communication mode */
+#define CAN_MCR_TTCM (1 << 7)
+
+/* ABOM: Automatic bus-off management */
+#define CAN_MCR_ABOM (1 << 6)
+
+/* AWUM: Automatic wakeup mode */
+#define CAN_MCR_AWUM (1 << 5)
+
+/* NART: No automatic retransmission */
+#define CAN_MCR_NART (1 << 4)
+
+/* RFLM: Receive FIFO locked mode */
+#define CAN_MCR_RFLM (1 << 3)
+
+/* TXFP: Transmit FIFO priority */
+#define CAN_MCR_TXFP (1 << 2)
+
+/* SLEEP: Sleep mode request */
+#define CAN_MCR_SLEEP (1 << 1)
+
+/* INRQ: Initialization request */
+#define CAN_MCR_INRQ (1 << 0)
+
+/* --- CAN_MSR values ------------------------------------------------------ */
+
+/* 31:12 Reserved, forced by hardware to 0 */
+
+/* RX: CAN Rx signal */
+#define CAN_MSR_RX (1 << 11)
+
+/* SAMP: Last sample point */
+#define CAN_MSR_SAMP (1 << 10)
+
+/* RXM: Receive mode */
+#define CAN_MSR_RXM (1 << 9)
+
+/* TXM: Transmit mode */
+#define CAN_MSR_TXM (1 << 8)
+
+/* 7:5 Reserved, forced by hardware to 0 */
+
+/* SLAKI: Sleep acknowledge interrupt */
+#define CAN_MSR_SLAKI (1 << 4)
+
+/* WKUI: Wakeup interrupt */
+#define CAN_MSR_WKUI (1 << 3)
+
+/* ERRI: Error interrupt */
+#define CAN_MSR_ERRI (1 << 2)
+
+/* SLAK: Sleep acknowledge */
+#define CAN_MSR_SLAK (1 << 1)
+
+/* INAK: Initialization acknowledge */
+#define CAN_MSR_INAK (1 << 0)
+
+/* --- CAN_TSR values ------------------------------------------------------ */
+
+/* LOW2: Lowest priority flag for mailbox 2 */
+#define CAN_TSR_LOW2 (1 << 31)
+
+/* LOW1: Lowest priority flag for mailbox 1 */
+#define CAN_TSR_LOW1 (1 << 30)
+
+/* LOW0: Lowest priority flag for mailbox 0 */
+#define CAN_TSR_LOW0 (1 << 29)
+
+/* TME2: Transmit mailbox 2 empty */
+#define CAN_TSR_TME2 (1 << 28)
+
+/* TME1: Transmit mailbox 1 empty */
+#define CAN_TSR_TME1 (1 << 27)
+
+/* TME0: Transmit mailbox 0 empty */
+#define CAN_TSR_TME0 (1 << 26)
+
+/* CODE[1:0]: Mailbox code */
+#define CAN_TSR_CODE_MASK (0x3 << 24)
+
+/* ABRQ2: Abort request for mailbox 2 */
+#define CAN_TSR_TABRQ2 (1 << 23)
+
+/* 22:20 Reserved, forced by hardware to 0 */
+
+/* TERR2: Transmission error for mailbox 2 */
+#define CAN_TSR_TERR2 (1 << 19)
+
+/* ALST2: Arbitration lost for mailbox 2 */
+#define CAN_TSR_ALST2 (1 << 18)
+
+/* TXOK2: Transmission OK for mailbox 2 */
+#define CAN_TSR_TXOK2 (1 << 17)
+
+/* RQCP2: Request completed mailbox 2 */
+#define CAN_TSR_RQCP2 (1 << 16)
+
+/* ABRQ1: Abort request for mailbox 1 */
+#define CAN_TSR_ABRQ1 (1 << 15)
+
+/* 14:12 Reserved, forced by hardware to 0 */
+
+/* TERR1: Transmission error for mailbox 1 */
+#define CAN_TSR_TERR1 (1 << 11)
+
+/* ALST1: Arbitration lost for mailbox 1 */
+#define CAN_TSR_ALST1 (1 << 10)
+
+/* TXOK1: Transmission OK for mailbox 1 */
+#define CAN_TSR_TXOK1 (1 << 9)
+
+/* RQCP1: Request completed mailbox 1 */
+#define CAN_TSR_RQCP1 (1 << 8)
+
+/* ABRQ0: Abort request for mailbox 0 */
+#define CAN_TSR_ABRQ0 (1 << 7)
+
+/* 6:4 Reserved, forced by hardware to 0 */
+
+/* TERR0: Transmission error for mailbox 0 */
+#define CAN_TSR_TERR0 (1 << 3)
+
+/* ALST0: Arbitration lost for mailbox 0 */
+#define CAN_TSR_ALST0 (1 << 2)
+
+/* TXOK0: Transmission OK for mailbox 0 */
+#define CAN_TSR_TXOK0 (1 << 1)
+
+/* RQCP0: Request completed mailbox 0 */
+#define CAN_TSR_RQCP0 (1 << 0)
+
+/* --- CAN_RF0R values ----------------------------------------------------- */
+
+/* 31:6 Reserved, forced by hardware to 0 */
+
+/* RFOM0: Release FIFO 0 output mailbox */
+#define CAN_RF0R_RFOM0 (1 << 5)
+
+/* FOVR0: FIFO 0 overrun */
+#define CAN_RF0R_FAVR0 (1 << 4)
+
+/* FULL0: FIFO 0 full */
+#define CAN_RF0R_FULL0 (1 << 3)
+
+/* 2 Reserved, forced by hardware to 0 */
+
+/* FMP0[1:0]: FIFO 0 message pending */
+#define CAN_RF0R_FMP0_MASK (0x3 << 0)
+
+/* --- CAN_RF1R values ----------------------------------------------------- */
+
+/* 31:6 Reserved, forced by hardware to 0 */
+
+/* RFOM1: Release FIFO 1 output mailbox */
+#define CAN_RF1R_RFOM1 (1 << 5)
+
+/* FOVR1: FIFO 1 overrun */
+#define CAN_RF1R_FAVR1 (1 << 4)
+
+/* FULL1: FIFO 1 full */
+#define CAN_RF1R_FULL1 (1 << 3)
+
+/* 2 Reserved, forced by hardware to 0 */
+
+/* FMP1[1:0]: FIFO 1 message pending */
+#define CAN_RF1R_FMP1_MASK (0x3 << 0)
+
+/* --- CAN_IER values ------------------------------------------------------ */
+
+/* 32:18 Reserved, forced by hardware to 0 */
+
+/* SLKIE: Sleep interrupt enable */
+#define CAN_IER_SLKIE (1 << 17)
+
+/* WKUIE: Wakeup interrupt enable */
+#define CAN_IER_WKUIE (1 << 16)
+
+/* ERRIE: Error interrupt enable */
+#define CAN_IER_ERRIE (1 << 15)
+
+/* 14:12 Reserved, forced by hardware to 0 */
+
+/* LECIE: Last error code interrupt enable */
+#define CAN_IER_LECIE (1 << 11)
+
+/* BOFIE: Bus-off interrupt enable */
+#define CAN_IER_BOFIE (1 << 10)
+
+/* EPVIE: Error passive interrupt enable */
+#define CAN_IER_EPVIE (1 << 9)
+
+/* EWGIE: Error warning interrupt enable */
+#define CAN_IER_EWGIE (1 << 8)
+
+/* 7 Reserved, forced by hardware to 0 */
+
+/* FOVIE1: FIFO overrun interrupt enable */
+#define CAN_IER_FOVIE1 (1 << 6)
+
+/* FFIE1: FIFO full interrupt enable */
+#define CAN_IER_FFIE1 (1 << 5)
+
+/* FMPIE1: FIFO message pending interrupt enable */
+#define CAN_IER_FMPIE1 (1 << 4)
+
+/* FOVIE0: FIFO overrun interrupt enable */
+#define CAN_IER_FOVIE0 (1 << 3)
+
+/* FFIE0: FIFO full interrupt enable */
+#define CAN_IER_FFIE0 (1 << 2)
+
+/* FMPIE0: FIFO message pending interrupt enable */
+#define CAN_IER_FMPIE0 (1 << 1)
+
+/* TMEIE: Transmit mailbox empty interrupt enable */
+#define CAN_IER_TMEIE (1 << 0)
+
+/* --- CAN_ESR values ------------------------------------------------------ */
+
+/* REC[7:0]: Receive error counter */
+#define CAN_ESR_REC_MASK (0xF << 24)
+
+/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */
+#define CAN_ESR_TEC_MASK (0xF << 16)
+
+/* 15:7 Reserved, forced by hardware to 0 */
+
+/* LEC[2:0]: Last error code */
+#define CAN_ESR_LEC_NO_ERROR (0x0 << 4)
+#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4)
+#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4)
+#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4)
+#define CAN_ESR_LEC_REC_ERROR (0x4 << 4)
+#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4)
+#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4)
+#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4)
+#define CAN_ESR_LEC_MASK (0x7 << 4)
+
+/* 3 Reserved, forced by hardware to 0 */
+
+/* BOFF: Bus-off flag */
+#define CAN_ESR_BOFF (1 << 2)
+
+/* EPVF: Error passive flag */
+#define CAN_ESR_EPVF (1 << 1)
+
+/* EWGF: Error warning flag */
+#define CAN_ESR_EWGF (1 << 0)
+
+/* --- CAN_BTR values ------------------------------------------------------ */
+
+/* SILM: Silent mode (debug) */
+#define CAN_BTR_SILM (1 << 31)
+
+/* LBKM: Loop back mode (debug) */
+#define CAN_BTR_LBKM (1 << 30)
+
+/* 29:26 Reserved, forced by hardware to 0 */
+
+/* SJW[1:0]: Resynchronization jump width */
+#define CAN_BTR_SJW_1TQ (0x0 << 24)
+#define CAN_BTR_SJW_2TQ (0x1 << 24)
+#define CAN_BTR_SJW_3TQ (0x2 << 24)
+#define CAN_BTR_SJW_4TQ (0x3 << 24)
+#define CAN_BTR_SJW_MASK (0x3 << 24)
+
+/* 23 Reserved, forced by hardware to 0 */
+
+/* TS2[2:0]: Time segment 2 */
+#define CAN_BTR_TS2_1TQ (0x0 << 20)
+#define CAN_BTR_TS2_2TQ (0x1 << 20)
+#define CAN_BTR_TS2_3TQ (0x2 << 20)
+#define CAN_BTR_TS2_4TQ (0x3 << 20)
+#define CAN_BTR_TS2_5TQ (0x4 << 20)
+#define CAN_BTR_TS2_6TQ (0x5 << 20)
+#define CAN_BTR_TS2_7TQ (0x6 << 20)
+#define CAN_BTR_TS2_8TQ (0x7 << 20)
+#define CAN_BTR_TS2_MASK (0x7 << 20)
+
+/* TS1[3:0]: Time segment 1 */
+#define CAN_BTR_TS1_1TQ (0x0 << 16)
+#define CAN_BTR_TS1_2TQ (0x1 << 16)
+#define CAN_BTR_TS1_3TQ (0x2 << 16)
+#define CAN_BTR_TS1_4TQ (0x3 << 16)
+#define CAN_BTR_TS1_5TQ (0x4 << 16)
+#define CAN_BTR_TS1_6TQ (0x5 << 16)
+#define CAN_BTR_TS1_7TQ (0x6 << 16)
+#define CAN_BTR_TS1_8TQ (0x7 << 16)
+#define CAN_BTR_TS1_9TQ (0x8 << 16)
+#define CAN_BTR_TS1_10TQ (0x9 << 16)
+#define CAN_BTR_TS1_11TQ (0xA << 16)
+#define CAN_BTR_TS1_12TQ (0xB << 16)
+#define CAN_BTR_TS1_13TQ (0xC << 16)
+#define CAN_BTR_TS1_14TQ (0xD << 16)
+#define CAN_BTR_TS1_15TQ (0xE << 16)
+#define CAN_BTR_TS1_16TQ (0xF << 16)
+#define CAN_BTR_TS1_MASK (0xF << 16)
+
+/* 15:10 Reserved, forced by hardware to 0 */
+
+/* BRP[9:0]: Baud rate prescaler */
+#define CAN_BTR_BRP_MASK (0x1FF << 0)
+
+/* --- CAN_TIxR values ------------------------------------------------------ */
+
+/* STID[10:0]: Standard identifier */
+#define CAN_TIxR_STID_MASK (0x3FF << 21)
+#define CAN_TIxR_STID_SHIFT 21
+
+/* EXID[15:0]: Extended identifier */
+#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3)
+#define CAN_TIxR_EXID_SHIFT 3
+
+/* IDE: Identifier extension */
+#define CAN_TIxR_IDE (1 << 2)
+
+/* RTR: Remote transmission request */
+#define CAN_TIxR_RTR (1 << 1)
+
+/* TXRQ: Transmit mailbox request */
+#define CAN_TIxR_TXRQ (1 << 0)
+
+/* --- CAN_TDTxR values ----------------------------------------------------- */
+
+/* TIME[15:0]: Message time stamp */
+#define CAN_TDTxR_TIME_MASK (0xFFFF << 15)
+#define CAN_TDTxR_TIME_SHIFT 15
+
+/* 15:6 Reserved, forced by hardware to 0 */
+
+/* TGT: Transmit global time */
+#define CAN_TDTxR_TGT (1 << 5)
+
+/* 7:4 Reserved, forced by hardware to 0 */
+
+/* DLC[3:0]: Data length code */
+#define CAN_TDTxR_DLC_MASK (0xF << 0)
+#define CAN_TDTxR_DLC_SHIFT 0
+
+/* --- CAN_TDLxR values ----------------------------------------------------- */
+
+/* DATA3[7:0]: Data byte 3 */
+/* DATA2[7:0]: Data byte 2 */
+/* DATA1[7:0]: Data byte 1 */
+/* DATA0[7:0]: Data byte 0 */
+
+/* --- CAN_TDHxR values ----------------------------------------------------- */
+
+/* DATA7[7:0]: Data byte 7 */
+/* DATA6[7:0]: Data byte 6 */
+/* DATA5[7:0]: Data byte 5 */
+/* DATA4[7:0]: Data byte 4 */
+
+/* --- CAN_RIxR values ------------------------------------------------------ */
+
+/* STID[10:0]: Standard identifier */
+#define CAN_RIxR_STID_MASK (0x3FF << 21)
+#define CAN_RIxR_STID_SHIFT 21
+
+/* EXID[15:0]: Extended identifier */
+#define CAN_RIxR_EXID_MASK (0x1FFFFFF << 3)
+#define CAN_RIxR_EXID_SHIFT 3
+
+/* IDE: Identifier extension */
+#define CAN_RIxR_IDE (1 << 2)
+
+/* RTR: Remote transmission request */
+#define CAN_RIxR_RTR (1 << 1)
+
+/* 0 Reserved */
+
+/* --- CAN_RDTxR values ----------------------------------------------------- */
+
+/* TIME[15:0]: Message time stamp */
+#define CAN_RDTxR_TIME_MASK (0xFFFF << 15)
+#define CAN_RDTxR_TIME_SHIFT 15
+
+/* FMI[7:0]: Filter match index */
+#define CAN_RDTxR_FMI_MASK (0xFF << 8)
+#define CAN_RDTxR_FMI_SHIFT 8
+
+/* 7:4 Reserved, forced by hardware to 0 */
+
+/* DLC[3:0]: Data length code */
+#define CAN_RDTxR_DLC_MASK (0xF << 0)
+#define CAN_RDTxR_DLC_SHIFT 0
+
+/* --- CAN_RDLxR values ----------------------------------------------------- */
+
+/* DATA3[7:0]: Data byte 3 */
+/* DATA2[7:0]: Data byte 2 */
+/* DATA1[7:0]: Data byte 1 */
+/* DATA0[7:0]: Data byte 0 */
+
+/* --- CAN_RDHxR values ----------------------------------------------------- */
+
+/* DATA7[7:0]: Data byte 7 */
+/* DATA6[7:0]: Data byte 6 */
+/* DATA5[7:0]: Data byte 5 */
+/* DATA4[7:0]: Data byte 4 */
+
+/* --- CAN_FMR values ------------------------------------------------------- */
+
+/* 31:14 Reserved, forced to reset value */
+
+/*
+ * CAN2SB[5:0]: CAN2 start bank
+ * (only on connectivity line devices otherwise reserved)
+ */
+#define CAN_FMR_CAN2SB_MASK (0x3F << 8)
+#define CAN_FMR_CAN2SB_SHIFT 15
+
+/* 7:1 Reserved, forced to reset value */
+
+/* FINIT: Filter init mode */
+#define CAN_FMR_FINIT (1 << 0)
+
+/* --- CAN_FM1R values ------------------------------------------------------ */
+
+/* 31:28 Reserved, forced by hardware to 0 */
+
+/*
+ * FBMx: Filter mode
+ * x is 0..27 should be calculated by a helper function making so many macros
+ * seems like an overkill?
+ */
+
+/* --- CAN_FS1R values ------------------------------------------------------ */
+
+/* 31:28 Reserved, forced by hardware to 0 */
+
+/*
+ * FSCx: Filter scale configuration
+ * x is 0..27 should be calculated by a helper function making so many macros
+ * seems like an overkill?
+ */
+
+/* --- CAN_FFA1R values ----------------------------------------------------- */
+
+/* 31:28 Reserved, forced by hardware to 0 */
+
+/*
+ * FFAx: Filter scale configuration
+ * x is 0..27 should be calculated by a helper function making so many macros
+ * seems like an overkill?
+ */
+
+/* --- CAN_FA1R values ------------------------------------------------------ */
+
+/* 31:28 Reserved, forced by hardware to 0 */
+
+/*
+ * FACTx: Filter active
+ * x is 0..27 should be calculated by a helper function making so many macros
+ * seems like an overkill?
+ */
+
+/* --- CAN_FiRx values ------------------------------------------------------ */
+
+/* FB[31:0]: Filter bits */
+
+/* --- CAN functions -------------------------------------------------------- */
+
+void can_reset(u32 canport);
+int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
+ bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp);
+
+void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
+ u32 fr1, u32 fr2, u32 fifo, bool enable);
+void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
+ u16 id2, u16 mask2, u32 fifo, bool enable);
+void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
+ u32 fifo, bool enable);
+void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
+ u16 id3, u16 id4, u32 fifo, bool enable);
+void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
+ u32 fifo, bool enable);
+
+void can_enable_irq(u32 canport, u32 irq);
+void can_disable_irq(u32 canport, u32 irq);
+
+int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data);
+void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
+ bool *rtr, u32 *fmi, u8 *length, u8 *data);
+
+void can_fifo_release(u32 canport, u8 fifo);
+
+#endif
diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h
new file mode 100644
index 0000000..5ad866e
--- /dev/null
+++ b/include/libopencm3/stm32/crc.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CRC_H
+#define LIBOPENCM3_CRC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- CRC registers ------------------------------------------------------- */
+
+/* Data register (CRC_DR) */
+#define CRC_DR MMIO32(CRC_BASE + 0x00)
+
+/* Independent data register (CRC_IDR) */
+#define CRC_IDR MMIO32(CRC_BASE + 0x04)
+
+/* Control register (CRC_CR) */
+#define CRC_CR MMIO32(CRC_BASE + 0x08)
+
+/* --- CRC_DR values ------------------------------------------------------- */
+
+/* Bits[31:0] Data register */
+
+/* --- CRC_IDR values ------------------------------------------------------ */
+
+/* Bits[7:0] General-purpose 8-bit data register bits */
+
+/* --- CRC_CR values ------------------------------------------------------- */
+
+/* RESET bit */
+#define CRC_CR_RESET (1 << 0)
+
+/* --- CRC function prototypes --------------------------------------------- */
+
+#endif
diff --git a/include/libopencm3/stm32/dma.h b/include/libopencm3/stm32/dma.h
new file mode 100644
index 0000000..7d0a856
--- /dev/null
+++ b/include/libopencm3/stm32/dma.h
@@ -0,0 +1,723 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_DMA_H
+#define LIBOPENCM3_DMA_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* DMA register base adresses (for convenience) */
+#define DMA1 DMA1_BASE
+#define DMA2 DMA2_BASE
+
+/* --- DMA registers ------------------------------------------------------- */
+
+/* DMA interrupt status register (DMAx_ISR) */
+#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00)
+#define DMA1_ISR DMA_ISR(DMA1)
+#define DMA2_ISR DMA_ISR(DMA2)
+
+/* DMA interrupt flag clear register (DMAx_IFCR) */
+#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04)
+#define DMA1_IFCR DMA_IFCR(DMA1)
+#define DMA2_IFCR DMA_IFCR(DMA2)
+
+/* DMA channel 1 configuration register (DMAx_CCR1) */
+#define DMA_CCR1(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 0)
+#define DMA1_CCR1 DMA_CCR1(DMA1)
+#define DMA2_CCR1 DMA_CCR1(DMA2)
+
+/* DMA channel 2 configuration register (DMAx_CCR2) */
+#define DMA_CCR2(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 1)
+#define DMA1_CCR2 DMA_CCR2(DMA1)
+#define DMA2_CCR2 DMA_CCR2(DMA2)
+
+/* DMA channel 3 configuration register (DMAx_CCR3) */
+#define DMA_CCR3(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 2)
+#define DMA1_CCR3 DMA_CCR3(DMA1)
+#define DMA2_CCR3 DMA_CCR3(DMA2)
+
+/* DMA channel 4 configuration register (DMAx_CCR4) */
+#define DMA_CCR4(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 3)
+#define DMA1_CCR4 DMA_CCR4(DMA1)
+#define DMA2_CCR4 DMA_CCR4(DMA2)
+
+/* DMA channel 5 configuration register (DMAx_CCR5) */
+#define DMA_CCR5(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 4)
+#define DMA1_CCR5 DMA_CCR5(DMA1)
+#define DMA2_CCR5 DMA_CCR5(DMA2)
+
+/* DMA channel 6 configuration register (DMAx_CCR6) */
+#define DMA_CCR6(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 5)
+#define DMA1_CCR6 DMA_CCR6(DMA1)
+
+/* DMA channel 7 configuration register (DMAx_CCR7) */
+#define DMA_CCR7(dma_base) MMIO32(dma_base + 0x08 + 0x14 * 6)
+#define DMA1_CCR7 DMA_CCR7(DMA1)
+
+/* DMA channel 1 number of data register (DMAx_CNDTR1) */
+#define DMA_CNDTR1(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 0)
+#define DMA1_CNDTR1 DMA_CNDTR1(DMA1)
+#define DMA2_CNDTR1 DMA_CNDTR1(DMA2)
+
+/* DMA channel 2 number of data register (DMAx_CNDTR2) */
+#define DMA_CNDTR2(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 1)
+#define DMA1_CNDTR2 DMA_CNDTR2(DMA1)
+#define DMA2_CNDTR2 DMA_CNDTR2(DMA2)
+
+/* DMA channel 3 number of data register (DMAx_CNDTR3) */
+#define DMA_CNDTR3(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 2)
+#define DMA1_CNDTR3 DMA_CNDTR3(DMA1)
+#define DMA2_CNDTR3 DMA_CNDTR3(DMA2)
+
+/* DMA channel 4 number of data register (DMAx_CNDTR4) */
+#define DMA_CNDTR4(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 3)
+#define DMA1_CNDTR4 DMA_CNDTR4(DMA1)
+#define DMA2_CNDTR4 DMA_CNDTR4(DMA2)
+
+/* DMA channel 5 number of data register (DMAx_CNDTR5) */
+#define DMA_CNDTR5(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 4)
+#define DMA1_CNDTR5 DMA_CNDTR5(DMA1)
+#define DMA2_CNDTR5 DMA_CNDTR5(DMA2)
+
+/* DMA channel 6 number of data register (DMAx_CNDTR6) */
+#define DMA_CNDTR6(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 5)
+#define DMA1_CNDTR6 DMA_CNDTR6(DMA1)
+
+/* DMA channel 7 number of data register (DMAx_CNDTR7) */
+#define DMA_CNDTR7(dma_base) MMIO32(dma_base + 0x0C + 0x14 * 6)
+#define DMA1_CNDTR7 DMA_CNDTR7(DMA1)
+
+/* DMA channel 1 peripheral address register (DMAx_CPAR1) */
+#define DMA_CPAR1(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 0)
+#define DMA1_CPAR1 DMA_CPAR1(DMA1)
+#define DMA2_CPAR1 DMA_CPAR1(DMA2)
+
+/* DMA channel 2 peripheral address register (DMAx_CPAR2) */
+#define DMA_CPAR2(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 1)
+#define DMA1_CPAR2 DMA_CPAR2(DMA1)
+#define DMA2_CPAR2 DMA_CPAR2(DMA2)
+
+/* DMA channel 3 peripheral address register (DMAx_CPAR3) */
+#define DMA_CPAR3(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 2)
+#define DMA1_CPAR3 DMA_CPAR3(DMA1)
+#define DMA2_CPAR3 DMA_CPAR3(DMA2)
+
+/* DMA channel 4 peripheral address register (DMAx_CPAR4) */
+#define DMA_CPAR4(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 3)
+#define DMA1_CPAR4 DMA_CPAR4(DMA1)
+#define DMA2_CPAR4 DMA_CPAR4(DMA2)
+
+/* DMA channel 5 peripheral address register (DMAx_CPAR5) */
+#define DMA_CPAR5(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 4)
+#define DMA1_CPAR5 DMA_CPAR5(DMA1)
+#define DMA2_CPAR5 DMA_CPAR5(DMA2)
+
+/* DMA channel 6 peripheral address register (DMAx_CPAR6) */
+#define DMA_CPAR6(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 5)
+#define DMA1_CPAR6 DMA_CPAR6(DMA1)
+
+/* DMA channel 7 peripheral address register (DMAx_CPAR7) */
+#define DMA_CPAR7(dma_base) MMIO32(dma_base + 0x10 + 0x14 * 6)
+#define DMA1_CPAR7 DMA_CPAR7(DMA1)
+
+/* DMA channel 1 memory address register (DMAx_CMAR1) */
+#define DMA_CMAR1(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 0)
+#define DMA1_CMAR1 DMA_CMAR1(DMA1)
+#define DMA2_CMAR1 DMA_CMAR1(DMA2)
+
+/* DMA channel 2 memory address register (DMAx_CMAR2) */
+#define DMA_CMAR2(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 1)
+#define DMA1_CMAR2 DMA_CMAR2(DMA1)
+#define DMA2_CMAR2 DMA_CMAR2(DMA2)
+
+/* DMA channel 3 memory address register (DMAx_CMAR3) */
+#define DMA_CMAR3(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 2)
+#define DMA1_CMAR3 DMA_CMAR3(DMA1)
+#define DMA2_CMAR3 DMA_CMAR3(DMA2)
+
+/* DMA channel 4 memory address register (DMAx_CMAR4) */
+#define DMA_CMAR4(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 3)
+#define DMA1_CMAR4 DMA_CMAR4(DMA1)
+#define DMA2_CMAR4 DMA_CMAR4(DMA2)
+
+/* DMA channel 5 memory address register (DMAx_CMAR5) */
+#define DMA_CMAR5(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 4)
+#define DMA1_CMAR5 DMA_CMAR5(DMA1)
+#define DMA2_CMAR5 DMA_CMAR5(DMA2)
+
+/* DMA channel 6 memory address register (DMAx_CMAR6) */
+#define DMA_CMAR6(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 5)
+#define DMA1_CMAR6 DMA_CMAR6(DMA1)
+
+/* DMA channel 7 memory address register (DMAx_CMAR7) */
+#define DMA_CMAR7(dma_base) MMIO32(dma_base + 0x14 + 0x14 * 6)
+#define DMA1_CMAR7 DMA_CMAR7(DMA1)
+
+/* --- DMA_ISR values ------------------------------------------------------ */
+
+/* TEIF7: Channel 7 transfer error flag */
+#define DMA_ISR_TEIF7 (1 << 27)
+/* HTIF7: Channel 7 half transfer flag */
+#define DMA_ISR_HTIF7 (1 << 26)
+/* TCIF7: Channel 7 transfer complete flag */
+#define DMA_ISR_TCIF7 (1 << 25)
+/* GIF7: Channel 7 global interrupt flag */
+#define DMA_ISR_GIF7 (1 << 24)
+/* TEIF6: Channel 6 transfer error flag */
+#define DMA_ISR_TEIF6 (1 << 23)
+/* HTIF6: Channel 6 half transfer flag */
+#define DMA_ISR_HTIF6 (1 << 22)
+/* TCIF6: Channel 6 transfer complete flag */
+#define DMA_ISR_TCIF6 (1 << 21)
+/* GIF6: Channel 6 global interrupt flag */
+#define DMA_ISR_GIF6 (1 << 20)
+/* TEIF5: Channel 5 transfer error flag */
+#define DMA_ISR_TEIF5 (1 << 19)
+/* HTIF5: Channel 5 half transfer flag */
+#define DMA_ISR_HTIF5 (1 << 18)
+/* TCIF5: Channel 5 transfer complete flag */
+#define DMA_ISR_TCIF5 (1 << 17)
+/* GIF5: Channel 5 global interrupt flag */
+#define DMA_ISR_GIF5 (1 << 16)
+/* TEIF4: Channel 4 transfer error flag */
+#define DMA_ISR_TEIF4 (1 << 15)
+/* HTIF4: Channel 4 half transfer flag */
+#define DMA_ISR_HTIF4 (1 << 14)
+/* TCIF4: Channel 4 transfer complete flag */
+#define DMA_ISR_TCIF4 (1 << 13)
+/* GIF4: Channel 4 global interrupt flag */
+#define DMA_ISR_GIF4 (1 << 12)
+/* TEIF3: Channel 3 transfer error flag */
+#define DMA_ISR_TEIF3 (1 << 11)
+/* HTIF3: Channel 3 half transfer flag */
+#define DMA_ISR_HTIF3 (1 << 10)
+/* TCIF3: Channel 3 transfer complete flag */
+#define DMA_ISR_TCIF3 (1 << 9)
+/* GIF3: Channel 3 global interrupt flag */
+#define DMA_ISR_GIF3 (1 << 8)
+/* TEIF2: Channel 2 transfer error flag */
+#define DMA_ISR_TEIF2 (1 << 7)
+/* HTIF2: Channel 23 half transfer flag */
+#define DMA_ISR_HTIF2 (1 << 6)
+/* TCIF2: Channel 2 transfer complete flag */
+#define DMA_ISR_TCIF2 (1 << 5)
+/* GIF2: Channel 2 global interrupt flag */
+#define DMA_ISR_GIF2 (1 << 4)
+/* TEIF1: Channel 1 transfer error flag */
+#define DMA_ISR_TEIF1 (1 << 3)
+/* HTIF1: Channel 1 half transfer flag */
+#define DMA_ISR_HTIF1 (1 << 2)
+/* TCIF1: Channel 1 transfer complete flag */
+#define DMA_ISR_TCIF1 (1 << 1)
+/* GIF1: Channel 1 global interrupt flag */
+#define DMA_ISR_GIF1 (1 << 0)
+
+/* --- DMA_IFCR values ----------------------------------------------------- */
+
+/* CTEIF7: Channel 7 transfer error clear */
+#define DMA_IFCR_CTEIF7 (1 << 27)
+/* CHTIF7: Channel 7 half transfer clear */
+#define DMA_IFCR_CHTIF7 (1 << 26)
+/* CTCIF7: Channel 7 transfer complete clear */
+#define DMA_IFCR_CTCIF7 (1 << 25)
+/* CGIF7: Channel 7 global interrupt clear */
+#define DMA_IFCR_CGIF7 (1 << 24)
+/* CTEIF6: Channel 6 transfer error clear */
+#define DMA_IFCR_CTEIF6 (1 << 23)
+/* CHTIF6: Channel 6 half transfer clear */
+#define DMA_IFCR_CHTIF6 (1 << 22)
+/* CTCIF6: Channel 6 transfer complete clear */
+#define DMA_IFCR_CTCIF6 (1 << 21)
+/* CGIF6: Channel 6 global interrupt clear */
+#define DMA_IFCR_CGIF6 (1 << 20)
+/* CTEIF5: Channel 5 transfer error clear */
+#define DMA_IFCR_CTEIF5 (1 << 19)
+/* CHTIF5: Channel 5 half transfer clear */
+#define DMA_IFCR_CHTIF5 (1 << 18)
+/* CTCIF5: Channel 5 transfer complete clear */
+#define DMA_IFCR_CTCIF5 (1 << 17)
+/* CGIF5: Channel 5 global interrupt clear */
+#define DMA_IFCR_CGIF5 (1 << 16)
+/* CTEIF4: Channel 4 transfer error clear */
+#define DMA_IFCR_CTEIF4 (1 << 15)
+/* CHTIF4: Channel 4 half transfer clear */
+#define DMA_IFCR_CHTIF4 (1 << 14)
+/* CTCIF4: Channel 4 transfer complete clear */
+#define DMA_IFCR_CTCIF4 (1 << 13)
+/* CGIF4: Channel 4 global interrupt clear */
+#define DMA_IFCR_CGIF4 (1 << 12)
+/* CTEIF3: Channel 3 transfer error clear */
+#define DMA_IFCR_CTEIF3 (1 << 11)
+/* CHTIF3: Channel 3 half transfer clear */
+#define DMA_IFCR_CHTIF3 (1 << 10)
+/* CTCIF3: Channel 3 transfer complete clear */
+#define DMA_IFCR_CTCIF3 (1 << 9)
+/* CGIF3: Channel 3 global interrupt clear */
+#define DMA_IFCR_CGIF3 (1 << 8)
+/* CTEIF2: Channel 2 transfer error clear */
+#define DMA_IFCR_CTEIF2 (1 << 7)
+/* CHTIF2: Channel 2 half transfer clear */
+#define DMA_IFCR_CHTIF2 (1 << 6)
+/* CTCIF2: Channel 2 transfer complete clear */
+#define DMA_IFCR_CTCIF2 (1 << 5)
+/* CGIF2: Channel 2 global interrupt clear */
+#define DMA_IFCR_CGIF2 (1 << 4)
+/* CTEIF1: Channel 1 transfer error clear */
+#define DMA_IFCR_CTEIF1 (1 << 3)
+/* CHTIF1: Channel 1 half transfer clear */
+#define DMA_IFCR_CHTIF1 (1 << 2)
+/* CTCIF1: Channel 1 transfer complete clear */
+#define DMA_IFCR_CTCIF1 (1 << 1)
+/* CGIF1: Channel 1 global interrupt clear */
+#define DMA_IFCR_CGIF1 (1 << 0)
+
+/* --- DMA_CCR1 values ----------------------------------------------------- */
+
+/* MEM2MEM: Memory to memory mode */
+#define DMA_CCR1_MEM2MEM (1 << 14)
+
+/* PL[13:12]: Channel priority level */
+#define DMA_CCR1_PL_LSB 12
+#define DMA_CCR1_PL_LOW 0x0
+#define DMA_CCR1_PL_MEDIUM 0x1
+#define DMA_CCR1_PL_HIGH 0x2
+#define DMA_CCR1_PL_VERY_HIGH 0x3
+
+/* MSIZE[11:10]: Memory size */
+#define DMA_CCR1_MSIZE_LSB 10
+#define DMA_CCR1_MSIZE_8BIT 0x0
+#define DMA_CCR1_MSIZE_16BIT 0x1
+#define DMA_CCR1_MSIZE_32BIT 0x2
+
+/* PSIZE[9:8]: Peripheral size */
+#define DMA_CCR1_PSIZE_LSB 8
+#define DMA_CCR1_PSIZE_8BIT 0x0
+#define DMA_CCR1_PSIZE_16BIT 0x1
+#define DMA_CCR1_PSIZE_32BIT 0x2
+
+/* MINC: Memory increment mode */
+#define DMA_CCR1_MINC (1 << 7)
+
+/* PINC: Peripheral increment mode */
+#define DMA_CCR1_PINC (1 << 6)
+
+/* CIRC: Circular mode */
+#define DMA_CCR1_CIRC (1 << 5)
+
+/* DIR: Data transfer direction */
+#define DMA_CCR1_DIR (1 << 4)
+
+/* TEIE: Transfer error interrupt enable */
+#define DMA_CCR1_TEIE (1 << 3)
+
+/* HTIE: Half transfer interrupt enable */
+#define DMA_CCR1_HTIE (1 << 2)
+
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_CCR1_TCIE (1 << 1)
+
+/* EN: Channel enable */
+#define DMA_CCR1_EN (1 << 0)
+
+/* --- DMA_CCR2 values ----------------------------------------------------- */
+
+/* MEM2MEM: Memory to memory mode */
+#define DMA_CCR2_MEM2MEM (1 << 14)
+
+/* PL[13:12]: Channel priority level */
+#define DMA_CCR2_PL_LSB 12
+#define DMA_CCR2_PL_LOW 0x0
+#define DMA_CCR2_PL_MEDIUM 0x1
+#define DMA_CCR2_PL_HIGH 0x2
+#define DMA_CCR2_PL_VERY_HIGH 0x3
+
+/* MSIZE[11:10]: Memory size */
+#define DMA_CCR2_MSIZE_LSB 10
+#define DMA_CCR2_MSIZE_8BIT 0x0
+#define DMA_CCR2_MSIZE_16BIT 0x1
+#define DMA_CCR2_MSIZE_32BIT 0x2
+
+/* PSIZE[9:8]: Peripheral size */
+#define DMA_CCR2_PSIZE_LSB 8
+#define DMA_CCR2_PSIZE_8BIT 0x0
+#define DMA_CCR2_PSIZE_16BIT 0x1
+#define DMA_CCR2_PSIZE_32BIT 0x2
+
+/* MINC: Memory increment mode */
+#define DMA_CCR2_MINC (1 << 7)
+
+/* PINC: Peripheral increment mode */
+#define DMA_CCR2_PINC (1 << 6)
+
+/* CIRC: Circular mode */
+#define DMA_CCR2_CIRC (1 << 5)
+
+/* DIR: Data transfer direction */
+#define DMA_CCR2_DIR (1 << 4)
+
+/* TEIE: Transfer error interrupt enable */
+#define DMA_CCR2_TEIE (1 << 3)
+
+/* HTIE: Half transfer interrupt enable */
+#define DMA_CCR2_HTIE (1 << 2)
+
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_CCR2_TCIE (1 << 1)
+
+/* EN: Channel enable */
+#define DMA_CCR2_EN (1 << 0)
+
+/* --- DMA_CCR3 values ----------------------------------------------------- */
+
+/* MEM2MEM: Memory to memory mode */
+#define DMA_CCR3_MEM2MEM (1 << 14)
+
+/* PL[13:12]: Channel priority level */
+#define DMA_CCR3_PL_LSB 12
+#define DMA_CCR3_PL_LOW 0x0
+#define DMA_CCR3_PL_MEDIUM 0x1
+#define DMA_CCR3_PL_HIGH 0x2
+#define DMA_CCR3_PL_VERY_HIGH 0x3
+
+/* MSIZE[11:10]: Memory size */
+#define DMA_CCR3_MSIZE_LSB 10
+#define DMA_CCR3_MSIZE_8BIT 0x0
+#define DMA_CCR31_MSIZE_16BIT 0x1
+#define DMA_CCR3_MSIZE_32BIT 0x2
+
+/* PSIZE[9:8]: Peripheral size */
+#define DMA_CCR3_PSIZE_LSB 8
+#define DMA_CCR3_PSIZE_8BIT 0x0
+#define DMA_CCR3_PSIZE_16BIT 0x1
+#define DMA_CCR3_PSIZE_32BIT 0x2
+
+/* MINC: Memory increment mode */
+#define DMA_CCR3_MINC (1 << 7)
+
+/* PINC: Peripheral increment mode */
+#define DMA_CCR3_PINC (1 << 6)
+
+/* CIRC: Circular mode */
+#define DMA_CCR3_CIRC (1 << 5)
+
+/* DIR: Data transfer direction */
+#define DMA_CCR3_DIR (1 << 4)
+
+/* TEIE: Transfer error interrupt enable */
+#define DMA_CCR3_TEIE (1 << 3)
+
+/* HTIE: Half transfer interrupt enable */
+#define DMA_CCR3_HTIE (1 << 2)
+
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_CCR3_TCIE (1 << 1)
+
+/* EN: Channel enable */
+#define DMA_CCR3_EN (1 << 0)
+
+/* --- DMA_CCR4 values ----------------------------------------------------- */
+
+/* MEM2MEM: Memory to memory mode */
+#define DMA_CCR4_MEM2MEM (1 << 14)
+
+/* PL[13:12]: Channel priority level */
+#define DMA_CCR4_PL_LSB 12
+#define DMA_CCR4_PL_LOW 0x0
+#define DMA_CCR4_PL_MEDIUM 0x1
+#define DMA_CCR4_PL_HIGH 0x2
+#define DMA_CCR4_PL_VERY_HIGH 0x3
+
+/* MSIZE[11:10]: Memory size */
+#define DMA_CCR4_MSIZE_LSB 10
+#define DMA_CCR4_MSIZE_8BIT 0x0
+#define DMA_CCR4_MSIZE_16BIT 0x1
+#define DMA_CCR4_MSIZE_32BIT 0x2
+
+/* PSIZE[9:8]: Peripheral size */
+#define DMA_CCR4_PSIZE_LSB 8
+#define DMA_CCR4_PSIZE_8BIT 0x0
+#define DMA_CCR4_PSIZE_16BIT 0x1
+#define DMA_CCR4_PSIZE_32BIT 0x2
+
+/* MINC: Memory increment mode */
+#define DMA_CCR4_MINC (1 << 7)
+
+/* PINC: Peripheral increment mode */
+#define DMA_CCR4_PINC (1 << 6)
+
+/* CIRC: Circular mode */
+#define DMA_CCR4_CIRC (1 << 5)
+
+/* DIR: Data transfer direction */
+#define DMA_CCR4_DIR (1 << 4)
+
+/* TEIE: Transfer error interrupt enable */
+#define DMA_CCR4_TEIE (1 << 3)
+
+/* HTIE: Half transfer interrupt enable */
+#define DMA_CCR4_HTIE (1 << 2)
+
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_CCR4_TCIE (1 << 1)
+
+/* EN: Channel enable */
+#define DMA_CCR4_EN (1 << 0)
+
+/* --- DMA_CCR5 values ----------------------------------------------------- */
+
+/* MEM2MEM: Memory to memory mode */
+#define DMA_CCR5_MEM2MEM (1 << 14)
+
+/* PL[13:12]: Channel priority level */
+#define DMA_CCR5_PL_LSB 12
+#define DMA_CCR5_PL_LOW 0x0
+#define DMA_CCR5_PL_MEDIUM 0x1
+#define DMA_CCR5_PL_HIGH 0x2
+#define DMA_CCR5_PL_VERY_HIGH 0x3
+
+/* MSIZE[11:10]: Memory size */
+#define DMA_CCR5_MSIZE_LSB 10
+#define DMA_CCR5_MSIZE_8BIT 0x0
+#define DMA_CCR5_MSIZE_16BIT 0x1
+#define DMA_CCR5_MSIZE_32BIT 0x2
+
+/* PSIZE[9:8]: Peripheral size */
+#define DMA_CCR5_PSIZE_LSB 8
+#define DMA_CCR5_PSIZE_8BIT 0x0
+#define DMA_CCR5_PSIZE_16BIT 0x1
+#define DMA_CCR5_PSIZE_32BIT 0x2
+
+/* MINC: Memory increment mode */
+#define DMA_CCR5_MINC (1 << 7)
+
+/* PINC: Peripheral increment mode */
+#define DMA_CCR5_PINC (1 << 6)
+
+/* CIRC: Circular mode */
+#define DMA_CCR5_CIRC (1 << 5)
+
+/* DIR: Data transfer direction */
+#define DMA_CCR5_DIR (1 << 4)
+
+/* TEIE: Transfer error interrupt enable */
+#define DMA_CCR5_TEIE (1 << 3)
+
+/* HTIE: Half transfer interrupt enable */
+#define DMA_CCR5_HTIE (1 << 2)
+
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_CCR5_TCIE (1 << 1)
+
+/* EN: Channel enable */
+#define DMA_CCR5_EN (1 << 0)
+
+/* --- DMA_CCR6 values ----------------------------------------------------- */
+
+/* MEM2MEM: Memory to memory mode */
+#define DMA_CCR6_MEM2MEM (1 << 14)
+
+/* PL[13:12]: Channel priority level */
+#define DMA_CCR6_PL_LSB 12
+#define DMA_CCR6_PL_LOW 0x0
+#define DMA_CCR6_PL_MEDIUM 0x1
+#define DMA_CCR6_PL_HIGH 0x2
+#define DMA_CCR6_PL_VERY_HIGH 0x3
+
+/* MSIZE[11:10]: Memory size */
+#define DMA_CCR6_MSIZE_LSB 10
+#define DMA_CCR6_MSIZE_8BIT 0x0
+#define DMA_CCR6_MSIZE_16BIT 0x1
+#define DMA_CCR6_MSIZE_32BIT 0x2
+
+/* PSIZE[9:8]: Peripheral size */
+#define DMA_CCR6_PSIZE_LSB 8
+#define DMA_CCR6_PSIZE_8BIT 0x0
+#define DMA_CCR6_PSIZE_16BIT 0x1
+#define DMA_CCR6_PSIZE_32BIT 0x2
+
+/* MINC: Memory increment mode */
+#define DMA_CCR6_MINC (1 << 7)
+
+/* PINC: Peripheral increment mode */
+#define DMA_CCR6_PINC (1 << 6)
+
+/* CIRC: Circular mode */
+#define DMA_CCR6_CIRC (1 << 5)
+
+/* DIR: Data transfer direction */
+#define DMA_CCR6_DIR (1 << 4)
+
+/* TEIE: Transfer error interrupt enable */
+#define DMA_CCR6_TEIE (1 << 3)
+
+/* HTIE: Half transfer interrupt enable */
+#define DMA_CCR6_HTIE (1 << 2)
+
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_CCR6_TCIE (1 << 1)
+
+/* EN: Channel enable */
+#define DMA_CCR6_EN (1 << 0)
+
+/* --- DMA_CCR7 values ----------------------------------------------------- */
+
+/* MEM2MEM: Memory to memory mode */
+#define DMA_CCR7_MEM2MEM (1 << 14)
+
+/* PL[13:12]: Channel priority level */
+#define DMA_CCR7_PL_LSB 12
+#define DMA_CCR7_PL_LOW 0x0
+#define DMA_CCR7_PL_MEDIUM 0x1
+#define DMA_CCR7_PL_HIGH 0x2
+#define DMA_CCR7_PL_VERY_HIGH 0x3
+
+/* MSIZE[11:10]: Memory size */
+#define DMA_CCR7_MSIZE_LSB 10
+#define DMA_CCR7_MSIZE_8BIT 0x0
+#define DMA_CCR7_MSIZE_16BIT 0x1
+#define DMA_CCR7_MSIZE_32BIT 0x2
+
+/* PSIZE[9:8]: Peripheral size */
+#define DMA_CCR7_PSIZE_LSB 8
+#define DMA_CCR7_PSIZE_8BIT 0x0
+#define DMA_CCR7_PSIZE_16BIT 0x1
+#define DMA_CCR7_PSIZE_32BIT 0x2
+
+/* MINC: Memory increment mode */
+#define DMA_CCR7_MINC (1 << 7)
+
+/* PINC: Peripheral increment mode */
+#define DMA_CCR7_PINC (1 << 6)
+
+/* CIRC: Circular mode */
+#define DMA_CCR7_CIRC (1 << 5)
+
+/* DIR: Data transfer direction */
+#define DMA_CCR7_DIR (1 << 4)
+
+/* TEIE: Transfer error interrupt enable */
+#define DMA_CCR7_TEIE (1 << 3)
+
+/* HTIE: Half transfer interrupt enable */
+#define DMA_CCR7_HTIE (1 << 2)
+
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_CCR7_TCIE (1 << 1)
+
+/* EN: Channel enable */
+#define DMA_CCR7_EN (1 << 0)
+
+/* --- DMA_CCRx generic values --------------------------------------------- */
+
+/* MEM2MEM: Memory to memory mode */
+#define DMA_CCR_MEM2MEM (1 << 14)
+
+/* PL[13:12]: Channel priority level */
+#define DMA_CCR_PL_LSB 12
+#define DMA_CCR_PL_LOW 0x0
+#define DMA_CCR_PL_MEDIUM 0x1
+#define DMA_CCR_PL_HIGH 0x2
+#define DMA_CCR_PL_VERY_HIGH 0x3
+
+/* MSIZE[11:10]: Memory size */
+#define DMA_CCR_MSIZE_LSB 10
+#define DMA_CCR_MSIZE_8BIT 0x0
+#define DMA_CCR_MSIZE_16BIT 0x1
+#define DMA_CCR_MSIZE_32BIT 0x2
+
+/* PSIZE[9:8]: Peripheral size */
+#define DMA_CCR_PSIZE_LSB 8
+#define DMA_CCR_PSIZE_8BIT 0x0
+#define DMA_CCR_PSIZE_16BIT 0x1
+#define DMA_CCR_PSIZE_32BIT 0x2
+
+/* MINC: Memory increment mode */
+#define DMA_CCR_MINC (1 << 7)
+
+/* PINC: Peripheral increment mode */
+#define DMA_CCR_PINC (1 << 6)
+
+/* CIRC: Circular mode */
+#define DMA_CCR_CIRC (1 << 5)
+
+/* DIR: Data transfer direction */
+#define DMA_CCR_DIR (1 << 4)
+
+/* TEIE: Transfer error interrupt enable */
+#define DMA_CCR_TEIE (1 << 3)
+
+/* HTIE: Half transfer interrupt enable */
+#define DMA_CCR_HTIE (1 << 2)
+
+/* TCIE: Transfer complete interrupt enable */
+#define DMA_CCR_TCIE (1 << 1)
+
+/* EN: Channel enable */
+#define DMA_CCR_EN (1 << 0)
+
+/* --- DMA_CNDTRx values --------------------------------------------------- */
+
+/* NDT[15:0]: Number of data to transfer */
+
+/* --- DMA_CPARx values ---------------------------------------------------- */
+
+/* PA[31:0]: Peripheral address */
+
+/* --- DMA_CMARx values ---------------------------------------------------- */
+
+/* MA[31:0]: Memory address */
+
+/* --- Generic values ------------------------------------------------------ */
+
+#define DMA_CHANNEL1 1
+#define DMA_CHANNEL2 2
+#define DMA_CHANNEL3 3
+#define DMA_CHANNEL4 4
+#define DMA_CHANNEL5 5
+#define DMA_CHANNEL6 6
+#define DMA_CHANNEL7 7
+
+/* --- function prototypes ------------------------------------------------- */
+
+void dma_enable_mem2mem_mode(u32 dma, u8 channel);
+void dma_set_priority(u32 dma, u8 channel, u8 prio);
+void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size);
+void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size);
+void dma_enable_memory_increment_mode(u32 dma, u8 channel);
+void dma_enable_peripheral_increment_mode(u32 dma, u8 channel);
+void dma_enable_circular_mode(u32 dma, u8 channel);
+void dma_set_read_from_peripheral(u32 dma, u8 channel);
+void dma_set_read_from_memory(u32 dma, u8 channel);
+void dma_enable_transfer_error_interrupt(u32 dma, u8 channel);
+void dma_disable_transfer_error_interrupt(u32 dma, u8 channel);
+void dma_enable_half_transfer_interrupt(u32 dma, u8 channel);
+void dma_disable_half_transfer_interrupt(u32 dma, u8 channel);
+void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel);
+void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel);
+void dma_enable_channel(u32 dma, u8 channel);
+void dma_disable_channel(u32 dma, u8 channel);
+void dma_set_peripheral_address(u32 dma, u8 channel, u32 address);
+void dma_set_memory_address(u32 dma, u8 channel, u32 address);
+void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
+
+#endif
diff --git a/include/libopencm3/stm32/ethernet.h b/include/libopencm3/stm32/ethernet.h
new file mode 100644
index 0000000..3d7f1ee
--- /dev/null
+++ b/include/libopencm3/stm32/ethernet.h
@@ -0,0 +1,203 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_ETHERNET_H
+#define LIBOPENCM3_ETHERNET_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* Ethernet MAC registers */
+#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00)
+#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04)
+#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08)
+#define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C)
+#define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10)
+#define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14)
+#define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18)
+#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C)
+#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28)
+#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C)
+#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38)
+#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C)
+#define ETH_MACA0HR MMIO32(ETHERNET_BASE + 0x40)
+#define ETH_MACA0LR MMIO32(ETHERNET_BASE + 0x44)
+#define ETH_MACA1HR MMIO32(ETHERNET_BASE + 0x48)
+#define ETH_MACA1LR MMIO32(ETHERNET_BASE + 0x4C)
+#define ETH_MACA2HR MMIO32(ETHERNET_BASE + 0x50)
+#define ETH_MACA2LR MMIO32(ETHERNET_BASE + 0x54)
+#define ETH_MACA3HR MMIO32(ETHERNET_BASE + 0x58)
+#define ETH_MACA3LR MMIO32(ETHERNET_BASE + 0x5C)
+
+/* Ethernet MMC registers */
+#define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100)
+#define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104)
+#define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108)
+#define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C)
+#define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110)
+#define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C)
+#define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150)
+#define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168)
+#define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194)
+#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198)
+#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4)
+
+/* Ethrenet IEEE 1588 time stamp registers */
+#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700)
+#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704)
+#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708)
+#define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C)
+#define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710)
+#define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714)
+#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718)
+#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C)
+#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720)
+
+/* Ethernet DMA registers */
+#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000)
+#define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004)
+#define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008)
+#define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C)
+#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010)
+#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010)
+#define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014)
+#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018)
+#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C)
+#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020)
+#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048)
+#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C)
+#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050)
+#define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054)
+
+/* Ethernet MAC Register bit definitions */
+/* Ethernet MAC configuration register ETH_MACCR bits */
+#define ETH_MACCR_RE 0x00000004
+#define ETH_MACCR_TE 0x00000008
+#define ETH_MACCR_DC 0x00000010
+#define ETH_MACCR_BL 0x00000060
+#define ETH_MACCR_APCS 0x00000080
+#define ETH_MACCR_RD 0x00000200
+#define ETH_MACCR_IPCO 0x00000400
+#define ETH_MACCR_DM 0x00000800
+#define ETH_MACCR_LM 0x00001000
+#define ETH_MACCR_ROD 0x00002000
+#define ETH_MACCR_FES 0x00004000
+#define ETH_MACCR_CSD 0x00010000
+#define ETH_MACCR_IFG 0x000E0000
+#define ETH_MACCR_JD 0x00400000
+#define ETH_MACCR_WD 0x00800000
+
+/* Ethernet MAC frame filter register ETH_MACFFR bits */
+#define ETH_MACFFR_PM 0x00000001
+#define ETH_MACFFR_HU 0x00000002
+#define ETH_MACFFR_HM 0x00000004
+#define ETH_MACFFR_DAIF 0x00000008
+#define ETH_MACFFR_PAM 0x00000010
+#define ETH_MACFFR_BFD 0x00000020
+#define ETH_MACFFR_PCF 0x000000C0
+#define ETH_MACFFR_SAIF 0x00000100
+#define ETH_MACFFR_SAF 0x00000200
+#define ETH_MACFFR_HPF 0x00000400
+#define ETH_MACFFR_PA 0x80000000
+
+/* Ethernet MAC MII address register ETH_MACMIIAR bits */
+#define ETH_MACMIIAR_MB 0x0001
+#define ETH_MACMIIAR_MW 0x0002
+/* Clock Range for MDC frequency */
+#define ETH_MACMIIAR_CR_MASK 0x001C
+#define ETH_MACMIIAR_CR_HCLK_DIV_42 0x0000 /* For HCLK 60-72 MHz */
+#define ETH_MACMIIAR_CR_HCLK_DIV_16 0x0008 /* For HCLK 20-35 MHz */
+#define ETH_MACMIIAR_CR_HCLK_DIV_24 0x000C /* For HCLK 35-60 MHz */
+#define ETH_MACMIIAR_MR 0x07C0
+#define ETH_MACMIIAR_PA 0xF800
+
+/* Ethernet MAC flow control register ETH_MACFCR bits */
+#define ETH_MACFCR_FCB 0x00000001
+#define ETH_MACFCR_BPA 0x00000001
+#define ETH_MACFCR_TFCE 0x00000002
+#define ETH_MACFCR_RFCE 0x00000004
+#define ETH_MACFCR_UPFD 0x00000008
+#define ETH_MACFCR_PLT 0x00000030
+#define ETH_MACFCR_ZQPD 0x00000080
+#define ETH_MACFCR_PT 0xFFFF0000
+
+/* Ethernet MAC interrupt status regster ETH_MACSR bits */
+#define ETH_MACSR_PMTS 0x0008
+#define ETH_MACSR_MMCS 0x0010
+#define ETH_MACSR_MMCRS 0x0020
+#define ETH_MACSR_MMCTS 0x0040
+#define ETH_MACSR_TSTS 0x0200
+
+/* Ethernet MAC interrupt mask regster ETH_MACIMR bits */
+#define ETH_MACIMR_PMTIM 0x0008
+#define ETH_MACIMR_TSTIM 0x0200
+
+/* Ethernet DMA Register bit definitions */
+/* Ethernet DMA bus mode register ETH_DMABMR bits */
+#define ETH_DMABMR_SR 0x00000001
+#define ETH_DMABMR_DA 0x00000002
+#define ETH_DMABMR_DSL_MASK 0x0000007C
+#define ETH_DMABMR_PBL_MASK 0x00003F00
+#define ETH_DMABMR_RTPR_MASK 0x0000C000
+#define ETH_DMABMR_RTPR_1TO1 0x00000000
+#define ETH_DMABMR_RTPR_2TO1 0x00004000
+#define ETH_DMABMR_RTPR_3TO1 0x00008000
+#define ETH_DMABMR_RTPR_4TO1 0x0000C000
+#define ETH_DMABMR_FB 0x00010000
+#define ETH_DMABMR_RDP_MASK 0x007E0000
+#define ETH_DMABMR_USP 0x00800000
+#define ETH_DMABMR_FPM 0x01000000
+#define ETH_DMABMR_AAB 0x02000000
+
+/* Ethernet DMA operation mode register ETH_DMAOMR bits */
+#define ETH_DMAOMR_SR 0x00000002
+#define ETH_DMAOMR_OSF 0x00000004
+#define ETH_DMAOMR_RTC_MASK 0x00000018
+#define ETH_DMAOMR_RTC_64 0x00000000
+#define ETH_DMAOMR_RTC_32 0x00000008
+#define ETH_DMAOMR_RTC_96 0x00000010
+#define ETH_DMAOMR_RTC_128 0x00000018
+#define ETH_DMAOMR_FUGF 0x00000040
+#define ETH_DMAOMR_FEF 0x00000080
+#define ETH_DMAOMR_ST 0x00002000
+#define ETH_DMAOMR_TTC_MASK 0x0001C000
+#define ETH_DMAOMR_FTF 0x00100000
+#define ETH_DMAOMR_TSF 0x00200000
+#define ETH_DMAOMR_DFRF 0x01000000
+#define ETH_DMAOMR_RSF 0x02000000
+#define ETH_DMAOMR_DTCEFD 0x04000000
+
+/* Ethernet DMA interrupt enable register ETH_DMAIER bits */
+#define ETH_DMAIER_TIE 0x00000001
+#define ETH_DMAIER_TPSIE 0x00000002
+#define ETH_DMAIER_TBUIE 0x00000004
+#define ETH_DMAIER_TJTIE 0x00000008
+#define ETH_DMAIER_ROIE 0x00000010
+#define ETH_DMAIER_TUIE 0x00000020
+#define ETH_DMAIER_RIE 0x00000040
+#define ETH_DMAIER_RBUIE 0x00000080
+#define ETH_DMAIER_RPSIE 0x00000100
+#define ETH_DMAIER_RWTIE 0x00000200
+#define ETH_DMAIER_ETIE 0x00000400
+#define ETH_DMAIER_FBEIE 0x00002000
+#define ETH_DMAIER_ERIE 0x00004000
+#define ETH_DMAIER_AISE 0x00008000
+#define ETH_DMAIER_NSIE 0x00010000
+
+#endif
diff --git a/include/libopencm3/stm32/exti.h b/include/libopencm3/stm32/exti.h
new file mode 100644
index 0000000..19ab547
--- /dev/null
+++ b/include/libopencm3/stm32/exti.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_EXTI_H
+#define LIBOPENCM3_EXTI_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- EXTI registers ------------------------------------------------------ */
+
+#define EXTI_IMR MMIO32(EXTI_BASE + 0x00)
+#define EXTI_EMR MMIO32(EXTI_BASE + 0x04)
+#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08)
+#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c)
+#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10)
+#define EXTI_PR MMIO32(EXTI_BASE + 0x14)
+
+/* EXTI number definitions */
+#define EXTI0 (1 << 0)
+#define EXTI1 (1 << 1)
+#define EXTI2 (1 << 2)
+#define EXTI3 (1 << 3)
+#define EXTI4 (1 << 4)
+#define EXTI5 (1 << 5)
+#define EXTI6 (1 << 6)
+#define EXTI7 (1 << 7)
+#define EXTI8 (1 << 8)
+#define EXTI9 (1 << 9)
+#define EXTI10 (1 << 10)
+#define EXTI11 (1 << 11)
+#define EXTI12 (1 << 12)
+#define EXTI13 (1 << 13)
+#define EXTI14 (1 << 14)
+#define EXTI15 (1 << 15)
+#define EXTI16 (1 << 16)
+#define EXTI17 (1 << 17)
+#define EXTI18 (1 << 18)
+#define EXTI19 (1 << 19)
+
+/* Trigger types */
+typedef enum trigger_e {
+ EXTI_TRIGGER_RISING,
+ EXTI_TRIGGER_FALLING,
+ EXTI_TRIGGER_BOTH,
+} exti_trigger_type;
+
+void exti_set_trigger(u32 extis, exti_trigger_type trig);
+void exti_enable_request(u32 extis);
+void exti_disable_request(u32 extis);
+void exti_reset_request(u32 extis);
+void exti_select_source(u32 exti, u32 gpioport);
+
+#endif
diff --git a/include/libopencm3/stm32/flash.h b/include/libopencm3/stm32/flash.h
new file mode 100644
index 0000000..f9b2aa9
--- /dev/null
+++ b/include/libopencm3/stm32/flash.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ * Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * For details see:
+ * PM0042 Programming manual: STM32F10xxx Flash programming
+ * October 2009, Doc ID 13259 Rev 7
+ * http://www.st.com/stonline/products/literature/pm/13259.pdf
+ */
+
+#ifndef LIBOPENCM3_FLASH_H
+#define LIBOPENCM3_FLASH_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- FLASH registers ----------------------------------------------------- */
+
+#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
+#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
+#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
+#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
+#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
+#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
+#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C)
+#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
+
+/* --- FLASH_ACR values ---------------------------------------------------- */
+
+#define FLASH_PRFTBS (1 << 5)
+#define FLASH_PRFTBE (1 << 4)
+#define FLASH_HLFCYA (1 << 3)
+#define FLASH_LATENCY_0WS 0x00
+#define FLASH_LATENCY_1WS 0x01
+#define FLASH_LATENCY_2WS 0x02
+
+/* --- FLASH_SR values ----------------------------------------------------- */
+
+#define FLASH_EOP (1 << 5)
+#define FLASH_WRPRTERR (1 << 4)
+#define FLASH_PGERR (1 << 2)
+#define FLASH_BSY (1 << 0)
+
+/* --- FLASH_CR values ----------------------------------------------------- */
+
+#define FLASH_EOPIE (1 << 12)
+#define FLASH_ERRIE (1 << 10)
+#define FLASH_OPTWRE (1 << 9)
+#define FLASH_LOCK (1 << 7)
+#define FLASH_STRT (1 << 6)
+#define FLASH_OPTER (1 << 5)
+#define FLASH_OPTPG (1 << 4)
+#define FLASH_MER (1 << 2)
+#define FLASH_PER (1 << 1)
+#define FLASH_PG (1 << 0)
+
+/* --- FLASH_OBR values ---------------------------------------------------- */
+
+/* FLASH_OBR[25:18]: Data1 */
+/* FLASH_OBR[17:10]: Data0 */
+#define FLASH_NRST_STDBY (1 << 4)
+#define FLASH_NRST_STOP (1 << 3)
+#define FLASH_WDG_SW (1 << 2)
+#define FLASH_RDPRT (1 << 1)
+#define FLASH_OPTERR (1 << 0)
+
+/* --- FLASH Keys -----------------------------------------------------------*/
+
+#define RDP_KEY ((u16)0x00a5)
+#define FLASH_KEY1 ((u32)0x45670123)
+#define FLASH_KEY2 ((u32)0xcdef89ab)
+
+/* --- Function prototypes ------------------------------------------------- */
+
+void flash_prefetch_buffer_enable(void);
+void flash_prefetch_buffer_disable(void);
+void flash_halfcycle_enable(void);
+void flash_halfcycle_disable(void);
+void flash_set_ws(u32 ws);
+void flash_unlock(void);
+void flash_lock(void);
+void flash_clear_pgerr_flag(void);
+void flash_clear_eop_flag(void);
+void flash_clear_wrprterr_flag(void);
+void flash_clear_bsy_flag(void);
+void flash_clear_status_flags(void);
+void flash_unlock_option_bytes(void);
+void flash_erase_all_pages(void);
+void flash_erase_page(u32 page_address);
+void flash_program_word(u32 address, u32 data);
+void flash_program_half_word(u32 address, u16 data);
+void flash_wait_for_last_operation(void);
+void flash_erase_option_bytes(void);
+void flash_program_option_bytes(u32 address, u16 data);
+
+#endif
diff --git a/include/libopencm3/stm32/fsmc.h b/include/libopencm3/stm32/fsmc.h
new file mode 100644
index 0000000..1d318e3
--- /dev/null
+++ b/include/libopencm3/stm32/fsmc.h
@@ -0,0 +1,284 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_FSMC_H
+#define LIBOPENCM3_FSMC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* TODO: Move to memorymap.h? */
+#define FSMC_BASE 0xa0000000
+
+#define FSMC_BANK1_BASE 0x60000000 /* NOR / PSRAM */
+#define FSMC_BANK2_BASE 0x70000000 /* NAND flash */
+#define FSMC_BANK3_BASE 0x80000000 /* NAND flash */
+#define FSMC_BANK4_BASE 0x90000000 /* PC card */
+
+/* --- FSMC registers ------------------------------------------------------ */
+
+/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */
+#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x)
+#define FSMC_BCR1 FSMC_BCR(0)
+#define FSMC_BCR2 FSMC_BCR(1)
+#define FSMC_BCR3 FSMC_BCR(2)
+#define FSMC_BCR4 FSMC_BCR(3)
+
+/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */
+#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x)
+#define FSMC_BTR1 FSMC_BTR(0)
+#define FSMC_BTR2 FSMC_BTR(1)
+#define FSMC_BTR3 FSMC_BTR(2)
+#define FSMC_BTR4 FSMC_BTR(3)
+
+/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */
+#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x)
+#define FSMC_BWTR1 FSMC_BWTR(0)
+#define FSMC_BWTR2 FSMC_BWTR(1)
+#define FSMC_BWTR3 FSMC_BWTR(2)
+#define FSMC_BWTR4 FSMC_BWTR(3)
+
+/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */
+#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x)
+#define FSMC_PCR2 FSMC_PCR(1)
+#define FSMC_PCR3 FSMC_PCR(2)
+#define FSMC_PCR4 FSMC_PCR(3)
+
+/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */
+#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x)
+#define FSMC_SR2 FSMC_SR(1)
+#define FSMC_SR3 FSMC_SR(2)
+#define FSMC_SR4 FSMC_SR(3)
+
+/* Common memory space timing registers 2..4 (FSMC_PMEMx) */
+#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x)
+#define FSMC_PMEM2 FSMC_PMEM(1)
+#define FSMC_PMEM3 FSMC_PMEM(2)
+#define FSMC_PMEM4 FSMC_PMEM(3)
+
+/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */
+#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x)
+#define FSMC_PATT2 FSMC_PATT(1)
+#define FSMC_PATT3 FSMC_PATT(2)
+#define FSMC_PATT4 FSMC_PATT(3)
+
+/* I/O space timing register 4 (FSMC_PIO4) */
+#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0)
+
+/* ECC result registers 2/3 (FSMC_ECCRx) */
+#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x)
+#define FSMC_ECCR2 FSMC_ECCR(1)
+#define FSMC_ECCR3 FSMC_ECCR(2)
+
+/* --- FSMC_BCRx values ---------------------------------------------------- */
+
+/* CBURSTRW: Write burst enable */
+#define FSMC_BCR_CBURSTRW (1 << 19)
+
+/* Bits 18..16: Reserved. */
+
+/* ASYNCWAIT: Wait signal during asynchronous transfers */
+#define FSMC_BCR_ASYNCWAIT (1 << 15)
+
+/* EXTMOD: Extended mode enable */
+#define FSMC_BCR_EXTMOD (1 << 14)
+
+/* WAITEN: Wait enable bit */
+#define FSMC_BCR_WAITEN (1 << 13)
+
+/* WREN: Write enable bit */
+#define FSMC_BCR_WREN (1 << 12)
+
+/* WAITCFG: Wait timing configuration */
+#define FSMC_BCR_WAITCFG (1 << 11)
+
+/* WRAPMOD: Wrapped burst mode support */
+#define FSMC_BCR_WRAPMOD (1 << 10)
+
+/* WAITPOL: Wait signal polarity bit */
+#define FSMC_BCR_WAITPOL (1 << 9)
+
+/* BURSTEN: Burst enable bit */
+#define FSMC_BCR_BURSTEN (1 << 8)
+
+/* Bit 7: Reserved. */
+
+/* FACCEN: Flash access enable */
+#define FSMC_BCR_FACCEN (1 << 6)
+
+/* MWID[5:4]: Memory databus width */
+#define FSMC_BCR_MWID (1 << 4)
+
+/* MTYP[3:2]: Memory type */
+#define FSMC_BCR_MTYP (1 << 2)
+
+/* MUXEN: Address/data multiplexing enable bit */
+#define FSMC_BCR_MUXEN (1 << 1)
+
+/* MBKEN: Memory bank enable bit */
+#define FSMC_BCR_MBKEN (1 << 0)
+
+/* --- FSMC_BTRx values ---------------------------------------------------- */
+
+/* ACCMOD[29:28]: Access mode */
+#define FSMC_BTR_ACCMOD (1 << 28)
+
+/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */
+#define FSMC_BTR_DATLAT (1 << 24)
+
+/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */
+#define FSMC_BTR_CLKDIV (1 << 20)
+
+/* BUSTURN[19:16]: Bus turnaround phase duration */
+#define FSMC_BTR_BUSTURN (1 << 16)
+
+/* DATAST[15:8]: Data-phase duration */
+#define FSMC_BTR_DATAST (1 << 8)
+
+/* ADDHLD[7:4]: Address-hold phase duration */
+#define FSMC_BTR_ADDHLD (1 << 4)
+
+/* ADDSET[3:0]: Address setup phase duration */
+#define FSMC_BTR_ADDSET (1 << 0)
+
+/* --- FSMC_BWTRx values --------------------------------------------------- */
+
+/* ACCMOD[29:28]: Access mode */
+#define FSMC_BWTR_ACCMOD (1 << 28)
+
+/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */
+#define FSMC_BWTR_DATLAT (1 << 24)
+
+/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */
+#define FSMC_BWTR_CLKDIV (1 << 20)
+
+/* Bits 19..16: Reserved. */
+
+/* DATAST[15:8]: Data-phase duration */
+#define FSMC_BWTR_DATAST (1 << 8)
+
+/* ADDHLD[7:4]: Address-hold phase duration */
+#define FSMC_BWTR_ADDHLD (1 << 4)
+
+/* ADDSET[3:0]: Address setup phase duration */
+#define FSMC_BWTR_ADDSET (1 << 0)
+
+/* --- FSMC_PCRx values ---------------------------------------------------- */
+
+/* ECCPS[19:17]: ECC page size */
+#define FSMC_PCR_ECCPS (1 << 17)
+
+/* TAR[16:13]: ALE to RE delay */
+#define FSMC_PCR_TAR (1 << 13)
+
+/* TCLR[12:9]: CLE to RE delay */
+#define FSMC_PCR_TCLR (1 << 9)
+
+/* Bits 8..7: Reserved. */
+
+/* ECCEN: ECC computation logic enable bit */
+#define FSMC_PCR_ECCEN (1 << 6)
+
+/* PWID[5:4]: Databus width */
+#define FSMC_PCR_PWID (1 << 4)
+
+/* PTYP: Memory type */
+#define FSMC_PCR_PTYP (1 << 3)
+
+/* PBKEN: PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR_PBKEN (1 << 2)
+
+/* PWAITEN: Wait feature enable bit */
+#define FSMC_PCR_PWAITEN (1 << 1)
+
+/* Bit 0: Reserved. */
+
+/* --- FSMC_SRx values ----------------------------------------------------- */
+
+/* FEMPT: FIFO empty */
+#define FSMC_SR_FEMPT (1 << 6)
+
+/* IFEN: Interrupt falling edge detection enable bit */
+#define FSMC_SR_IFEN (1 << 5)
+
+/* ILEN: Interrupt high-level detection enable bit */
+#define FSMC_SR_ILEN (1 << 4)
+
+/* IREN: Interrupt rising edge detection enable bit */
+#define FSMC_SR_IREN (1 << 3)
+
+/* IFS: Interrupt falling edge status */
+#define FSMC_SR_IFS (1 << 2)
+
+/* ILS: Interrupt high-level status */
+#define FSMC_SR_ILS (1 << 1)
+
+/* IRS: Interrupt rising edge status */
+#define FSMC_SR_IRS (1 << 0)
+
+/* --- FSMC_PMEMx values --------------------------------------------------- */
+
+/* MEMHIZx[31:24]: Common memory x databus HiZ time */
+#define FSMC_PMEM_MEMHIZX (1 << 24)
+
+/* MEMHOLDx[23:16]: Common memory x hold time */
+#define FSMC_PMEM_MEMHOLDX (1 << 16)
+
+/* MEMWAITx[15:8]: Common memory x wait time */
+#define FSMC_PMEM_MEMHOLDX (1 << 8)
+
+/* MEMSETx[7:0]: Common memory x setup time */
+#define FSMC_PMEM_MEMSETX (1 << 0)
+
+/* --- FSMC_PATTx values --------------------------------------------------- */
+
+/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */
+#define FSMC_PATT_ATTHIZX (1 << 24)
+
+/* ATTHOLDx[23:16]: Attribute memory x hold time */
+#define FSMC_PATT_ATTHOLDX (1 << 16)
+
+/* ATTWAITx[15:8]: Attribute memory x wait time */
+#define FSMC_PATT_ATTWAITX (1 << 8)
+
+/* ATTSETx[7:0]: Attribute memory x setup time */
+#define FSMC_PATT_ATTSETX (1 << 0)
+
+/* --- FSMC_PIO4 values ---------------------------------------------------- */
+
+/* IOHIZx[31:24]: I/O x databus HiZ time */
+#define FSMC_PIO4_IOHIZX (1 << 24)
+
+/* IOHOLDx[23:16]: I/O x hold time */
+#define FSMC_PIO4_IOHOLDX (1 << 16)
+
+/* IOWAITx[15:8]: I/O x wait time */
+#define FSMC_PIO4_IOWAITX (1 << 8)
+
+/* IOSETx[7:0]: I/O x setup time */
+#define FSMC_PIO4_IOSETX (1 << 0)
+
+/* --- FSMC_ECCRx values --------------------------------------------------- */
+
+/* ECCx[31:0]: ECC result */
+#define FSMC_ECCR_ECCX (1 << 0)
+
+#endif
diff --git a/include/libopencm3/stm32/gpio.h b/include/libopencm3/stm32/gpio.h
new file mode 100644
index 0000000..f1463a3
--- /dev/null
+++ b/include/libopencm3/stm32/gpio.h
@@ -0,0 +1,555 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_GPIO_H
+#define LIBOPENCM3_GPIO_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* GPIO port base addresses (for convenience) */
+#define GPIOA GPIO_PORT_A_BASE
+#define GPIOB GPIO_PORT_B_BASE
+#define GPIOC GPIO_PORT_C_BASE
+#define GPIOD GPIO_PORT_D_BASE
+#define GPIOE GPIO_PORT_E_BASE
+#define GPIOF GPIO_PORT_F_BASE
+#define GPIOG GPIO_PORT_G_BASE
+
+/* GPIO number definitions (for convenience) */
+#define GPIO0 (1 << 0)
+#define GPIO1 (1 << 1)
+#define GPIO2 (1 << 2)
+#define GPIO3 (1 << 3)
+#define GPIO4 (1 << 4)
+#define GPIO5 (1 << 5)
+#define GPIO6 (1 << 6)
+#define GPIO7 (1 << 7)
+#define GPIO8 (1 << 8)
+#define GPIO9 (1 << 9)
+#define GPIO10 (1 << 10)
+#define GPIO11 (1 << 11)
+#define GPIO12 (1 << 12)
+#define GPIO13 (1 << 13)
+#define GPIO14 (1 << 14)
+#define GPIO15 (1 << 15)
+#define GPIO_ALL 0xffff
+
+/* --- Alternate function GPIOs -------------------------------------------- */
+
+/* Default alternate functions of some pins (with and without remapping) */
+
+/* CAN1 / CAN */
+#define GPIO_CAN1_RX GPIO11 /* PA11 */
+#define GPIO_CAN1_TX GPIO12 /* PA12 */
+#define GPIO_CAN_RX GPIO_CAN1_RX /* Alias */
+#define GPIO_CAN_TX GPIO_CAN1_TX /* Alias */
+
+#define GPIO_CAN_PB_RX GPIO8 /* PB8 */
+#define GPIO_CAN_PB_TX GPIO9 /* PB9 */
+#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */
+#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */
+
+#define GPIO_CAN_PD_RX GPIO0 /* PD0 */
+#define GPIO_CAN_PD_TX GPIO1 /* PD1 */
+#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */
+#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */
+
+/* CAN2 */
+#define GPIO_CAN2_RX GPIO12 /* PB12 */
+#define GPIO_CAN2_TX GPIO13 /* PB13 */
+
+#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */
+#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */
+
+/* JTAG/SWD */
+#define GPIO_JTMS_SWDIO GPIO13 /* PA13 */
+#define GPIO_JTCK_SWCLK GPIO14 /* PA14 */
+#define GPIO_JTDI GPIO15 /* PA15 */
+#define GPIO_JTDO_TRACESWO GPIO3 /* PB3 */
+#define GPIO_JNTRST GPIO4 /* PB4 */
+#define GPIO_TRACECK GPIO2 /* PE2 */
+#define GPIO_TRACED0 GPIO3 /* PE3 */
+#define GPIO_TRACED1 GPIO4 /* PE4 */
+#define GPIO_TRACED2 GPIO5 /* PE5 */
+#define GPIO_TRACED3 GPIO6 /* PE6 */
+
+/* Timer5 */
+#define GPIO_TIM5_CH4 GPIO3 /* PA3 */
+
+/* Timer4 */
+#define GPIO_TIM4_CH1 GPIO6 /* PB6 */
+#define GPIO_TIM4_CH2 GPIO7 /* PB7 */
+#define GPIO_TIM4_CH3 GPIO8 /* PB8 */
+#define GPIO_TIM4_CH4 GPIO9 /* PB9 */
+
+#define GPIO_TIM4_RE_CH1 GPIO12 /* PD12 */
+#define GPIO_TIM4_RE_CH2 GPIO13 /* PD13 */
+#define GPIO_TIM4_RE_CH3 GPIO14 /* PD14 */
+#define GPIO_TIM4_RE_CH4 GPIO15 /* PD15 */
+
+/* Timer3 */
+#define GPIO_TIM3_CH1 GPIO6 /* PA6 */
+#define GPIO_TIM3_CH2 GPIO7 /* PA7 */
+#define GPIO_TIM3_CH3 GPIO0 /* PB0 */
+#define GPIO_TIM3_CH4 GPIO1 /* PB1 */
+
+#define GPIO_TIM3_PR_CH1 GPIO4 /* PB4 */
+#define GPIO_TIM3_PR_CH2 GPIO5 /* PB5 */
+#define GPIO_TIM3_PR_CH3 GPIO0 /* PB0 */
+#define GPIO_TIM3_PR_CH4 GPIO1 /* PB1 */
+
+#define GPIO_TIM3_FR_CH1 GPIO6 /* PC6 */
+#define GPIO_TIM3_FR_CH2 GPIO7 /* PC7 */
+#define GPIO_TIM3_FR_CH3 GPIO8 /* PC8 */
+#define GPIO_TIM3_FR_CH4 GPIO9 /* PC9 */
+
+/* Timer2 */
+#define GPIO_TIM2_CH1_ETR GPIO0 /* PA0 */
+#define GPIO_TIM2_CH2 GPIO1 /* PA1 */
+#define GPIO_TIM2_CH3 GPIO2 /* PA2 */
+#define GPIO_TIM2_CH4 GPIO3 /* PA3 */
+
+#define GPIO_TIM2_PR1_CH1_ETR GPIO15 /* PA15 */
+#define GPIO_TIM2_PR1_CH2 GPIO3 /* PB3 */
+#define GPIO_TIM2_PR1_CH3 GPIO2 /* PA2 */
+#define GPIO_TIM2_PR1_CH4 GPIO3 /* PA3 */
+
+#define GPIO_TIM2_PR2_CH1_ETR GPIO0 /* PA0 */
+#define GPIO_TIM2_PR2_CH2 GPIO1 /* PA1 */
+#define GPIO_TIM2_PR2_CH3 GPIO10 /* PB10 */
+#define GPIO_TIM2_PR2_CH4 GPIO11 /* PB11 */
+
+#define GPIO_TIM2_FR_CH1_ETR GPIO15 /* PA15 */
+#define GPIO_TIM2_FR_CH2 GPIO3 /* PB3 */
+#define GPIO_TIM2_FR_CH3 GPIO10 /* PB10 */
+#define GPIO_TIM2_FR_CH4 GPIO11 /* PB11 */
+
+/* Timer1 */
+#define GPIO_TIM1_ETR GPIO12 /* PA12 */
+#define GPIO_TIM1_CH1 GPIO8 /* PA8 */
+#define GPIO_TIM1_CH2 GPIO9 /* PA9 */
+#define GPIO_TIM1_CH3 GPIO10 /* PA10 */
+#define GPIO_TIM1_CH4 GPIO11 /* PA11 */
+#define GPIO_TIM1_BKIN GPIO12 /* PB12 */
+#define GPIO_TIM1_CH1N GPIO13 /* PB13 */
+#define GPIO_TIM1_CH2N GPIO14 /* PB14 */
+#define GPIO_TIM1_CH3N GPIO15 /* PB15 */
+
+#define GPIO_TIM1_PR_ETR GPIO12 /* PA12 */
+#define GPIO_TIM1_PR_CH1 GPIO8 /* PA8 */
+#define GPIO_TIM1_PR_CH2 GPIO9 /* PA9 */
+#define GPIO_TIM1_PR_CH3 GPIO10 /* PA10 */
+#define GPIO_TIM1_PR_CH4 GPIO11 /* PA11 */
+#define GPIO_TIM1_PR_BKIN GPIO6 /* PA6 */
+#define GPIO_TIM1_PR_CH1N GPIO7 /* PA7 */
+#define GPIO_TIM1_PR_CH2N GPIO0 /* PB0 */
+#define GPIO_TIM1_PR_CH3N GPIO1 /* PB1 */
+
+#define GPIO_TIM1_FR_ETR GPIO7 /* PE7 */
+#define GPIO_TIM1_FR_CH1 GPIO9 /* PE9 */
+#define GPIO_TIM1_FR_CH2 GPIO11 /* PE11 */
+#define GPIO_TIM1_FR_CH3 GPIO13 /* PE13 */
+#define GPIO_TIM1_FR_CH4 GPIO14 /* PE14 */
+#define GPIO_TIM1_FR_BKIN GPIO15 /* PE15 */
+#define GPIO_TIM1_FR_CH1N GPIO8 /* PE8 */
+#define GPIO_TIM1_FR_CH2N GPIO10 /* PE10 */
+#define GPIO_TIM1_FR_CH3N GPIO12 /* PE12 */
+
+/* USART3 */
+#define GPIO_USART3_TX GPIO10 /* PB10 */
+#define GPIO_USART3_RX GPIO11 /* PB11 */
+#define GPIO_USART3_CK GPIO12 /* PB12 */
+#define GPIO_USART3_CTS GPIO13 /* PB13 */
+#define GPIO_USART3_RTS GPIO14 /* PB14 */
+
+#define GPIO_USART3_PR_TX GPIO10 /* PC10 */
+#define GPIO_USART3_PR_RX GPIO11 /* PC11 */
+#define GPIO_USART3_PR_CK GPIO12 /* PC12 */
+#define GPIO_USART3_PR_CTS GPIO13 /* PB13 */
+#define GPIO_USART3_PR_RTS GPIO14 /* PB14 */
+
+#define GPIO_USART3_FR_TX GPIO8 /* PD8 */
+#define GPIO_USART3_FR_RX GPIO9 /* PD9 */
+#define GPIO_USART3_FR_CK GPIO10 /* PD10 */
+#define GPIO_USART3_FR_CTS GPIO11 /* PD11 */
+#define GPIO_USART3_FR_RTS GPIO12 /* PD12 */
+
+/* USART2 */
+#define GPIO_USART2_CTS GPIO0 /* PA0 */
+#define GPIO_USART2_RTS GPIO1 /* PA1 */
+#define GPIO_USART2_TX GPIO2 /* PA2 */
+#define GPIO_USART2_RX GPIO3 /* PA3 */
+#define GPIO_USART2_CK GPIO4 /* PA4 */
+
+#define GPIO_USART2_RE_CTS GPIO3 /* PD3 */
+#define GPIO_USART2_RE_RTS GPIO4 /* PD4 */
+#define GPIO_USART2_RE_TX GPIO5 /* PD5 */
+#define GPIO_USART2_RE_RX GPIO6 /* PD6 */
+#define GPIO_USART2_RE_CK GPIO7 /* PD7 */
+
+/* USART1 */
+#define GPIO_USART1_TX GPIO9 /* PA9 */
+#define GPIO_USART1_RX GPIO10 /* PA10 */
+
+#define GPIO_USART1_RE_TX GPIO6 /* PB6 */
+#define GPIO_USART1_RE_RX GPIO7 /* PB7 */
+
+/* I2C1 */
+#define GPIO_I2C1_SMBAI GPIO5 /* PB5 */
+#define GPIO_I2C1_SCL GPIO6 /* PB6 */
+#define GPIO_I2C1_SDA GPIO7 /* PB7 */
+
+#define GPIO_I2C1_RE_SMBAI GPIO5 /* PB5 */
+#define GPIO_I2C1_RE_SCL GPIO8 /* PB8 */
+#define GPIO_I2C1_RE_SDA GPIO9 /* PB9 */
+
+/* I2C2 */
+#define GPIO_I2C2_SCL GPIO10 /* PB10 */
+#define GPIO_I2C2_SDA GPIO11 /* PB11 */
+#define GPIO_I2C2_SMBAI GPIO12 /* PB12 */
+
+/* SPI1 */
+#define GPIO_SPI1_NSS GPIO4 /* PA4 */
+#define GPIO_SPI1_SCK GPIO5 /* PA5 */
+#define GPIO_SPI1_MISO GPIO6 /* PA6 */
+#define GPIO_SPI1_MOSI GPIO7 /* PA7 */
+
+#define GPIO_SPI1_RE_NSS GPIO15 /* PA15 */
+#define GPIO_SPI1_RE_SCK GPIO3 /* PB3 */
+#define GPIO_SPI1_RE_MISO GPIO4 /* PB4 */
+#define GPIO_SPI1_RE_MOSI GPIO5 /* PB5 */
+
+/* SPI2 */
+#define GPIO_SPI2_NSS GPIO12 /* PB12 */
+#define GPIO_SPI2_SCK GPIO13 /* PB13 */
+#define GPIO_SPI2_MISO GPIO14 /* PB14 */
+#define GPIO_SPI2_MOSI GPIO15 /* PB15 */
+
+/* SPI3 */
+#define GPIO_SPI3_NSS GPIO15 /* PA15 */
+#define GPIO_SPI3_SCK GPIO3 /* PB3 */
+#define GPIO_SPI3_MISO GPIO4 /* PB4 */
+#define GPIO_SPI3_MOSI GPIO5 /* PB5 */
+
+#define GPIO_SPI3_RE_NSS GPIO4 /* PA4 */
+#define GPIO_SPI3_RE_SCK GPIO10 /* PC10 */
+#define GPIO_SPI3_RE_MISO GPIO11 /* PC11 */
+#define GPIO_SPI3_RE_MOSI GPIO12 /* PC12 */
+
+/* ETH */
+#define GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */
+#define GPIO_ETH_RXD0 GPIO4 /* PC4 */
+#define GPIO_ETH_RXD1 GPIO5 /* PC5 */
+#define GPIO_ETH_RXD2 GPIO0 /* PB0 */
+#define GPIO_ETH_RXD3 GPIO1 /* PB1 */
+
+#define GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */
+#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */
+#define GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */
+#define GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */
+#define GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */
+
+/* --- GPIO registers ------------------------------------------------------ */
+
+/* Port configuration register low (GPIOx_CRL) */
+#define GPIO_CRL(port) MMIO32(port + 0x00)
+#define GPIOA_CRL GPIO_CRL(GPIOA)
+#define GPIOB_CRL GPIO_CRL(GPIOB)
+#define GPIOC_CRL GPIO_CRL(GPIOC)
+#define GPIOD_CRL GPIO_CRL(GPIOD)
+#define GPIOE_CRL GPIO_CRL(GPIOE)
+#define GPIOF_CRL GPIO_CRL(GPIOF)
+#define GPIOG_CRL GPIO_CRL(GPIOG)
+
+/* Port configuration register low (GPIOx_CRH) */
+#define GPIO_CRH(port) MMIO32(port + 0x04)
+#define GPIOA_CRH GPIO_CRH(GPIOA)
+#define GPIOB_CRH GPIO_CRH(GPIOB)
+#define GPIOC_CRH GPIO_CRH(GPIOC)
+#define GPIOD_CRH GPIO_CRH(GPIOD)
+#define GPIOE_CRH GPIO_CRH(GPIOE)
+#define GPIOF_CRH GPIO_CRH(GPIOF)
+#define GPIOG_CRH GPIO_CRH(GPIOG)
+
+/* Port input data register (GPIOx_IDR) */
+#define GPIO_IDR(port) MMIO32(port + 0x08)
+#define GPIOA_IDR GPIO_IDR(GPIOA)
+#define GPIOB_IDR GPIO_IDR(GPIOB)
+#define GPIOC_IDR GPIO_IDR(GPIOC)
+#define GPIOD_IDR GPIO_IDR(GPIOD)
+#define GPIOE_IDR GPIO_IDR(GPIOE)
+#define GPIOF_IDR GPIO_IDR(GPIOF)
+#define GPIOG_IDR GPIO_IDR(GPIOG)
+
+/* Port output data register (GPIOx_ODR) */
+#define GPIO_ODR(port) MMIO32(port + 0x0c)
+#define GPIOA_ODR GPIO_ODR(GPIOA)
+#define GPIOB_ODR GPIO_ODR(GPIOB)
+#define GPIOC_ODR GPIO_ODR(GPIOC)
+#define GPIOD_ODR GPIO_ODR(GPIOD)
+#define GPIOE_ODR GPIO_ODR(GPIOE)
+#define GPIOF_ODR GPIO_ODR(GPIOF)
+#define GPIOG_ODR GPIO_ODR(GPIOG)
+
+/* Port bit set/reset register (GPIOx_BSRR) */
+#define GPIO_BSRR(port) MMIO32(port + 0x10)
+#define GPIOA_BSRR GPIO_BSRR(GPIOA)
+#define GPIOB_BSRR GPIO_BSRR(GPIOB)
+#define GPIOC_BSRR GPIO_BSRR(GPIOC)
+#define GPIOD_BSRR GPIO_BSRR(GPIOD)
+#define GPIOE_BSRR GPIO_BSRR(GPIOE)
+#define GPIOF_BSRR GPIO_BSRR(GPIOF)
+#define GPIOG_BSRR GPIO_BSRR(GPIOG)
+
+/* Port bit reset register (GPIOx_BRR) */
+#define GPIO_BRR(port) MMIO16(port + 0x14)
+#define GPIOA_BRR GPIO_BRR(GPIOA)
+#define GPIOB_BRR GPIO_BRR(GPIOB)
+#define GPIOC_BRR GPIO_BRR(GPIOC)
+#define GPIOD_BRR GPIO_BRR(GPIOD)
+#define GPIOE_BRR GPIO_BRR(GPIOE)
+#define GPIOF_BRR GPIO_BRR(GPIOF)
+#define GPIOG_BRR GPIO_BRR(GPIOG)
+
+/* Port configuration lock register (GPIOx_LCKR) */
+#define GPIO_LCKR(port) MMIO32(port + 0x18)
+#define GPIOA_LCKR GPIO_LCKR(GPIOA)
+#define GPIOB_LCKR GPIO_LCKR(GPIOB)
+#define GPIOC_LCKR GPIO_LCKR(GPIOC)
+#define GPIOD_LCKR GPIO_LCKR(GPIOD)
+#define GPIOE_LCKR GPIO_LCKR(GPIOE)
+#define GPIOF_LCKR GPIO_LCKR(GPIOF)
+#define GPIOG_LCKR GPIO_LCKR(GPIOG)
+
+/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */
+
+/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */
+#define GPIO_CNF_INPUT_ANALOG 0x00
+#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */
+#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02
+
+/* Output mode (MODE[1:0]) values */
+#define GPIO_MODE_INPUT 0x00 /* Default */
+#define GPIO_MODE_OUTPUT_10_MHZ 0x01
+#define GPIO_MODE_OUTPUT_2_MHZ 0x02
+#define GPIO_MODE_OUTPUT_50_MHZ 0x03
+
+/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */
+#define GPIO_CNF_OUTPUT_PUSHPULL 0x00
+#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01
+#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02
+#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03
+
+/* --- GPIO_IDR values ----------------------------------------------------- */
+
+/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
+
+/* --- GPIO_ODR values ----------------------------------------------------- */
+
+/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
+
+/* --- GPIO_BSRR values ---------------------------------------------------- */
+
+/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
+/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
+
+/* --- GPIO_BRR values ----------------------------------------------------- */
+
+/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */
+
+/* --- GPIO_LCKR values ---------------------------------------------------- */
+
+#define GPIO_LCKK (1 << 16)
+/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
+
+/* --- AFIO registers ------------------------------------------------------ */
+
+/* Event control register (AFIO_EVCR) */
+#define AFIO_EVCR MMIO32(AFIO_BASE + 0x00)
+
+/* AF remap and debug I/O configuration register (AFIO_MAPR) */
+#define AFIO_MAPR MMIO32(AFIO_BASE + 0x04)
+
+/* External interrupt configuration register 1 (AFIO_EXTICR1) */
+#define AFIO_EXTICR1 MMIO32(AFIO_BASE + 0x08)
+
+/* External interrupt configuration register 2 (AFIO_EXTICR2) */
+#define AFIO_EXTICR2 MMIO32(AFIO_BASE + 0x0c)
+
+/* External interrupt configuration register 3 (AFIO_EXTICR3) */
+#define AFIO_EXTICR3 MMIO32(AFIO_BASE + 0x10)
+
+/* External interrupt configuration register 4 (AFIO_EXTICR4) */
+#define AFIO_EXTICR4 MMIO32(AFIO_BASE + 0x14)
+
+/* --- AFIO_EVCR values ---------------------------------------------------- */
+
+/* EVOE: Event output enable */
+#define AFIO_EVCR_EVOE (1 << 7)
+
+/* PORT[2:0]: Port selection */
+#define AFIO_EVCR_PORT_PA (0x0 << 4)
+#define AFIO_EVCR_PORT_PB (0x1 << 4)
+#define AFIO_EVCR_PORT_PC (0x2 << 4)
+#define AFIO_EVCR_PORT_PD (0x3 << 4)
+#define AFIO_EVCR_PORT_PE (0x4 << 4)
+
+/* PIN[3:0]: Pin selection */
+#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
+#define AFIO_EVCR_PIN_Px1 (0x1 << 0)
+#define AFIO_EVCR_PIN_Px2 (0x2 << 0)
+#define AFIO_EVCR_PIN_Px3 (0x3 << 0)
+#define AFIO_EVCR_PIN_Px4 (0x4 << 0)
+#define AFIO_EVCR_PIN_Px5 (0x5 << 0)
+#define AFIO_EVCR_PIN_Px6 (0x6 << 0)
+#define AFIO_EVCR_PIN_Px7 (0x7 << 0)
+#define AFIO_EVCR_PIN_Px8 (0x8 << 0)
+#define AFIO_EVCR_PIN_Px9 (0x9 << 0)
+#define AFIO_EVCR_PIN_Px10 (0xA << 0)
+#define AFIO_EVCR_PIN_Px11 (0xB << 0)
+#define AFIO_EVCR_PIN_Px12 (0xC << 0)
+#define AFIO_EVCR_PIN_Px13 (0xD << 0)
+#define AFIO_EVCR_PIN_Px14 (0xE << 0)
+#define AFIO_EVCR_PIN_Px15 (0xF << 0)
+
+/* --- AFIO_MAPR values ---------------------------------------------------- */
+
+/* 31 reserved */
+
+/* PTP_PPS_REMAP: Ethernet PTP PPS remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
+
+/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
+
+/* SPI3_REMAP: SPI3/I2S3 remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_SPI3_REMAP (1 << 28)
+
+/* 27 reserved */
+
+/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
+#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
+#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
+#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
+#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24)
+
+/* MII_REMAP: MII or RMII selection
+ * (only connectivity line devices) */
+#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
+
+/* CAN2_REMAP: CAN2 I/O remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_CAN2_REMAP (1 << 22)
+
+/* ETH_REMAP: Ethernet MAC I/O remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_ETH_REMAP (1 << 21)
+
+/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping
+ * (only low-, medium-, high- and XL-densitiy devices) */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
+
+/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping
+ * (only low-, medium-, high- and XL-densitiy devices) */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
+
+/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping
+ * (only low-, medium-, high- and XL-densitiy devices) */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
+
+/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping
+ * (only low-, medium-, high- and XL-densitiy devices) */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
+
+/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */
+#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
+
+/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_PD01_REMAP (1 << 15)
+
+/* CAN_REMAP[1:0]: CAN1 alternate function remapping */
+#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
+#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */
+#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
+
+/* TIM4_REMAP: TIM4 remapping */
+#define AFIO_MAPR_TIM4_REMAP (1 << 12)
+
+/* TIM3_REMAP[1:0]: TIM3 remapping */
+#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
+#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10)
+#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10)
+
+/* TIM2_REMAP[1:0]: TIM2 remapping */
+#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
+#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8)
+#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8)
+#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8)
+
+/* TIM1_REMAP[1:0]: TIM1 remapping */
+#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
+#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6)
+#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6)
+
+/* USART3_REMAP[1:0]: USART3 remapping */
+#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
+#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4)
+#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4)
+
+/* USART2_REMAP[1:0]: USART2 remapping */
+#define AFIO_MAPR_USART2_REMAP (1 << 3)
+
+/* USART1_REMAP[1:0]: USART1 remapping */
+#define AFIO_MAPR_USART1_REMAP (1 << 2)
+
+/* I2C1_REMAP[1:0]: I2C1 remapping */
+#define AFIO_MAPR_I2C1_REMAP (1 << 1)
+
+/* SPI1_REMAP[1:0]: SPI1 remapping */
+#define AFIO_MAPR_SPI1_REMAP (1 << 0)
+
+/* --- AFIO_EXTICR1 values ------------------------------------------------- */
+/* --- AFIO_EXTICR2 values ------------------------------------------------- */
+/* --- AFIO_EXTICR3 values ------------------------------------------------- */
+/* --- AFIO_EXTICR4 values ------------------------------------------------- */
+
+/* EXTI0 - EXTI15 interrupt source selection registers */
+
+/* Note: For using them we should define a function that calculates the right
+ * registers, using definitions is probably not a good idea.
+ */
+
+/* --- Function prototypes ------------------------------------------------- */
+
+void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios);
+void gpio_set(u32 gpioport, u16 gpios);
+void gpio_clear(u32 gpioport, u16 gpios);
+u16 gpio_get(u32 gpioport, u16 gpios);
+void gpio_toggle(u32 gpioport, u16 gpios);
+u16 gpio_port_read(u32 gpioport);
+void gpio_port_write(u32 gpioport, u16 data);
+void gpio_port_config_lock(u32 gpioport, u16 gpios);
+
+#endif
diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h
new file mode 100644
index 0000000..1b837b8
--- /dev/null
+++ b/include/libopencm3/stm32/i2c.h
@@ -0,0 +1,333 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_I2C_H
+#define LIBOPENCM3_I2C_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* I2C register base adresses (for convenience) */
+#define I2C1 I2C1_BASE
+#define I2C2 I2C2_BASE
+
+/* --- I2C registers ------------------------------------------------------- */
+
+/* Control register 1 (I2Cx_CR1) */
+#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00)
+#define I2C1_CR1 I2C_CR1(I2C1)
+#define I2C2_CR1 I2C_CR1(I2C2)
+
+/* Control register 2 (I2Cx_CR2) */
+#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04)
+#define I2C1_CR2 I2C_CR2(I2C1)
+#define I2C2_CR2 I2C_CR2(I2C2)
+
+/* Own address register 1 (I2Cx_OAR1) */
+#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08)
+#define I2C1_OAR1 I2C_OAR1(I2C1)
+#define I2C2_OAR1 I2C_OAR1(I2C2)
+
+/* Own address register 2 (I2Cx_OAR2) */
+#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c)
+#define I2C1_OAR2 I2C_OAR2(I2C1)
+#define I2C2_OAR2 I2C_OAR2(I2C2)
+
+/* Data register (I2Cx_DR) */
+#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10)
+#define I2C1_DR I2C_DR(I2C1)
+#define I2C2_DR I2C_DR(I2C2)
+
+/* Status register 1 (I2Cx_SR1) */
+#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14)
+#define I2C1_SR1 I2C_SR1(I2C1)
+#define I2C2_SR1 I2C_SR1(I2C2)
+
+/* Status register 2 (I2Cx_SR2) */
+#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18)
+#define I2C1_SR2 I2C_SR2(I2C1)
+#define I2C2_SR2 I2C_SR2(I2C2)
+
+/* Clock control register (I2Cx_CCR) */
+#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c)
+#define I2C1_CCR I2C_CCR(I2C1)
+#define I2C2_CCR I2C_CCR(I2C2)
+
+/* TRISE register (I2Cx_CCR) */
+#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20)
+#define I2C1_TRISE I2C_TRISE(I2C1)
+#define I2C2_TRISE I2C_TRISE(I2C2)
+
+/* --- I2Cx_CR1 values ----------------------------------------------------- */
+
+/* SWRST: Software reset */
+#define I2C_CR1_SWRST (1 << 15)
+
+/* Note: Bit 14 is reserved, and forced to 0 by hardware. */
+
+/* ALERT: SMBus alert */
+#define I2C_CR1_ALERT (1 << 13)
+
+/* PEC: Packet error checking */
+#define I2C_CR1_PEC (1 << 12)
+
+/* POS: Acknowledge / PEC postition */
+#define I2C_CR1_POS (1 << 11)
+
+/* ACK: Acknowledge enable */
+#define I2C_CR1_ACK (1 << 10)
+
+/* STOP: STOP generation */
+#define I2C_CR1_STOP (1 << 9)
+
+/* START: START generation */
+#define I2C_CR1_START (1 << 8)
+
+/* NOSTRETCH: Clock stretching disable (slave mode) */
+#define I2C_CR1_NOSTRETCH (1 << 7)
+
+/* ENGC: General call enable */
+#define I2C_CR1_ENGC (1 << 6)
+
+/* ENPEC: Enable PEC */
+#define I2C_CR1_ENPEC (1 << 5)
+
+/* ENARP: ARP enable */
+#define I2C_CR1_ENARP (1 << 4)
+
+/* SMBTYPE: SMBus type */
+#define I2C_CR1_SMBTYPE (1 << 3)
+
+/* Note: Bit 2 is reserved, and forced to 0 by hardware. */
+
+/* SMBUS: SMBus mode */
+#define I2C_CR1_SMBUS (1 << 1)
+
+/* PE: Peripheral enable */
+#define I2C_CR1_PE (1 << 0)
+
+/* --- I2Cx_CR2 values ----------------------------------------------------- */
+
+/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */
+
+/* LAST: DMA last transfer */
+#define I2C_CR2_LAST (1 << 12)
+
+/* DMAEN: DMA requests enable */
+#define I2C_CR2_DMAEN (1 << 11)
+
+/* ITBUFEN: Buffer interrupt enable */
+#define I2C_CR2_ITBUFEN (1 << 10)
+
+/* ITEVTEN: Event interrupt enable */
+#define I2C_CR2_ITEVTEN (1 << 9)
+
+/* ITERREN: Error interrupt enable */
+#define I2C_CR2_ITERREN (1 << 8)
+
+/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
+
+/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
+#define I2C_CR2_FREQ_2MHZ 0x02
+#define I2C_CR2_FREQ_3MHZ 0x03
+#define I2C_CR2_FREQ_4MHZ 0x04
+#define I2C_CR2_FREQ_5MHZ 0x05
+#define I2C_CR2_FREQ_6MHZ 0x06
+#define I2C_CR2_FREQ_7MHZ 0x07
+#define I2C_CR2_FREQ_8MHZ 0x08
+#define I2C_CR2_FREQ_9MHZ 0x09
+#define I2C_CR2_FREQ_10MHZ 0x0a
+#define I2C_CR2_FREQ_11MHZ 0x0b
+#define I2C_CR2_FREQ_12MHZ 0x0c
+#define I2C_CR2_FREQ_13MHZ 0x0d
+#define I2C_CR2_FREQ_14MHZ 0x0e
+#define I2C_CR2_FREQ_15MHZ 0x0f
+#define I2C_CR2_FREQ_16MHZ 0x10
+#define I2C_CR2_FREQ_17MHZ 0x11
+#define I2C_CR2_FREQ_18MHZ 0x12
+#define I2C_CR2_FREQ_19MHZ 0x13
+#define I2C_CR2_FREQ_20MHZ 0x14
+#define I2C_CR2_FREQ_21MHZ 0x15
+#define I2C_CR2_FREQ_22MHZ 0x16
+#define I2C_CR2_FREQ_23MHZ 0x17
+#define I2C_CR2_FREQ_24MHZ 0x18
+#define I2C_CR2_FREQ_25MHZ 0x19
+#define I2C_CR2_FREQ_26MHZ 0x1a
+#define I2C_CR2_FREQ_27MHZ 0x1b
+#define I2C_CR2_FREQ_28MHZ 0x1c
+#define I2C_CR2_FREQ_29MHZ 0x1d
+#define I2C_CR2_FREQ_30MHZ 0x1e
+#define I2C_CR2_FREQ_31MHZ 0x1f
+#define I2C_CR2_FREQ_32MHZ 0x20
+#define I2C_CR2_FREQ_33MHZ 0x21
+#define I2C_CR2_FREQ_34MHZ 0x22
+#define I2C_CR2_FREQ_35MHZ 0x23
+#define I2C_CR2_FREQ_36MHZ 0x24
+
+/* --- I2Cx_OAR1 values ---------------------------------------------------- */
+
+/* ADDMODE: Addressing mode (slave mode) */
+#define I2C_OAR1_ADDMODE (1 << 15)
+#define I2C_OAR1_ADDMODE_7BIT 0
+#define I2C_OAR1_ADDMODE_10BIT 1
+
+/* Note: Bit 14 should always be kept at 1 by software! */
+
+/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */
+
+/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */
+
+/* --- I2Cx_OAR1 values ---------------------------------------------------- */
+
+/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
+
+/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */
+
+/* ENDUAL: Dual addressing mode enable */
+#define I2C_OAR2_ENDUAL (1 << 0)
+
+/* --- I2Cx_DR values ------------------------------------------------------ */
+
+/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
+
+/* DR[7:0] 8-bit data register */
+
+/* --- I2Cx_SR1 values ----------------------------------------------------- */
+
+/* SMBALERT: SMBus alert */
+#define I2C_SR1_SMBALERT (1 << 15)
+
+/* TIMEOUT: Timeout or Tlow Error */
+#define I2C_SR1_TIMEOUT (1 << 14)
+
+/* Note: Bit 13 is reserved, and forced to 0 by hardware. */
+
+/* PECERR: PEC Error in reception */
+#define I2C_SR1_PECERR (1 << 12)
+
+/* OVR: Overrun/Underrun */
+#define I2C_SR1_OVR (1 << 11)
+
+/* AF: Acknowledge failure */
+#define I2C_SR1_AF (1 << 10)
+
+/* ARLO: Arbitration lost (master mode) */
+#define I2C_SR1_ARLO (1 << 9)
+
+/* BERR: Bus error */
+#define I2C_SR1_BERR (1 << 8)
+
+/* TxE: Data register empty (transmitters) */
+#define I2C_SR1_TxE (1 << 7)
+
+/* RxNE: Data register not empty (receivers) */
+#define I2C_SR1_RxNE (1 << 6)
+
+/* Note: Bit 5 is reserved, and forced to 0 by hardware. */
+
+/* STOPF: STOP detection (slave mode) */
+#define I2C_SR1_STOPF (1 << 4)
+
+/* ADD10: 10-bit header sent (master mode) */
+#define I2C_SR1_ADD10 (1 << 3)
+
+/* BTF: Byte transfer finished */
+#define I2C_SR1_BTF (1 << 2)
+
+/* ADDR: Address sent (master mode) / address matched (slave mode) */
+#define I2C_SR1_ADDR (1 << 1)
+
+/* SB: Start bit (master mode) */
+#define I2C_SR1_SB (1 << 0)
+
+/* --- I2Cx_SR2 values ----------------------------------------------------- */
+
+/* Bits [15:8]: PEC[7:0]: Packet error checking register */
+
+/* DUALF: Dual flag (slave mode) */
+#define I2C_SR2_DUALF (1 << 7)
+
+/* SMBHOST: SMBus host header (slave mode) */
+#define I2C_SR2_SMBHOST (1 << 6)
+
+/* SMBDEFAULT: SMBus device default address (slave mode) */
+#define I2C_SR2_SMBDEFAULT (1 << 5)
+
+/* GENCALL: General call address (slave mode) */
+#define I2C_SR2_GENCALL (1 << 4)
+
+/* Note: Bit 3 is reserved, and forced to 0 by hardware. */
+
+/* TRA: Transmitter / receiver */
+#define I2C_SR2_TRA (1 << 2)
+
+/* BUSY: Bus busy */
+#define I2C_SR2_BUSY (1 << 1)
+
+/* MSL: Master / slave */
+#define I2C_SR2_MSL (1 << 0)
+
+/* --- I2Cx_CCR values ----------------------------------------------------- */
+
+/* F/S: I2C Master mode selection (fast / standard) */
+#define I2C_CCR_FS (1 << 15)
+
+/* DUTY: Fast Mode Duty Cycle */
+#define I2C_CCR_DUTY (1 << 14)
+
+/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
+
+/*
+ * Bits [11:0]:
+ * CCR[11:0]: Clock control register in Fast/Standard mode (master mode)
+ */
+
+/* --- I2Cx_TRISE values --------------------------------------------------- */
+
+/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
+
+/*
+ * Bits [5:0]:
+ * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
+ */
+
+/* --- I2C const definitions ----------------------------------------------- */
+
+#define I2C_WRITE 0
+#define I2C_READ 1
+
+/* --- I2C funtion prototypes----------------------------------------------- */
+
+void i2c_peripheral_enable(u32 i2c);
+void i2c_peripheral_disable(u32 i2c);
+void i2c_send_start(u32 i2c);
+void i2c_send_stop(u32 i2c);
+void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave);
+void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave);
+void i2c_set_fast_mode(u32 i2c);
+void i2c_set_standard_mode(u32 i2c);
+void i2c_set_clock_frequency(u32 i2c, u8 freq);
+void i2c_set_ccr(u32 i2c, u16 freq);
+void i2c_set_trise(u32 i2c, u16 trise);
+void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
+void i2c_send_data(u32 i2c, u8 data);
+
+#endif
diff --git a/include/libopencm3/stm32/iwdg.h b/include/libopencm3/stm32/iwdg.h
new file mode 100644
index 0000000..bf2784a
--- /dev/null
+++ b/include/libopencm3/stm32/iwdg.h
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_IWDG_H
+#define LIBOPENCM3_IWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- IWDG registers ------------------------------------------------------ */
+
+/* Key Register (IWDG_KR) */
+#define IWDG_KR MMIO32(IWDG_BASE + 0x00)
+
+/* Prescaler register (IWDG_PR) */
+#define IWDG_PR MMIO32(IWDG_BASE + 0x04)
+
+/* Reload register (IWDG_RLR) */
+#define IWDG_RLR MMIO32(IWDG_BASE + 0x08)
+
+/* Status register (IWDG_SR) */
+#define IWDG_SR MMIO32(IWDG_BASE + 0x0C)
+
+/* --- IWDG_KR values ------------------------------------------------------ */
+
+/* KEY[15:0]: Key value */
+#define IWDG_KR_RESET 0xAAAA
+#define IWDG_KR_UNLOCK 0x5555
+#define IWDG_KR_START 0xCCCC
+
+/* --- IWDG_PR values ------------------------------------------------------ */
+
+/* PR[2:0]: Prescaler divider */
+#define IWDG_PR_LSB 0
+#define IWDG_PR_DIV4 0x0
+#define IWDG_PR_DIV8 0x1
+#define IWDG_PR_DIV16 0x2
+#define IWDG_PR_DIV32 0x3
+#define IWDG_PR_DIV64 0x4
+#define IWDG_PR_DIV128 0x5
+#define IWDG_PR_DIV256 0x6
+/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */
+/* #define IWDG_PR_DIV256 0x7 */
+
+/* --- IWDG_RLR values ----------------------------------------------------- */
+
+/* RL[11:0]: Watchdog counter reload value */
+
+/* --- IWDG_SR values ------------------------------------------------------ */
+
+/* RVU: Watchdog counter reload value update */
+#define IWDG_SR_RVU (1 << 1)
+
+/* PVU: Watchdog prescaler value update */
+#define IWDG_SR_PVU (1 << 0)
+
+/* --- IWDG funtion prototypes---------------------------------------------- */
+
+#endif
diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h
new file mode 100644
index 0000000..52fe6d4
--- /dev/null
+++ b/include/libopencm3/stm32/memorymap.h
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_MEMORYMAP_H
+#define LIBOPENCM3_MEMORYMAP_H
+
+#include <libopencm3/cm3/memorymap.h>
+
+/* --- STM32 specific peripheral definitions ------------------------------- */
+
+/* Memory map for all busses */
+#define PERIPH_BASE 0x40000000
+#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
+#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
+#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000)
+
+/* Register boundary addresses */
+
+/* APB1 */
+#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
+#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
+#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
+#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
+#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
+#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
+/* PERIPH_BASE_APB1 + 0x1800 (0x4000 1800 - 0x4000 27FF): Reserved */
+#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
+#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
+#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
+/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
+#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800)
+#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00)
+/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
+#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
+#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
+#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
+#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
+#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
+#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
+#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
+#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
+#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
+#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
+/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */
+#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00)
+#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
+#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
+/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */
+
+/* APB2 */
+#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000)
+#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
+#define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800)
+#define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00)
+#define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000)
+#define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400)
+#define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800)
+#define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00)
+#define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000)
+#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)
+#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800)
+#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00)
+#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
+#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)
+#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
+#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00)
+/* PERIPH_BASE_APB2 + 0x4000 (0x4001 4000 - 0x4001 7FFF): Reserved */
+
+/* AHB */
+#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000)
+/* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */
+#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000)
+#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400)
+/* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */
+#define RCC_BASE (PERIPH_BASE_AHB + 0x09000)
+/* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */
+#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000)
+#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000)
+/* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */
+#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)
+/* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */
+#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0x10000000)
+
+#endif
diff --git a/include/libopencm3/stm32/nvic.h b/include/libopencm3/stm32/nvic.h
new file mode 100644
index 0000000..ce8132f
--- /dev/null
+++ b/include/libopencm3/stm32/nvic.h
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_NVIC_H
+#define LIBOPENCM3_NVIC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- NVIC Registers ------------------------------------------------------ */
+
+/* ISER: Interrupt Set Enable Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
+
+/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
+
+/* ICER: Interrupt Clear Enable Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
+
+/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
+
+/* ISPR: Interrupt Set Pending Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
+
+/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
+
+/* ICPR: Interrupt Clear Pending Registers */
+/* Note: 8 32bit Registers */
+#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
+
+/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
+
+/* IABR: Interrupt Active Bit Register */
+/* Note: 8 32bit Registers */
+#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
+
+/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
+
+/* IPR: Interrupt Priority Registers */
+/* Note: 240 8bit Registers */
+#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
+
+/* STIR: Software Trigger Interrupt Register */
+#define NVIC_STIR MMIO32(STIR_BASE)
+
+/* --- IRQ channel numbers-------------------------------------------------- */
+
+/* Cortex M3 System Interrupts */
+#define NVIC_NMI_IRQ -14
+#define NVIC_HARD_FAULT_IRQ -13
+#define NVIC_MEM_MANAGE_IRQ -12
+#define NVIC_BUS_FAULT_IRQ -11
+#define NVIC_USAGE_FAULT_IRQ -10
+/* irq numbers -6 to -9 are reserved */
+#define NVIC_SV_CALL_IRQ -5
+#define DEBUG_MONITOR_IRQ -4
+/* irq number -3 reserved */
+#define NVIC_PENDSV_IRQ -2
+#define NVIC_SYSTICK_IRQ -1
+
+/* User Interrupts */
+#define NVIC_WWDG_IRQ 0
+#define NVIC_PVD_IRQ 1
+#define NVIC_TAMPER_IRQ 2
+#define NVIC_RTC_IRQ 3
+#define NVIC_FLASH_IRQ 4
+#define NVIC_RCC_IRQ 5
+#define NVIC_EXTI0_IRQ 6
+#define NVIC_EXTI1_IRQ 7
+#define NVIC_EXTI2_IRQ 8
+#define NVIC_EXTI3_IRQ 9
+#define NVIC_EXTI4_IRQ 10
+#define NVIC_DMA1_CHANNEL1_IRQ 11
+#define NVIC_DMA1_CHANNEL2_IRQ 12
+#define NVIC_DMA1_CHANNEL3_IRQ 13
+#define NVIC_DMA1_CHANNEL4_IRQ 14
+#define NVIC_DMA1_CHANNEL5_IRQ 15
+#define NVIC_DMA1_CHANNEL6_IRQ 16
+#define NVIC_DMA1_CHANNEL7_IRQ 17
+#define NVIC_ADC1_2_IRQ 18
+#define NVIC_USB_HP_CAN_TX_IRQ 19
+#define NVIC_USB_LP_CAN_RX0_IRQ 20
+#define NVIC_CAN_RX1_IRQ 21
+#define NVIC_CAN_SCE_IRQ 22
+#define NVIC_EXTI9_5_IRQ 23
+#define NVIC_TIM1_BRK_IRQ 24
+#define NVIC_TIM1_UP_IRQ 25
+#define NVIC_TIM1_TRG_COM_IRQ 26
+#define NVIC_TIM1_CC_IRQ 27
+#define NVIC_TIM2_IRQ 28
+#define NVIC_TIM3_IRQ 29
+#define NVIC_TIM4_IRQ 30
+#define NVIC_I2C1_EV_IRQ 31
+#define NVIC_I2C1_ER_IRQ 32
+#define NVIC_I2C2_EV_IRQ 33
+#define NVIC_I2C2_ER_IRQ 34
+#define NVIC_SPI1_IRQ 35
+#define NVIC_SPI2_IRQ 36
+#define NVIC_USART1_IRQ 37
+#define NVIC_USART2_IRQ 38
+#define NVIC_USART3_IRQ 39
+#define NVIC_EXTI15_10_IRQ 40
+#define NVIC_RTC_ALARM_IRQ 41
+#define NVIC_USB_WAKEUP_IRQ 42
+#define NVIC_TIM8_BRK_IRQ 43
+#define NVIC_TIM8_UP_IRQ 44
+#define NVIC_TIM8_TRG_COM_IRQ 45
+#define NVIC_TIM8_CC_IRQ 46
+#define NVIC_ADC3_IRQ 47
+#define NVIC_FSMC_IRQ 48
+#define NVIC_SDIO_IRQ 49
+#define NVIC_TIM5_IRQ 50
+#define NVIC_SPI3_IRQ 51
+#define NVIC_USART4_IRQ 52
+#define NVIC_USART5_IRQ 53
+#define NVIC_TIM6_IRQ 54
+#define NVIC_TIM7_IRQ 55
+#define NVIC_DMA2_CHANNEL1_IRQ 56
+#define NVIC_DMA2_CHANNEL2_IRQ 57
+#define NVIC_DMA2_CHANNEL3_IRQ 58
+#define NVIC_DMA2_CHANNEL4_5_IRQ 59
+
+/* --- NVIC functions ------------------------------------------------------ */
+
+void nvic_enable_irq(u8 irqn);
+void nvic_disable_irq(u8 irqn);
+u8 nvic_get_pending_irq(u8 irqn);
+void nvic_set_pending_irq(u8 irqn);
+void nvic_clear_pending_irq(u8 irqn);
+u8 nvic_get_active_irq(u8 irqn);
+u8 nvic_get_irq_enabled(u8 irqn);
+void nvic_set_priority(u8 irqn, u8 priority);
+void nvic_generate_software_interrupt(u8 irqn);
+
+#endif
diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h
new file mode 100644
index 0000000..e5b9804
--- /dev/null
+++ b/include/libopencm3/stm32/pwr.h
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_PWR_H
+#define LIBOPENCM3_PWR_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- PWR registers ------------------------------------------------------- */
+
+/* Power control register (PWR_CR) */
+#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
+
+/* Power control/status register (PWR_CSR) */
+#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
+
+/* --- PWR_CR values ------------------------------------------------------- */
+
+/* DBP: Disable backup domain write protection */
+#define PWR_CR_DBP (1 << 8)
+
+/* PLS[7:5]: PVD level selection */
+#define PWR_CR_PLS_LSB 5
+#define PWR_CR_PLS_2V2 0x0
+#define PWR_CR_PLS_2V3 0x1
+#define PWR_CR_PLS_2V4 0x2
+#define PWR_CR_PLS_2V5 0x3
+#define PWR_CR_PLS_2V6 0x4
+#define PWR_CR_PLS_2V7 0x5
+#define PWR_CR_PLS_2V8 0x6
+#define PWR_CR_PLS_2V9 0x7
+
+/* PVDE: Power voltage detector enable */
+#define PWR_CR_PVDE (1 << 4)
+
+/* CSBF: Clear standby flag */
+#define PWR_CR_CSBF (1 << 3)
+
+/* CWUF: Clear wakeup flag */
+#define PWR_CR_CWUF (1 << 2)
+
+/* PDDS: Power down deepsleep */
+#define PWR_CR_PDDS (1 << 1)
+
+/* LPDS: Low-power deepsleep */
+#define PWR_CR_LPDS (1 << 0)
+
+/* --- PWR_CSR values ------------------------------------------------------ */
+
+/* EWUP: Enable WKUP pin */
+#define PWR_CSR_EWUP (1 << 8)
+
+/* PVDO: PVD output */
+#define PWR_CSR_PVDO (1 << 2)
+
+/* SBF: Standby flag */
+#define PWR_CSR_SBF (1 << 1)
+
+/* WUF: Wakeup flag */
+#define PWR_CSR_WUF (1 << 0)
+
+/* --- PWR function prototypes ------------------------------------------- */
+
+#endif
diff --git a/include/libopencm3/stm32/rcc.h b/include/libopencm3/stm32/rcc.h
new file mode 100644
index 0000000..7215f2b
--- /dev/null
+++ b/include/libopencm3/stm32/rcc.h
@@ -0,0 +1,407 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RCC_H
+#define LIBOPENCM3_RCC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */
+/* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */
+
+/* --- RCC registers ------------------------------------------------------- */
+
+#define RCC_CR MMIO32(RCC_BASE + 0x00)
+#define RCC_CFGR MMIO32(RCC_BASE + 0x04)
+#define RCC_CIR MMIO32(RCC_BASE + 0x08)
+#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)
+#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)
+#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)
+#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)
+#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
+#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
+#define RCC_CSR MMIO32(RCC_BASE + 0x24)
+#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */
+#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */
+
+/* --- RCC_CR values ------------------------------------------------------- */
+
+#define RCC_CR_PLL3RDY (1 << 29) /* (**) */
+#define RCC_CR_PLL3ON (1 << 28) /* (**) */
+#define RCC_CR_PLL2RDY (1 << 27) /* (**) */
+#define RCC_CR_PLL2ON (1 << 26) /* (**) */
+#define RCC_CR_PLLRDY (1 << 25)
+#define RCC_CR_PLLON (1 << 24)
+#define RCC_CR_CSSON (1 << 19)
+#define RCC_CR_HSEBYP (1 << 18)
+#define RCC_CR_HSERDY (1 << 17)
+#define RCC_CR_HSEON (1 << 16)
+/* HSICAL: [15:8] */
+/* HSITRIM: [7:3] */
+#define RCC_CR_HSIRDY (1 << 1)
+#define RCC_CR_HSION (1 << 0)
+
+/* --- RCC_CFGR values ----------------------------------------------------- */
+
+/* MCO: Microcontroller clock output */
+#define RCC_CFGR_MCO_NOCLK 0x0
+#define RCC_CFGR_MCO_SYSCLK 0x4
+#define RCC_CFGR_MCO_HSICLK 0x5
+#define RCC_CFGR_MCO_HSECLK 0x6
+#define RCC_CFGR_RMCO_PLLCLK_DIV2 0x7
+#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */
+#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */
+#define RCC_CFGR_MCO_XT1 0xa /* (**) */
+#define RCC_CFGR_MCO_PLL3 0xb /* (**) */
+
+/* USBPRE: USB prescaler (RCC_CFGR[22]) */
+#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0
+#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1
+
+/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */
+#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0
+#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1
+
+/* PLLMUL: PLL multiplication factor */
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */
+#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */
+// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */
+
+/* TODO: conn. line differs. */
+/* PLLXTPRE: HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0
+#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1
+
+/* PLLSRC: PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0
+#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
+#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */
+
+/* ADCPRE: ADC prescaler */
+#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0
+#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1
+#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2
+#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3
+
+/* PPRE2: APB high-speed prescaler (APB2) */
+#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
+#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
+#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
+#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
+#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
+
+/* PPRE1: APB low-speed prescaler (APB1) */
+#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
+#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
+#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
+#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
+#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
+
+/* HPRE: AHB prescaler */
+#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
+#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
+#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
+#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
+#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
+#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
+#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
+#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
+#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
+
+/* SWS: System clock switch status */
+#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0
+#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1
+#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2
+
+/* SW: System clock switch */
+#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0
+#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1
+#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2
+
+/* --- RCC_CIR values ------------------------------------------------------ */
+
+/* Clock security system interrupt clear bit */
+#define RCC_CIR_CSSC (1 << 23)
+
+/* OSC ready interrupt clear bits */
+#define RCC_CIR_PLL3RDYC (1 << 22) /* (**) */
+#define RCC_CIR_PLL2RDYC (1 << 21) /* (**) */
+#define RCC_CIR_PLLRDYC (1 << 20)
+#define RCC_CIR_HSERDYC (1 << 19)
+#define RCC_CIR_HSIRDYC (1 << 18)
+#define RCC_CIR_LSERDYC (1 << 17)
+#define RCC_CIR_LSIRDYC (1 << 16)
+
+/* OSC ready interrupt enable bits */
+#define RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */
+#define RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */
+#define RCC_CIR_PLLRDYIE (1 << 12)
+#define RCC_CIR_HSERDYIE (1 << 11)
+#define RCC_CIR_HSIRDYIE (1 << 10)
+#define RCC_CIR_LSERDYIE (1 << 9)
+#define RCC_CIR_LSIRDYIE (1 << 8)
+
+/* Clock security system interrupt flag bit */
+#define RCC_CIR_CSSF (1 << 7)
+
+/* OSC ready interrupt flag bits */
+#define RCC_CIR_PLL3RDYF (1 << 6) /* (**) */
+#define RCC_CIR_PLL2RDYF (1 << 5) /* (**) */
+#define RCC_CIR_PLLRDYF (1 << 4)
+#define RCC_CIR_HSERDYF (1 << 3)
+#define RCC_CIR_HSIRDYF (1 << 2)
+#define RCC_CIR_LSERDYF (1 << 1)
+#define RCC_CIR_LSIRDYF (1 << 0)
+
+/* --- RCC_APB2RSTR values ------------------------------------------------- */
+
+#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */
+#define RCC_APB2RSTR_USART1RST (1 << 14)
+#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */
+#define RCC_APB2RSTR_SPI1RST (1 << 12)
+#define RCC_APB2RSTR_TIM1RST (1 << 11)
+#define RCC_APB2RSTR_ADC2RST (1 << 10)
+#define RCC_APB2RSTR_ADC1RST (1 << 9)
+#define RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */
+#define RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */
+#define RCC_APB2RSTR_IOPERST (1 << 6)
+#define RCC_APB2RSTR_IOPDRST (1 << 5)
+#define RCC_APB2RSTR_IOPCRST (1 << 4)
+#define RCC_APB2RSTR_IOPBRST (1 << 3)
+#define RCC_APB2RSTR_IOPARST (1 << 2)
+#define RCC_APB2RSTR_AFIORST (1 << 0)
+
+/* --- RCC_APB1RSTR values ------------------------------------------------- */
+
+#define RCC_APB1RSTR_DACRST (1 << 29)
+#define RCC_APB1RSTR_PWRRST (1 << 28)
+#define RCC_APB1RSTR_BKPRST (1 << 27)
+#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */
+#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */
+#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */
+#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */
+#define RCC_APB1RSTR_I2C2RST (1 << 22)
+#define RCC_APB1RSTR_I2C1RST (1 << 21)
+#define RCC_APB1RSTR_USART5RST (1 << 20)
+#define RCC_APB1RSTR_USART4RST (1 << 19)
+#define RCC_APB1RSTR_USART3RST (1 << 18)
+#define RCC_APB1RSTR_USART2RST (1 << 17)
+#define RCC_APB1RSTR_SPI3RST (1 << 15)
+#define RCC_APB1RSTR_SPI2RST (1 << 14)
+#define RCC_APB1RSTR_WWDGRST (1 << 11)
+#define RCC_APB1RSTR_TIM7RST (1 << 5)
+#define RCC_APB1RSTR_TIM6RST (1 << 4)
+#define RCC_APB1RSTR_TIM5RST (1 << 3)
+#define RCC_APB1RSTR_TIM4RST (1 << 2)
+#define RCC_APB1RSTR_TIM3RST (1 << 1)
+#define RCC_APB1RSTR_TIM2RST (1 << 0)
+
+/* --- RCC_AHBENR values --------------------------------------------------- */
+
+#define RCC_AHBENR_SDIOEN (1 << 10)
+#define RCC_AHBENR_FSMCEN (1 << 8)
+#define RCC_AHBENR_CRCEN (1 << 6)
+#define RCC_AHBENR_FLITFEN (1 << 4)
+#define RCC_AHBENR_SRAMEN (1 << 2)
+#define RCC_AHBENR_DMA2EN (1 << 1)
+#define RCC_AHBENR_DMA1EN (1 << 0)
+
+/* --- RCC_APB2ENR values -------------------------------------------------- */
+
+#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */
+#define RCC_APB2ENR_USART1EN (1 << 14)
+#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */
+#define RCC_APB2ENR_SPI1EN (1 << 12)
+#define RCC_APB2ENR_TIM1EN (1 << 11)
+#define RCC_APB2ENR_ADC2EN (1 << 10)
+#define RCC_APB2ENR_ADC1EN (1 << 9)
+#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */
+#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */
+#define RCC_APB2ENR_IOPEEN (1 << 6)
+#define RCC_APB2ENR_IOPDEN (1 << 5)
+#define RCC_APB2ENR_IOPCEN (1 << 4)
+#define RCC_APB2ENR_IOPBEN (1 << 3)
+#define RCC_APB2ENR_IOPAEN (1 << 2)
+#define RCC_APB2ENR_AFIOEN (1 << 0)
+
+/* --- RCC_APB1ENR values -------------------------------------------------- */
+
+#define RCC_APB1ENR_DACEN (1 << 29)
+#define RCC_APB1ENR_PWREN (1 << 28)
+#define RCC_APB1ENR_BKPEN (1 << 27)
+#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */
+#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */
+#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */
+#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */
+#define RCC_APB1ENR_I2C2EN (1 << 22)
+#define RCC_APB1ENR_I2C1EN (1 << 21)
+#define RCC_APB1ENR_USART5EN (1 << 20)
+#define RCC_APB1ENR_USART4EN (1 << 19)
+#define RCC_APB1ENR_USART3EN (1 << 18)
+#define RCC_APB1ENR_USART2EN (1 << 17)
+#define RCC_APB1ENR_SPI3EN (1 << 15)
+#define RCC_APB1ENR_SPI2EN (1 << 14)
+#define RCC_APB1ENR_WWDGEN (1 << 11)
+#define RCC_APB1ENR_TIM7EN (1 << 5)
+#define RCC_APB1ENR_TIM6EN (1 << 4)
+#define RCC_APB1ENR_TIM5EN (1 << 3)
+#define RCC_APB1ENR_TIM4EN (1 << 2)
+#define RCC_APB1ENR_TIM3EN (1 << 1)
+#define RCC_APB1ENR_TIM2EN (1 << 0)
+
+/* --- RCC_BDCR values ----------------------------------------------------- */
+
+#define RCC_BDCR_BDRST (1 << 16)
+#define RCC_BDCR_RTCEN (1 << 15)
+/* RCC_BDCR[9:8]: RTCSEL */
+#define RCC_BDCR_LSEBYP (1 << 2)
+#define RCC_BDCR_LSERDY (1 << 1)
+#define RCC_BDCR_LSEON (1 << 0)
+
+/* --- RCC_CSR values ------------------------------------------------------ */
+
+#define RCC_CSR_LPWRRSTF (1 << 31)
+#define RCC_CSR_WWDGRSTF (1 << 30)
+#define RCC_CSR_IWDGRSTF (1 << 29)
+#define RCC_CSR_SFTRSTF (1 << 28)
+#define RCC_CSR_PORRSTF (1 << 27)
+#define RCC_CSR_PINRSTF (1 << 26)
+#define RCC_CSR_RMVF (1 << 24)
+#define RCC_CSR_LSIRDY (1 << 1)
+#define RCC_CSR_LSION (1 << 0)
+
+/* --- RCC_AHBRSTR values -------------------------------------------------- */
+
+#define RCC_AHBRSTR_ETHMACRST (1 << 14)
+#define RCC_AHBRSTR_OTGFSRST (1 << 12)
+
+/* --- RCC_CFGR2 values ---------------------------------------------------- */
+
+/* I2S3SRC: I2S3 clock source */
+#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0
+#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1
+
+/* I2S2SRC: I2S2 clock source */
+#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0
+#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1
+
+/* PREDIV1SRC: PREDIV1 entry clock source */
+#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0
+#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1
+
+#define RCC_CFGR2_PLL2MUL (1 << 0)
+#define RCC_CFGR2_PREDIV2 (1 << 0)
+#define RCC_CFGR2_PREDIV1 (1 << 0)
+
+/* PLL3MUL: PLL3 multiplication factor */
+#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6
+#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7
+#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8
+#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9
+#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa
+#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb
+#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc
+#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe
+#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf
+
+/* PLL2MUL: PLL2 multiplication factor */
+#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6
+#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7
+#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8
+#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9
+#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa
+#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb
+#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc
+#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe
+#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf
+
+/* PREDIV2: PREDIV2 division factor */
+#define RCC_CFGR2_PREDIV2_NODIV 0x0
+#define RCC_CFGR2_PREDIV2_DIV2 0x1
+#define RCC_CFGR2_PREDIV2_DIV3 0x2
+#define RCC_CFGR2_PREDIV2_DIV4 0x3
+#define RCC_CFGR2_PREDIV2_DIV5 0x4
+#define RCC_CFGR2_PREDIV2_DIV6 0x5
+#define RCC_CFGR2_PREDIV2_DIV7 0x6
+#define RCC_CFGR2_PREDIV2_DIV8 0x7
+#define RCC_CFGR2_PREDIV2_DIV9 0x8
+#define RCC_CFGR2_PREDIV2_DIV10 0x9
+#define RCC_CFGR2_PREDIV2_DIV11 0xa
+#define RCC_CFGR2_PREDIV2_DIV12 0xb
+#define RCC_CFGR2_PREDIV2_DIV13 0xc
+#define RCC_CFGR2_PREDIV2_DIV14 0xd
+#define RCC_CFGR2_PREDIV2_DIV15 0xe
+#define RCC_CFGR2_PREDIV2_DIV16 0xf
+
+/* --- Function prototypes ------------------------------------------------- */
+
+typedef enum {
+ PLL, HSE, HSI, LSE, LSI
+} osc_t;
+
+void rcc_osc_ready_int_clear(osc_t osc);
+void rcc_osc_ready_int_enable(osc_t osc);
+void rcc_osc_ready_int_disable(osc_t osc);
+int rcc_osc_ready_int_flag(osc_t osc);
+void rcc_css_int_clear(void);
+int rcc_css_int_flag(void);
+void rcc_wait_for_osc_ready(osc_t osc);
+void rcc_osc_on(osc_t osc);
+void rcc_osc_off(osc_t osc);
+void rcc_css_enable(void);
+void rcc_css_disable(void);
+void rcc_osc_bypass_enable(osc_t osc);
+void rcc_osc_bypass_disable(osc_t osc);
+void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
+void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
+void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
+void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
+void rcc_set_sysclk_source(u32 clk);
+void rcc_set_pll_multiplication_factor(u32 mul);
+void rcc_set_pll_source(u32 pllsrc);
+void rcc_set_pllxtpre(u32 pllxtpre);
+void rcc_set_adcpre(u32 adcpre);
+void rcc_set_ppre2(u32 ppre2);
+void rcc_set_ppre1(u32 ppre1);
+void rcc_set_hpre(u32 hpre);
+void rcc_set_usbpre(u32 usbpre);
+u32 rcc_get_system_clock_source(int i);
+void rcc_clock_setup_in_hsi_out_64mhz(void);
+void rcc_clock_setup_in_hsi_out_48mhz(void);
+void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
+void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
+void rcc_backupdomain_reset(void);
+
+#endif
diff --git a/include/libopencm3/stm32/rtc.h b/include/libopencm3/stm32/rtc.h
new file mode 100644
index 0000000..b71525e
--- /dev/null
+++ b/include/libopencm3/stm32/rtc.h
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_RTC_H
+#define LIBOPENCM3_RTC_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/pwr.h>
+
+/* --- RTC registers ------------------------------------------------------- */
+
+/* RTC control register high (RTC_CRH) */
+#define RTC_CRH MMIO32(RTC_BASE + 0x00)
+
+/* RTC control register low (RTC_CRL) */
+#define RTC_CRL MMIO32(RTC_BASE + 0x04)
+
+/* RTC prescaler load register (RTC_PRLH / RTC_PRLL) */
+#define RTC_PRLH MMIO32(RTC_BASE + 0x08)
+#define RTC_PRLL MMIO32(RTC_BASE + 0x0c)
+
+/* RTC prescaler divider register (RTC_DIVH / RTC_DIVL) */
+#define RTC_DIVH MMIO32(RTC_BASE + 0x10)
+#define RTC_DIVL MMIO32(RTC_BASE + 0x14)
+
+/* RTC counter register (RTC_CNTH / RTC_CNTL) */
+#define RTC_CNTH MMIO32(RTC_BASE + 0x18)
+#define RTC_CNTL MMIO32(RTC_BASE + 0x1c)
+
+/* RTC alarm register high (RTC_ALRH / RTC_ALRL) */
+#define RTC_ALRH MMIO32(RTC_BASE + 0x20)
+#define RTC_ALRL MMIO32(RTC_BASE + 0x24)
+
+/* --- RTC_CRH values -------------------------------------------------------*/
+
+/* Note: Bits [15:3] are reserved, and forced to 0 by hardware. */
+
+/* OWIE: Overflow interrupt enable */
+#define RTC_CRH_OWIE (1 << 2)
+
+/* ALRIE: Alarm interrupt enable */
+#define RTC_CRH_ALRIE (1 << 1)
+
+/* SECIE: Second interrupt enable */
+#define RTC_CRH_SECIE (1 << 0)
+
+/* --- RTC_CRL values -------------------------------------------------------*/
+
+/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
+
+/* RTOFF: RTC operation OFF */
+#define RTC_CRL_RTOFF (1 << 5)
+
+/* CNF: Configuration flag */
+#define RTC_CRL_CNF (1 << 4)
+
+/* RSF: Registers synchronized flag */
+#define RTC_CRL_RSF (1 << 3)
+
+/* OWF: Overflow flag */
+#define RTC_CRL_OWF (1 << 2)
+
+/* ALRF: Alarm flag */
+#define RTC_CRL_ALRF (1 << 1)
+
+/* SECF: Second flag */
+#define RTC_CRL_SECF (1 << 0)
+
+/* --- RTC_PRLH values ------------------------------------------------------*/
+
+/* Note: Bits [15:4] are reserved, and forced to 0 by hardware. */
+
+/* TODO */
+
+/* --- RTC_PRLL values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- RTC_DIVH values ------------------------------------------------------*/
+
+/* Bits [15:4] are reserved. */
+
+/* TODO */
+
+/* --- RTC_DIVL values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- RTC_CNTH values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- RTC_CNTL values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- RTC_ALRH values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- RTC_ALRL values ------------------------------------------------------*/
+
+/* TODO */
+
+/* --- Function prototypes --------------------------------------------------*/
+
+typedef enum {
+ RTC_SEC, RTC_ALR, RTC_OW,
+} rtcflag_t;
+
+void rtc_awake_from_off(osc_t clock_source);
+void rtc_enter_config_mode(void);
+void rtc_exit_config_mode(void);
+void rtc_set_alarm_time(u32 alarm_time);
+void rtc_enable_alarm(void);
+void rtc_disable_alarm(void);
+void rtc_set_prescale_val(u32 prescale_val);
+u32 rtc_get_counter_val(void);
+u32 rtc_get_prescale_div_val(void);
+u32 rtc_get_alarm_val(void);
+void rtc_set_counter_val(u32 counter_val);
+void rtc_interrupt_enable(rtcflag_t flag_val);
+void rtc_interrupt_disable(rtcflag_t flag_val);
+void rtc_clear_flag(rtcflag_t flag_val);
+u32 rtc_check_flag(rtcflag_t flag_val);
+void rtc_awake_from_standby(void);
+void rtc_auto_awake(osc_t clock_source, u32 prescale_val);
+
+#endif
diff --git a/include/libopencm3/stm32/scb.h b/include/libopencm3/stm32/scb.h
new file mode 100644
index 0000000..9594cf1
--- /dev/null
+++ b/include/libopencm3/stm32/scb.h
@@ -0,0 +1,300 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SCB_H
+#define LIBOPENCM3_SCB_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- SCB: Registers ------------------------------------------------------ */
+
+/* CPUID: CPUID base register */
+#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
+
+/* ICSR: Interrupt Control State Register */
+#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
+
+/* VTOR: Vector Table Offset Register */
+#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
+
+/* AIRCR: Application Interrupt and Reset Control Register */
+#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
+
+/* SCR: System Control Register */
+#define SCB_SCR MMIO32(SCB_BASE + 0x10)
+
+/* CCR: Configuration Control Register */
+#define SCB_CCR MMIO32(SCB_BASE + 0x14)
+
+/* SHP: System Handler Priority Registers */
+/* Note: 12 8bit registers */
+#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
+#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
+#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
+#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
+
+/* SHCSR: System Handler Control and State Register */
+#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
+
+/* CFSR: Configurable Fault Status Registers */
+#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
+
+/* HFSR: Hard Fault Status Register */
+#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
+
+/* DFSR: Debug Fault Status Register */
+#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
+
+/* MMFAR: Memory Manage Fault Address Register */
+#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
+
+/* BFAR: Bus Fault Address Register */
+#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
+
+/* AFSR: Auxiliary Fault Status Register */
+#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
+
+/* --- SCB values ---------------------------------------------------------- */
+
+/* --- SCB_CPUID values ---------------------------------------------------- */
+
+/* Implementer[31:24]: Implementer code */
+#define SCP_CPUID_IMPLEMENTER_LSB 24
+/* Variant[23:20]: Variant number */
+#define SCP_CPUID_VARIANT_LSB 20
+/* Constant[19:16]: Reads as 0xF */
+#define SCP_CPUID_CONSTANT_LSB 16
+/* PartNo[15:4]: Part number of the processor */
+#define SCP_CPUID_PARTNO_LSB 4
+/* Revision[3:0]: Revision number */
+#define SCP_CPUID_REVISION_LSB 0
+
+/* --- SCB_ICSR values ----------------------------------------------------- */
+
+/* NMIPENDSET: NMI set-pending bit */
+#define SCB_ICSR_NMIPENDSET (1 << 31)
+/* Bits [30:29]: reserved - must be kept cleared */
+/* PENDSVSET: PendSV set-pending bit */
+#define SCB_ICSR_PENDSVSET (1 << 28)
+/* PENDSVCLR: PendSV clear-pending bit */
+#define SCB_ICSR_PENDSVCLR (1 << 27)
+/* PENDSTSET: SysTick exception set-pending bit */
+#define SCB_ICSR_PENDSTSET (1 << 26)
+/* PENDSTCLR: SysTick exception clear-pending bit */
+#define SCB_ICSR_PENDSTCLR (1 << 25)
+/* Bit 24: reserved - must be kept cleared */
+/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
+/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
+#define SCB_ICSR_ISRPENDING (1 << 22)
+/* VECTPENDING[21:12] Pending vector */
+#define SCB_ICSR_VECTPENDING_LSB 12
+/* RETOBASE: Return to base level */
+#define SCB_ICSR_RETOBASE (1 << 11)
+/* Bits [10:9]: reserved - must be kept cleared */
+/* VECTACTIVE[8:0] Active vector */
+#define SCB_ICSR_VECTACTIVE_LSB 0
+
+/* --- SCB_VTOR values ----------------------------------------------------- */
+
+/* Bits [31:30]: reserved - must be kept cleared */
+/* TBLOFF[29:9]: Vector table base offset field */
+#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
+
+/* --- SCB_AIRCR values ---------------------------------------------------- */
+
+/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
+#define SCB_AIRCR_VECTKEYSTAT_LSB 16
+#define SCB_AIRCR_VECTKEY 0x05FA0000
+/* ENDIANESS Data endianness bit */
+#define SCB_AIRCR_ENDIANESS (1 << 15)
+/* Bits [14:11]: reserved - must be kept cleared */
+/* PRIGROUP[10:8]: Interrupt priority grouping field */
+#define SCB_AIRCR_PRIGROUP_LSB 8
+#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB 0x3
+#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 0x4
+#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 0x5
+#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 0x6
+#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 0x7
+/* Bits [7:3]: reserved - must be kept cleared */
+/* SYSRESETREQ System reset request */
+#define SCB_AIRCR_SYSRESETREQ (1 << 2)
+/* VECTCLRACTIVE */
+#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
+/* VECTRESET */
+#define SCB_AIRCR_VECTRESET (1 << 0)
+
+/* --- SCB_SCR values ------------------------------------------------------ */
+
+/* Bits [31:5]: reserved - must be kept cleared */
+/* SEVEONPEND Send Event on Pending bit */
+#define SCB_SCR_SEVEONPEND (1 << 4)
+/* Bit 3: reserved - must be kept cleared */
+/* SLEEPDEEP */
+#define SCB_SCR_SLEEPDEEP (1 << 2)
+/* SLEEPONEXIT */
+#define SCB_SCR_SLEEPONEXIT (1 << 1)
+/* Bit 0: reserved - must be kept cleared */
+
+/* --- SCB_CCR values ------------------------------------------------------ */
+
+/* Bits [31:10]: reserved - must be kept cleared */
+/* STKALIGN */
+#define SCB_CCR_STKALIGN (1 << 9)
+/* BFHFNMIGN */
+#define SCB_CCR_BFHFNMIGN (1 << 8)
+/* Bits [7:5]: reserved - must be kept cleared */
+/* DIV_0_TRP */
+#define SCB_CCR_DIV_0_TRP (1 << 4)
+/* UNALIGN_TRP */
+#define SCB_CCR_UNALIGN_TRP (1 << 3)
+/* Bit 2: reserved - must be kept cleared */
+/* USERSETMPEND */
+#define SCB_CCR_USERSETMPEND (1 << 1)
+/* NONBASETHRDENA */
+#define SCB_CCR_NONBASETHRDENA (1 << 0)
+
+/* --- SCB_SHPR1 values ---------------------------------------------------- */
+
+/* Bits [31:24]: reserved - must be kept cleared */
+/* PRI_6[23:16]: Priority of system handler 6, usage fault */
+#define SCB_SHPR1_PRI_6_LSB 16
+/* PRI_5[15:8]: Priority of system handler 5, bus fault */
+#define SCB_SHPR1_PRI_5_LSB 8
+/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
+#define SCB_SHPR1_PRI_4_LSB 0
+
+/* --- SCB_SHPR2 values ---------------------------------------------------- */
+
+/* PRI_11[31:24]: Priority of system handler 11, SVCall */
+#define SCB_SHPR2_PRI_11_LSB 24
+/* Bits [23:0]: reserved - must be kept cleared */
+
+/* --- SCB_SHPR3 values ---------------------------------------------------- */
+
+/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
+#define SCB_SHPR3_PRI_15_LSB 24
+/* PRI_14[23:16]: Priority of system handler 14, PendSV */
+#define SCB_SHPR3_PRI_14_LSB 16
+/* Bits [15:0]: reserved - must be kept cleared */
+
+/* --- SCB_SHCSR values ---------------------------------------------------- */
+
+/* Bits [31:19]: reserved - must be kept cleared */
+/* USGFAULTENA: Usage fault enable */
+#define SCB_SHCSR_USGFAULTENA (1 << 18)
+/* BUSFAULTENA: Bus fault enable */
+#define SCB_SHCSR_BUSFAULTENA (1 << 17)
+/* MEMFAULTENA: Memory management fault enable */
+#define SCB_SHCSR_MEMFAULTENA (1 << 16)
+/* SVCALLPENDED: SVC call pending */
+#define SCB_SHCSR_SVCALLPENDED (1 << 15)
+/* BUSFAULTPENDED: Bus fault exception pending */
+#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
+/* MEMFAULTPENDED: Memory management fault exception pending */
+#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
+/* USGFAULTPENDED: Usage fault exception pending */
+#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
+/* SYSTICKACT: SysTick exception active */
+#define SCB_SHCSR_SYSTICKACT (1 << 11)
+/* PENDSVACT: PendSV exception active */
+#define SCB_SHCSR_PENDSVACT (1 << 10)
+/* Bit 9: reserved - must be kept cleared */
+/* MONITORACT: Debug monitor active */
+#define SCB_SHCSR_MONITORACT (1 << 8)
+/* SVCALLACT: SVC call active */
+#define SCB_SHCSR_SVCALLACT (1 << 7)
+/* Bits [6:4]: reserved - must be kept cleared */
+/* USGFAULTACT: Usage fault exception active */
+#define SCB_SHCSR_USGFAULTACT (1 << 3)
+/* Bit 2: reserved - must be kept cleared */
+/* BUSFAULTACT: Bus fault exception active */
+#define SCB_SHCSR_BUSFAULTACT (1 << 1)
+/* MEMFAULTACT: Memory management fault exception active */
+#define SCB_SHCSR_MEMFAULTACT (1 << 0)
+
+/* --- SCB_CFSR values ----------------------------------------------------- */
+
+/* Bits [31:26]: reserved - must be kept cleared */
+/* DIVBYZERO: Divide by zero usage fault */
+#define SCB_CFSR_DIVBYZERO (1 << 25)
+/* UNALIGNED: Unaligned access usage fault */
+#define SCB_CFSR_UNALIGNED (1 << 24)
+/* Bits [23:20]: reserved - must be kept cleared */
+/* NOCP: No coprocessor usage fault */
+#define SCB_CFSR_NOCP (1 << 19)
+/* INVPC: Invalid PC load usage fault */
+#define SCB_CFSR_INVPC (1 << 18)
+/* INVSTATE: Invalid state usage fault */
+#define SCB_CFSR_INVSTATE (1 << 17)
+/* UNDEFINSTR: Undefined instruction usage fault */
+#define SCB_CFSR_UNDEFINSTR (1 << 16)
+/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
+#define SCB_CFSR_BFARVALID (1 << 15)
+/* Bits [14:13]: reserved - must be kept cleared */
+/* STKERR: Bus fault on stacking for exception entry */
+#define SCB_CFSR_STKERR (1 << 12)
+/* UNSTKERR: Bus fault on unstacking for a return from exception */
+#define SCB_CFSR_UNSTKERR (1 << 11)
+/* IMPRECISERR: Imprecise data bus error */
+#define SCB_CFSR_IMPRECISERR (1 << 10)
+/* PRECISERR: Precise data bus error */
+#define SCB_CFSR_PRECISERR (1 << 9)
+/* IBUSERR: Instruction bus error */
+#define SCB_CFSR_IBUSERR (1 << 8)
+/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
+#define SCB_CFSR_MMARVALID (1 << 7)
+/* Bits [6:5]: reserved - must be kept cleared */
+/* MSTKERR: Memory manager fault on stacking for exception entry */
+#define SCB_CFSR_MSTKERR (1 << 4)
+/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
+#define SCB_CFSR_MUNSTKERR (1 << 3)
+/* Bit 2: reserved - must be kept cleared */
+/* DACCVIOL: Data access violation flag */
+#define SCB_CFSR_DACCVIOL (1 << 1)
+/* IACCVIOL: Instruction access violation flag */
+#define SCB_CFSR_IACCVIOL (1 << 0)
+
+/* --- SCB_HFSR values ----------------------------------------------------- */
+
+/* DEBUG_VT: reserved for debug use */
+#define SCB_HFSR_DEBUG_VT (1 << 31)
+/* FORCED: Forced hard fault */
+#define SCB_HFSR_FORCED (1 << 30)
+/* Bits [29:2]: reserved - must be kept cleared */
+/* VECTTBL: Vector table hard fault */
+#define SCB_HFSR_VECTTBL (1 << 1)
+/* Bit 0: reserved - must be kept cleared */
+
+/* --- SCB_MMFAR values ---------------------------------------------------- */
+
+/* MMFAR [31:0]: Memory management fault address */
+
+/* --- SCB_BFAR values ----------------------------------------------------- */
+
+/* BFAR [31:0]: Bus fault address */
+
+/* --- SCB functions ------------------------------------------------------- */
+void scb_reset_core(void);
+void scb_reset_system(void);
+
+/* TODO: */
+
+#endif
diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h
new file mode 100644
index 0000000..726310a
--- /dev/null
+++ b/include/libopencm3/stm32/spi.h
@@ -0,0 +1,331 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* Registers can be accessed as 16bit or 32bit values. */
+
+/* --- Convenience macros -------------------------------------------------- */
+
+#define SPI1 SPI1_BASE
+#define SPI2 SPI2_I2S_BASE
+#define SPI3 SPI3_I2S_BASE
+
+/* --- SPI registers ------------------------------------------------------- */
+
+/* Control register 1 (SPIx_CR1) */
+#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00)
+#define SPI1_CR1 SPI_CR1(SPI1_BASE)
+#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE)
+#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE)
+
+/* Control register 2 (SPIx_CR2) */
+#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04)
+#define SPI1_CR2 SPI_CR2(SPI1_BASE)
+#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE)
+#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE)
+
+/* Status register (SPIx_SR) */
+#define SPI_SR(spi_base) MMIO32(spi_base + 0x08)
+#define SPI1_SR SPI_SR(SPI1_BASE)
+#define SPI2_SR SPI_SR(SPI2_I2S_BASE)
+#define SPI3_SR SPI_SR(SPI3_I2S_BASE)
+
+/* Data register (SPIx_DR) */
+#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c)
+#define SPI1_DR SPI_DR(SPI1_BASE)
+#define SPI2_DR SPI_DR(SPI2_I2S_BASE)
+#define SPI3_DR SPI_DR(SPI3_I2S_BASE)
+
+/* CRC polynomial register (SPIx_CRCPR) */
+/* Note: Not used in I2S mode. */
+#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10)
+#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE)
+#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE)
+#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE)
+
+/* RX CRC register (SPIx_RXCRCR) */
+/* Note: Not used in I2S mode. */
+#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14)
+#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)
+#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE)
+#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE)
+
+/* TX CRC register (SPIx_RXCRCR) */
+/* Note: Not used in I2S mode. */
+#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18)
+#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)
+#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE)
+#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE)
+
+/* I2S configuration register (SPIx_I2SCFGR) */
+#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c)
+#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)
+#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE)
+#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE)
+
+/* I2S prescaler register (SPIx_I2SPR) */
+#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20)
+#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE)
+#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE)
+#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE)
+
+/* --- SPI_CR1 values ------------------------------------------------------ */
+
+/* Note: None of the CR1 bits are used in I2S mode. */
+
+/* BIDIMODE: Bidirectional data mode enable */
+#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)
+#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)
+#define SPI_CR1_BIDIMODE (1 << 15)
+
+/* BIDIOE: Output enable in bidirectional mode */
+#define SPI_CR1_BIDIOE (1 << 14)
+
+/* CRCEN: Hardware CRC calculation enable */
+#define SPI_CR1_CRCEN (1 << 13)
+
+/* CRCNEXT: Transmit CRC next */
+#define SPI_CR1_CRCNEXT (1 << 12)
+
+/* DFF: Data frame format */
+#define SPI_CR1_DFF_8BIT (0 << 11)
+#define SPI_CR1_DFF_16BIT (1 << 11)
+#define SPI_CR1_DFF (1 << 11)
+
+/* RXONLY: Receive only */
+#define SPI_CR1_RXONLY (1 << 10)
+
+/* SSM: Software slave management */
+#define SPI_CR1_SSM (1 << 9)
+
+/* SSI: Internal slave select */
+#define SPI_CR1_SSI (1 << 8)
+
+/* LSBFIRST: Frame format */
+#define SPI_CR1_MSBFIRST (0 << 7)
+#define SPI_CR1_LSBFIRST (1 << 7)
+
+/* SPE: SPI enable */
+#define SPI_CR1_SPE (1 << 6)
+
+/* BR[2:0]: Baud rate control */
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
+#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
+#define SPI_CR1_BR_FPCLK_DIV_2 0x0
+#define SPI_CR1_BR_FPCLK_DIV_4 0x1
+#define SPI_CR1_BR_FPCLK_DIV_8 0x2
+#define SPI_CR1_BR_FPCLK_DIV_16 0x3
+#define SPI_CR1_BR_FPCLK_DIV_32 0x4
+#define SPI_CR1_BR_FPCLK_DIV_64 0x5
+#define SPI_CR1_BR_FPCLK_DIV_128 0x6
+#define SPI_CR1_BR_FPCLK_DIV_256 0x7
+
+/* MSTR: Master selection */
+#define SPI_CR1_MSTR (1 << 2)
+
+/* CPOL: Clock polarity */
+#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
+#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
+#define SPI_CR1_CPOL (1 << 1)
+
+/* CPHA: Clock phase */
+#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
+#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
+#define SPI_CR1_CPHA (1 << 0)
+
+/* --- SPI_CR1 values ------------------------------------------------------ */
+
+/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
+
+/* TXEIE: Tx buffer empty interrupt enable */
+#define SPI_CR2_TXEIE (1 << 7)
+
+/* RXNEIE: RX buffer not empty interrupt enable */
+#define SPI_CR2_RXNEIE (1 << 6)
+
+/* ERRIE: Error interrupt enable */
+#define SPI_CR2_ERRIE (1 << 5)
+
+/* Bits [4:3]: Reserved. Forced to 0 by hardware. */
+
+/* SSOE: SS output enable */
+#define SPI_CR2_SSOE (1 << 2)
+
+/* TXDMAEN: Tx buffer DMA enable */
+#define SPI_CR2_TXDMAEN (1 << 1)
+
+/* RXDMAEN: Rx buffer DMA enable */
+#define SPI_CR2_RXDMAEN (1 << 0)
+
+/* --- SPI_SR values ------------------------------------------------------- */
+
+/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
+
+/* BSY: Busy flag */
+#define SPI_SR_BSY (1 << 7)
+
+/* OVR: Overrun flag */
+#define SPI_SR_OVR (1 << 6)
+
+/* MODF: Mode fault */
+#define SPI_SR_MODF (1 << 5)
+
+/* CRCERR: CRC error flag */
+#define SPI_SR_CRCERR (1 << 4)
+
+/* UDR: Underrun flag */
+#define SPI_SR_UDR (1 << 3)
+
+/* CHSIDE: Channel side */
+#define SPI_SR_CHSIDE (1 << 2)
+
+/* TXE: Transmit buffer empty */
+#define SPI_SR_TXE (1 << 1)
+
+/* RXNE: Receive buffer not empty */
+#define SPI_SR_RXNE (1 << 0)
+
+/* --- SPI_SR values ------------------------------------------------------- */
+
+/* SPI_DR[15:0]: Data Register. */
+
+/* --- SPI_CRCPR values ---------------------------------------------------- */
+
+/* SPI_CRCPR [15:0]: CRC Polynomial Register. */
+
+/* --- SPI_RXCRCR values --------------------------------------------------- */
+
+/* SPI_RXCRCR [15:0]: RX CRC Register. */
+
+/* --- SPI_TXCRCR values --------------------------------------------------- */
+
+/* SPI_TXCRCR [15:0]: TX CRC Register. */
+
+/* --- SPI_I2SCFGR values -------------------------------------------------- */
+
+/* Bits [15:12]: Reserved. Forced to 0 by hardware. */
+
+/* I2SMOD: I2S mode selection */
+#define SPI_I2SCFGR_I2SMOD (1 << 11)
+
+/* I2SE: I2S Enable */
+#define SPI_I2SCFGR_I2SE (1 << 10)
+
+/* I2SCFG[9:8]: I2S configuration mode */
+#define SPI_I2SCFGR_I2SCFG_LSB 8
+#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0
+#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1
+#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2
+#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3
+
+/* PCMSYNC: PCM frame synchronization */
+#define SPI_I2SCFGR_PCMSYNC (1 << 7)
+
+/* Bit 6: Reserved. Forced to 0 by hardware. */
+
+/* I2SSTD[5:4]: I2S standard selection */
+#define SPI_I2SCFGR_I2SSTD_LSB 4
+#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0
+#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1
+#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2
+#define SPI_I2SCFGR_I2SSTD_PCM 0x3
+
+/* CKPOL: Steady state clock polarity */
+#define SPI_I2SCFGR_CKPOL (1 << 3)
+
+/* DATLEN[2:1]: Data length to be transferred */
+#define SPI_I2SCFGR_DATLEN_LSB 1
+#define SPI_I2SCFGR_DATLEN_16BIT 0x0
+#define SPI_I2SCFGR_DATLEN_24BIT 0x1
+#define SPI_I2SCFGR_DATLEN_32BIT 0x2
+
+/* CHLEN: Channel length */
+#define SPI_I2SCFGR_CHLEN (1 << 0)
+
+/* --- SPI_I2SPR values ---------------------------------------------------- */
+
+/* Bits [15:10]: Reserved. Forced to 0 by hardware. */
+
+/* MCKOE: Master clock output enable */
+#define SPI_I2SPR_MCKOE (1 << 9)
+
+/* ODD: Odd factor for the prescaler */
+#define SPI_I2SPR_ODD (1 << 8)
+
+/* I2SDIV[7:0]: I2S Linear prescaler */
+/* 0 and 1 are forbidden values */
+
+/* --- Function prototypes ------------------------------------------------- */
+
+int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
+void spi_enable(u32 spi);
+void spi_disable(u32 spi);
+void spi_write(u32 spi, u16 data);
+void spi_send(u32 spi, u16 data);
+u16 spi_read(u32 spi);
+void spi_set_bidirectional_mode(u32 spi);
+void spi_set_unidirectional_mode(u32 spi);
+void spi_set_bidirectional_receive_only_mode(u32 spi);
+void spi_set_bidirectional_transmit_only_mode(u32 spi);
+void spi_enable_crc(u32 spi);
+void spi_disable_crc(u32 spi);
+void spi_set_next_tx_from_buffer(u32 spi);
+void spi_set_next_tx_from_crc(u32 spi);
+void spi_set_dff_8bit(u32 spi);
+void spi_set_dff_16bit(u32 spi);
+void spi_set_full_duplex_mode(u32 spi);
+void spi_set_receive_only_mode(u32 spi);
+void spi_disable_software_slave_management(u32 spi);
+void spi_enable_software_slave_management(u32 spi);
+void spi_set_nss_high(u32 spi);
+void spi_set_nss_low(u32 spi);
+void spi_send_lsb_first(u32 spi);
+void spi_send_msb_first(u32 spi);
+void spi_set_baudrate_prescaler(u32 spi, u8 baudrate);
+void spi_set_master_mode(u32 spi);
+void spi_set_slave_mode(u32 spi);
+void spi_set_clock_polarity_1(u32 spi);
+void spi_set_clock_polarity_0(u32 spi);
+void spi_set_clock_phase_1(u32 spi);
+void spi_set_clock_phase_0(u32 spi);
+void spi_enable_tx_buffer_empty_interrupt(u32 spi);
+void spi_disable_tx_buffer_empty_interrupt(u32 spi);
+void spi_enable_rx_buffer_not_empty_interrupt(u32 spi);
+void spi_disable_rx_buffer_not_empty_interrupt(u32 spi);
+void spi_enable_error_interrupt(u32 spi);
+void spi_disable_error_interrupt(u32 spi);
+void spi_enable_ss_output(u32 spi);
+void spi_disable_ss_output(u32 spi);
+void spi_enable_tx_dma(u32 spi);
+void spi_disable_tx_dma(u32 spi);
+void spi_enable_rx_dma(u32 spi);
+void spi_disable_rx_dma(u32 spi);
+
+#endif
diff --git a/include/libopencm3/stm32/systick.h b/include/libopencm3/stm32/systick.h
new file mode 100644
index 0000000..7c2c9a3
--- /dev/null
+++ b/include/libopencm3/stm32/systick.h
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SYSTICK_H
+#define LIBOPENCM3_SYSTICK_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- SYSTICK registers --------------------------------------------------- */
+
+/* Control and status register (STK_CTRL) */
+#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00)
+
+/* reload value register (STK_LOAD) */
+#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04)
+
+/* current value register (STK_VAL) */
+#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08)
+
+/* calibration value register (STK_CALIB) */
+#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C)
+
+/* --- STK_CTRL values ----------------------------------------------------- */
+/* Bits [31:17] Reserved, must be kept cleared. */
+/* COUNTFLAG: */
+#define STK_CTRL_COUNTFLAG (1 << 16)
+/* Bits [15:3] Reserved, must be kept cleared. */
+/* CLKSOURCE: Clock source selection */
+#define STK_CTRL_CLKSOURCE (1 << 2)
+#define STK_CTRL_CLKSOURCE_LSB 2
+#define STK_CTRL_CLKSOURCE_AHB_DIV8 0
+#define STK_CTRL_CLKSOURCE_AHB 1
+/* TICKINT: SysTick exception request enable */
+#define STK_CTRL_TICKINT (1 << 1)
+/* ENABLE: Counter enable */
+#define STK_CTRL_ENABLE (1 << 0)
+
+/* --- STK_LOAD values ----------------------------------------------------- */
+/* Bits [31:24] Reserved, must be kept cleared. */
+/* RELOAD[23:0]: RELOAD value */
+
+/* --- STK_VAL values ------------------------------------------------------ */
+/* Bits [31:24] Reserved, must be kept cleared. */
+/* CURRENT[23:0]: Current counter value */
+
+/* --- STK_CALIB values ---------------------------------------------------- */
+/* NOREF: NOREF flag */
+#define STK_CALIB_NOREF (1 << 31)
+/* SKEW: SKEW flag */
+#define STK_CALIB_SKEW (1 << 30)
+/* Bits [29:24] Reserved, must be kept cleared. */
+/* TENMS[23:0]: Calibration value */
+
+/* --- Function Prototypes ------------------------------------------------- */
+
+void systick_set_reload(u32 value);
+u32 systick_get_value(void);
+void systick_set_clocksource(u8 clocksource);
+void systick_interrupt_enable(void);
+void systick_interrupt_disable(void);
+void systick_counter_enable(void);
+void systick_counter_disable(void);
+u8 systick_get_countflag(void);
+
+#endif
diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
new file mode 100644
index 0000000..dabf732
--- /dev/null
+++ b/include/libopencm3/stm32/timer.h
@@ -0,0 +1,807 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_TIMER_H
+#define LIBOPENCM3_TIMER_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* Timer register base adresses (for convenience) */
+#define TIM1 TIM1_BASE
+#define TIM2 TIM2_BASE
+#define TIM3 TIM3_BASE
+#define TIM4 TIM4_BASE
+#define TIM5 TIM5_BASE
+#define TIM6 TIM6_BASE
+#define TIM7 TIM7_BASE
+#define TIM8 TIM8_BASE
+
+/* --- Timer registers ----------------------------------------------------- */
+
+/* Control register 1 (TIMx_CR1) */
+#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00)
+#define TIM1_CR1 TIM_CR1(TIM1)
+#define TIM2_CR1 TIM_CR1(TIM2)
+#define TIM3_CR1 TIM_CR1(TIM3)
+#define TIM4_CR1 TIM_CR1(TIM4)
+#define TIM5_CR1 TIM_CR1(TIM5)
+#define TIM6_CR1 TIM_CR1(TIM6)
+#define TIM7_CR1 TIM_CR1(TIM7)
+#define TIM8_CR1 TIM_CR1(TIM8)
+
+/* Control register 2 (TIMx_CR2) */
+#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04)
+#define TIM1_CR2 TIM_CR2(TIM1)
+#define TIM2_CR2 TIM_CR2(TIM2)
+#define TIM3_CR2 TIM_CR2(TIM3)
+#define TIM4_CR2 TIM_CR2(TIM4)
+#define TIM5_CR2 TIM_CR2(TIM5)
+#define TIM6_CR2 TIM_CR2(TIM6)
+#define TIM7_CR2 TIM_CR2(TIM7)
+#define TIM8_CR2 TIM_CR2(TIM8)
+
+/* Slave mode control register (TIMx_SMCR) */
+#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08)
+#define TIM1_SMCR TIM_SMCR(TIM1)
+#define TIM2_SMCR TIM_SMCR(TIM2)
+#define TIM3_SMCR TIM_SMCR(TIM3)
+#define TIM4_SMCR TIM_SMCR(TIM4)
+#define TIM5_SMCR TIM_SMCR(TIM5)
+#define TIM8_SMCR TIM_SMCR(TIM8)
+
+/* DMA/Interrupt enable register (TIMx_DIER) */
+#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C)
+#define TIM1_DIER TIM_DIER(TIM1)
+#define TIM2_DIER TIM_DIER(TIM2)
+#define TIM3_DIER TIM_DIER(TIM3)
+#define TIM4_DIER TIM_DIER(TIM4)
+#define TIM5_DIER TIM_DIER(TIM5)
+#define TIM6_DIER TIM_DIER(TIM6)
+#define TIM7_DIER TIM_DIER(TIM7)
+#define TIM8_DIER TIM_DIER(TIM8)
+
+/* Status register (TIMx_SR) */
+#define TIM_SR(tim_base) MMIO32(tim_base + 0x10)
+#define TIM1_SR TIM_SR(TIM1)
+#define TIM2_SR TIM_SR(TIM2)
+#define TIM3_SR TIM_SR(TIM3)
+#define TIM4_SR TIM_SR(TIM4)
+#define TIM5_SR TIM_SR(TIM5)
+#define TIM6_SR TIM_SR(TIM6)
+#define TIM7_SR TIM_SR(TIM7)
+#define TIM8_SR TIM_SR(TIM8)
+
+/* Event generation register (TIMx_EGR) */
+#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14)
+#define TIM1_EGR TIM_EGR(TIM1)
+#define TIM2_EGR TIM_EGR(TIM2)
+#define TIM3_EGR TIM_EGR(TIM3)
+#define TIM4_EGR TIM_EGR(TIM4)
+#define TIM5_EGR TIM_EGR(TIM5)
+#define TIM6_EGR TIM_EGR(TIM6)
+#define TIM7_EGR TIM_EGR(TIM7)
+#define TIM8_EGR TIM_EGR(TIM8)
+
+/* Capture/compare mode register 1 (TIMx_CCMR1) */
+#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18)
+#define TIM1_CCMR1 TIM_CCMR1(TIM1)
+#define TIM2_CCMR1 TIM_CCMR1(TIM2)
+#define TIM3_CCMR1 TIM_CCMR1(TIM3)
+#define TIM4_CCMR1 TIM_CCMR1(TIM4)
+#define TIM5_CCMR1 TIM_CCMR1(TIM5)
+#define TIM8_CCMR1 TIM_CCMR1(TIM8)
+
+/* Capture/compare mode register 2 (TIMx_CCMR2) */
+#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C)
+#define TIM1_CCMR2 TIM_CCMR2(TIM1)
+#define TIM2_CCMR2 TIM_CCMR2(TIM2)
+#define TIM3_CCMR2 TIM_CCMR2(TIM3)
+#define TIM4_CCMR2 TIM_CCMR2(TIM4)
+#define TIM5_CCMR2 TIM_CCMR2(TIM5)
+#define TIM8_CCMR2 TIM_CCMR2(TIM8)
+
+/* Capture/compare enable register (TIMx_CCER) */
+#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20)
+#define TIM1_CCER TIM_CCER(TIM1)
+#define TIM2_CCER TIM_CCER(TIM2)
+#define TIM3_CCER TIM_CCER(TIM3)
+#define TIM4_CCER TIM_CCER(TIM4)
+#define TIM5_CCER TIM_CCER(TIM5)
+#define TIM8_CCER TIM_CCER(TIM8)
+
+/* Counter (TIMx_CNT) */
+#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24)
+#define TIM1_CNT TIM_CNT(TIM1)
+#define TIM2_CNT TIM_CNT(TIM2)
+#define TIM3_CNT TIM_CNT(TIM3)
+#define TIM4_CNT TIM_CNT(TIM4)
+#define TIM5_CNT TIM_CNT(TIM5)
+#define TIM6_CNT TIM_CNT(TIM6)
+#define TIM7_CNT TIM_CNT(TIM7)
+#define TIM8_CNT TIM_CNT(TIM8)
+
+/* Prescaler (TIMx_PSC) */
+#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28)
+#define TIM1_PSC TIM_PSC(TIM1)
+#define TIM2_PSC TIM_PSC(TIM2)
+#define TIM3_PSC TIM_PSC(TIM3)
+#define TIM4_PSC TIM_PSC(TIM4)
+#define TIM5_PSC TIM_PSC(TIM5)
+#define TIM6_PSC TIM_PSC(TIM6)
+#define TIM7_PSC TIM_PSC(TIM7)
+#define TIM8_PSC TIM_PSC(TIM8)
+
+/* Auto-reload register (TIMx_ARR) */
+#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C)
+#define TIM1_ARR TIM_ARR(TIM1)
+#define TIM2_ARR TIM_ARR(TIM2)
+#define TIM3_ARR TIM_ARR(TIM3)
+#define TIM4_ARR TIM_ARR(TIM4)
+#define TIM5_ARR TIM_ARR(TIM5)
+#define TIM6_ARR TIM_ARR(TIM6)
+#define TIM7_ARR TIM_ARR(TIM7)
+#define TIM8_ARR TIM_ARR(TIM8)
+
+/* Repetition counter register (TIMx_RCR) */
+#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30)
+#define TIM1_RCR TIM_RCR(TIM1)
+#define TIM8_RCR TIM_RCR(TIM8)
+
+/* Capture/compare register 1 (TIMx_CCR1) */
+#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34)
+#define TIM1_CCR1 TIM_CCR1(TIM1)
+#define TIM2_CCR1 TIM_CCR1(TIM2)
+#define TIM3_CCR1 TIM_CCR1(TIM3)
+#define TIM4_CCR1 TIM_CCR1(TIM4)
+#define TIM5_CCR1 TIM_CCR1(TIM5)
+#define TIM8_CCR1 TIM_CCR1(TIM8)
+
+/* Capture/compare register 2 (TIMx_CCR2) */
+#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38)
+#define TIM1_CCR2 TIM_CCR2(TIM1)
+#define TIM2_CCR2 TIM_CCR2(TIM2)
+#define TIM3_CCR2 TIM_CCR2(TIM3)
+#define TIM4_CCR2 TIM_CCR2(TIM4)
+#define TIM5_CCR2 TIM_CCR2(TIM5)
+#define TIM8_CCR2 TIM_CCR2(TIM8)
+
+/* Capture/compare register 3 (TIMx_CCR3) */
+#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C)
+#define TIM1_CCR3 TIM_CCR3(TIM1)
+#define TIM2_CCR3 TIM_CCR3(TIM2)
+#define TIM3_CCR3 TIM_CCR3(TIM3)
+#define TIM4_CCR3 TIM_CCR3(TIM4)
+#define TIM5_CCR3 TIM_CCR3(TIM5)
+#define TIM8_CCR3 TIM_CCR3(TIM8)
+
+/* Capture/compare register 4 (TIMx_CCR4) */
+#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40)
+#define TIM1_CCR4 TIM_CCR4(TIM1)
+#define TIM2_CCR4 TIM_CCR4(TIM2)
+#define TIM3_CCR4 TIM_CCR4(TIM3)
+#define TIM4_CCR4 TIM_CCR4(TIM4)
+#define TIM5_CCR4 TIM_CCR4(TIM5)
+#define TIM8_CCR4 TIM_CCR4(TIM8)
+
+/* Break and dead-time register (TIMx_BDTR) */
+#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44)
+#define TIM1_BDTR TIM_BDTR(TIM1)
+#define TIM8_BDTR TIM_BDTR(TIM8)
+
+/* DMA control register (TIMx_DCR) */
+#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48)
+#define TIM1_DCR TIM_DCR(TIM1)
+#define TIM2_DCR TIM_DCR(TIM2)
+#define TIM3_DCR TIM_DCR(TIM3)
+#define TIM4_DCR TIM_DCR(TIM4)
+#define TIM5_DCR TIM_DCR(TIM5)
+#define TIM8_DCR TIM_DCR(TIM8)
+
+/* DMA address for full transfer (TIMx_DMAR) */
+#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C)
+#define TIM1_DMAR TIM_DMAR(TIM1)
+#define TIM2_DMAR TIM_DMAR(TIM2)
+#define TIM3_DMAR TIM_DMAR(TIM3)
+#define TIM4_DMAR TIM_DMAR(TIM4)
+#define TIM5_DMAR TIM_DMAR(TIM5)
+#define TIM8_DMAR TIM_DMAR(TIM8)
+
+/* --- TIMx_CR1 values ----------------------------------------------------- */
+
+/* CKD[1:0]: Clock division */
+#define TIM_CR1_CKD_CK_INT (0x0 << 8)
+#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8)
+#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8)
+#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8)
+
+/* ARPE: Auto-reload preload enable */
+#define TIM_CR1_ARPE (1 << 7)
+
+/* CMS[1:0]: Center-aligned mode selection */
+#define TIM_CR1_CMS_EDGE (0x0 << 5)
+#define TIM_CR1_CMS_CENTER_1 (0x1 << 5)
+#define TIM_CR1_CMS_CENTER_2 (0x2 << 5)
+#define TIM_CR1_CMS_CENTER_3 (0x3 << 5)
+
+/* DIR: Direction */
+#define TIM_CR1_DIR_UP (0 << 4)
+#define TIM_CR1_DIR_DOWN (1 << 4)
+
+/* OPM: One pulse mode */
+#define TIM_CR1_OPM (1 << 3)
+
+/* URS: Update request source */
+#define TIM_CR1_URS (1 << 2)
+
+/* UDIS: Update disable */
+#define TIM_CR1_UDIS (1 << 1)
+
+/* CEN: Counter enable */
+#define TIM_CR1_CEN (1 << 0)
+
+/* --- TIMx_CR2 values ----------------------------------------------------- */
+
+/* OIS4: Output idle state 4 (OC4 output) */
+#define TIM_CR2_OIS4 (1 << 14)
+
+/* OIS3N: Output idle state 3 (OC3N output) */
+#define TIM_CR2_OIS3N (1 << 13)
+
+/* OIS3: Output idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3 (1 << 12)
+
+/* OIS2N: Output idle state 2 (OC2N output) */
+#define TIM_CR2_OIS2N (1 << 11)
+
+/* OIS2: Output idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2 (1 << 10)
+
+/* OIS1N: Output idle state 1 (OC1N output) */
+#define TIM_CR2_OIS1N (1 << 9)
+
+/* OIS1: Output idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1 (1 << 8)
+#define TIM_CR2_OIS_MASK (0x7f << 8)
+
+/* TI1S: TI1 selection */
+#define TIM_CR2_TI1S (1 << 7)
+
+/* MMS[2:0]: Master mode selection */
+#define TIM_CR2_MMS_RESET (0x0 << 4)
+#define TIM_CR2_MMS_ENABLE (0x1 << 4)
+#define TIM_CR2_MMS_UPDATE (0x2 << 4)
+#define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4)
+#define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4)
+#define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4)
+#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4)
+#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4)
+#define TIM_CR2_MMS_MASK (0x7 << 4)
+
+/* CCDS: Capture/compare DMA selection */
+#define TIM_CR2_CCDS (1 << 3)
+
+/* CCUS: Capture/compare control update selection */
+#define TIM_CR2_CCUS (1 << 2)
+
+/* CCPC: Capture/compare preload control */
+#define TIM_CR2_CCPC (1 << 0)
+
+/* --- TIMx_SMCR values ---------------------------------------------------- */
+
+/* ETP: External trigger polarity */
+#define TIM_SMCR_ETP (1 << 15)
+
+/* ECE: External clock enable */
+#define TIM_SMCR_ECE (1 << 14)
+
+/* ETPS[1:0]: External trigger prescaler */
+#define TIM_SMCR_ETPS_OFF (0x0 << 12)
+#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12)
+#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12)
+#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12)
+
+/* ETF[3:0]: External trigger filter */
+#define TIM_SMCR_ETF_OFF (0x0 << 8)
+#define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8)
+#define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8)
+#define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8)
+#define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8)
+#define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8)
+#define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8)
+#define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8)
+#define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8)
+#define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8)
+#define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8)
+#define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8)
+#define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8)
+#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8)
+#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8)
+#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8)
+
+/* MSM: Master/slave mode */
+#define TIM_SMCR_MSM (1 << 7)
+
+/* TS[2:0]: Trigger selection */
+#define TIM_SMCR_TS_ITR0 (0x0 << 4)
+#define TIM_SMCR_TS_ITR1 (0x1 << 4)
+#define TIM_SMCR_TS_ITR2 (0x2 << 4)
+#define TIM_SMCR_TS_ITR3 (0x3 << 4)
+#define TIM_SMCR_TS_IT1F_ED (0x4 << 4)
+#define TIM_SMCR_TS_IT1FP1 (0x5 << 4)
+#define TIM_SMCR_TS_IT1FP2 (0x6 << 4)
+#define TIM_SMCR_TS_ETRF (0x7 << 4)
+
+/* SMS[2:0]: Slave mode selection */
+#define TIM_SMCR_SMS_OFF (0x0 << 0)
+#define TIM_SMCR_SMS_EM1 (0x1 << 0)
+#define TIM_SMCR_SMS_EM2 (0x2 << 0)
+#define TIM_SMCR_SMS_EM3 (0x3 << 0)
+#define TIM_SMCR_SMS_RM (0x4 << 0)
+#define TIM_SMCR_SMS_GM (0x5 << 0)
+#define TIM_SMCR_SMS_TM (0x6 << 0)
+#define TIM_SMCR_SMS_ECM1 (0x7 << 0)
+
+/* --- TIMx_DIER values ---------------------------------------------------- */
+
+/* TDE: Trigger DMA request enable */
+#define TIM_DIER_TDE (1 << 14)
+
+/* COMDE: COM DMA request enable */
+#define TIM_DIER_COMDE (1 << 13)
+
+/* CC4DE: Capture/Compare 4 DMA request enable */
+#define TIM_DIER_CC4DE (1 << 12)
+
+/* CC3DE: Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC3DE (1 << 11)
+
+/* CC2DE: Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC2DE (1 << 10)
+
+/* CC1DE: Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC1DE (1 << 9)
+
+/* UDE: Update DMA request enable */
+#define TIM_DIER_UDE (1 << 8)
+
+/* BIE: Break interrupt enable */
+#define TIM_DIER_BIE (1 << 7)
+
+/* TIE: Trigger interrupt enable */
+#define TIM_DIER_TIE (1 << 6)
+
+/* COMIE: COM interrupt enable */
+#define TIM_DIER_COMIE (1 << 5)
+
+/* CC4IE: Capture/compare 4 interrupt enable */
+#define TIM_DIER_CC4IE (1 << 4)
+
+/* CC3IE: Capture/compare 3 interrupt enable */
+#define TIM_DIER_CC3IE (1 << 3)
+
+/* CC2IE: Capture/compare 2 interrupt enable */
+#define TIM_DIER_CC2IE (1 << 2)
+
+/* CC1IE: Capture/compare 1 interrupt enable */
+#define TIM_DIER_CC1IE (1 << 1)
+
+/* UIE: Update interrupt enable */
+#define TIM_DIER_UIE (1 << 0)
+
+/* --- TIMx_SR values ------------------------------------------------------ */
+
+/* CC4OF: Capture/compare 4 overcapture flag */
+#define TIM_SR_CC4OF (1 << 12)
+
+/* CC3OF: Capture/compare 3 overcapture flag */
+#define TIM_SR_CC3OF (1 << 11)
+
+/* CC2OF: Capture/compare 2 overcapture flag */
+#define TIM_SR_CC2OF (1 << 10)
+
+/* CC1OF: Capture/compare 1 overcapture flag */
+#define TIM_SR_CC1OF (1 << 9)
+
+/* BIF: Break interrupt flag */
+#define TIM_SR_BIF (1 << 7)
+
+/* TIF: Trigger interrupt flag */
+#define TIM_SR_TIF (1 << 6)
+
+/* COMIF: COM interrupt flag */
+#define TIM_SR_COMIF (1 << 5)
+
+/* CC4IF: Capture/compare 4 interrupt flag */
+#define TIM_SR_CC4IF (1 << 4)
+
+/* CC3IF: Capture/compare 3 interrupt flag */
+#define TIM_SR_CC3IF (1 << 3)
+
+/* CC2IF: Capture/compare 2 interrupt flag */
+#define TIM_SR_CC2IF (1 << 2)
+
+/* CC1IF: Capture/compare 1 interrupt flag */
+#define TIM_SR_CC1IF (1 << 1)
+
+/* UIF: Update interrupt flag */
+#define TIM_SR_UIF (1 << 0)
+
+/* --- TIMx_EGR values ----------------------------------------------------- */
+
+/* BG: Break generation */
+#define TIM_EGR_BG (1 << 7)
+
+/* TG: Trigger generation */
+#define TIM_EGR_TG (1 << 6)
+
+/* COMG: Capture/compare control update generation */
+#define TIM_EGR_COMG (1 << 5)
+
+/* CC4G: Capture/compare 4 generation */
+#define TIM_EGR_CC4G (1 << 4)
+
+/* CC3G: Capture/compare 3 generation */
+#define TIM_EGR_CC3G (1 << 3)
+
+/* CC2G: Capture/compare 2 generation */
+#define TIM_EGR_CC2G (1 << 2)
+
+/* CC1G: Capture/compare 1 generation */
+#define TIM_EGR_CC1G (1 << 1)
+
+/* UG: Update generation */
+#define TIM_EGR_UG (1 << 0)
+
+/* --- TIMx_CCMR1 values --------------------------------------------------- */
+
+/* --- Output compare mode --- */
+
+/* OC2CE: Output compare 2 clear enable */
+#define TIM_CCMR1_OC2CE (1 << 15)
+
+/* OC2M[2:0]: Output compare 2 mode */
+#define TIM_CCMR1_OC2M_FROZEN (0x0 << 12)
+#define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12)
+#define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12)
+#define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12)
+#define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12)
+#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12)
+#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12)
+#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12)
+
+/* OC2PE: Output compare 2 preload enable */
+#define TIM_CCMR1_OC2PE (1 << 11)
+
+/* OC2FE: Output compare 2 fast enable */
+#define TIM_CCMR1_OC2FE (1 << 10)
+
+/* CC2S[1:0]: Capture/compare 2 selection */
+/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
+ * TIMx_CCER). */
+#define TIM_CCMR1_CC2S_OUT (0x0 << 8)
+#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8)
+#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8)
+#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8)
+
+/* OC1CE: Output compare 1 clear enable */
+#define TIM_CCMR1_OC1CE (1 << 7)
+
+/* OC1M[2:0]: Output compare 1 mode */
+#define TIM_CCMR1_OC1M_FROZEN (0x0 << 4)
+#define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4)
+#define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4)
+#define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4)
+#define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4)
+#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4)
+#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4)
+#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4)
+
+/* OC1PE: Output compare 1 preload enable */
+#define TIM_CCMR1_OC1PE (1 << 3)
+
+/* OC1FE: Output compare 1 fast enable */
+#define TIM_CCMR1_OC1FE (1 << 2)
+
+/* CC1S[1:0]: Capture/compare 1 selection */
+/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
+ * TIMx_CCER). */
+#define TIM_CCMR1_CC1S_OUT (0x0 << 0)
+#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0)
+#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0)
+#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0)
+
+/* --- Input capture mode --- */
+
+/* IC2F[3:0]: Input capture 2 filter */
+#define TIM_CCMR1_IC2F_OFF (0x0 << 12)
+#define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12)
+#define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12)
+#define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12)
+#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12)
+
+/* IC2PSC[1:0]: Input capture 2 prescaler */
+#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10)
+#define TIM_CCMR1_IC2PSC_2 (0x1 << 10)
+#define TIM_CCMR1_IC2PSC_4 (0x2 << 10)
+#define TIM_CCMR1_IC2PSC_8 (0x3 << 10)
+
+/* IC1F[3:0]: Input capture 1 filter */
+#define TIM_CCMR1_IC1F_OFF (0x0 << 4)
+#define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4)
+#define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4)
+#define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4)
+#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4)
+
+/* IC1PSC[1:0]: Input capture 1 prescaler */
+#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2)
+#define TIM_CCMR1_IC1PSC_2 (0x1 << 2)
+#define TIM_CCMR1_IC1PSC_4 (0x2 << 2)
+#define TIM_CCMR1_IC1PSC_8 (0x3 << 2)
+
+/* --- TIMx_CCMR2 values --------------------------------------------------- */
+
+/* --- Output compare mode --- */
+
+/* OC4CE: Output compare 4 clear enable */
+#define TIM_CCMR2_OC4CE (1 << 15)
+
+/* OC4M[2:0]: Output compare 4 mode */
+#define TIM_CCMR2_OC4M_FROZEN (0x0 << 12)
+#define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12)
+#define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12)
+#define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12)
+#define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12)
+#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12)
+#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12)
+#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12)
+
+/* OC4PE: Output compare 4 preload enable */
+#define TIM_CCMR2_OC4PE (1 << 11)
+
+/* OC4FE: Output compare 4 fast enable */
+#define TIM_CCMR2_OC4FE (1 << 10)
+
+/* CC4S[1:0]: Capture/compare 4 selection */
+/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
+ * TIMx_CCER). */
+#define TIM_CCMR2_CC4S_OUT (0x0 << 8)
+#define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8)
+#define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8)
+#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8)
+
+/* OC3CE: Output compare 3 clear enable */
+#define TIM_CCMR2_OC1CE (1 << 7)
+
+/* OC3M[2:0]: Output compare 3 mode */
+#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4)
+#define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4)
+#define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4)
+#define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4)
+#define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4)
+#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4)
+#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4)
+#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4)
+
+/* OC3PE: Output compare 3 preload enable */
+#define TIM_CCMR2_OC3PE (1 << 3)
+
+/* OC3FE: Output compare 3 fast enable */
+#define TIM_CCMR2_OC3FE (1 << 2)
+
+/* CC3S[1:0]: Capture/compare 3 selection */
+/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
+ * TIMx_CCER). */
+#define TIM_CCMR2_CC3S_OUT (0x0 << 0)
+#define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0)
+#define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0)
+#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0)
+
+/* --- Input capture mode --- */
+
+/* IC4F[3:0]: Input capture 4 filter */
+#define TIM_CCMR2_IC4F_OFF (0x0 << 12)
+#define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12)
+#define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12)
+#define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12)
+#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12)
+
+/* IC4PSC[1:0]: Input capture 4 prescaler */
+#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10)
+#define TIM_CCMR2_IC4PSC_2 (0x1 << 10)
+#define TIM_CCMR2_IC4PSC_4 (0x2 << 10)
+#define TIM_CCMR2_IC4PSC_8 (0x3 << 10)
+
+/* IC3F[3:0]: Input capture 3 filter */
+#define TIM_CCMR2_IC3F_OFF (0x0 << 4)
+#define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4)
+#define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4)
+#define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4)
+#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4)
+
+/* IC3PSC[1:0]: Input capture 3 prescaler */
+#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2)
+#define TIM_CCMR2_IC3PSC_2 (0x1 << 2)
+#define TIM_CCMR2_IC3PSC_4 (0x2 << 2)
+#define TIM_CCMR2_IC3PSC_8 (0x3 << 2)
+
+/* --- TIMx_CCER values ---------------------------------------------------- */
+
+/* CC4P: Capture/compare 4 output polarity */
+#define TIM_CCER_CC4P (1 << 13)
+
+/* CC4E: Capture/compare 4 output enable */
+#define TIM_CCER_CC4E (1 << 12)
+
+/* CC3NP: Capture/compare 3 complementary output polarity */
+#define TIM_CCER_CC3NP (1 << 11)
+
+/* CC3NE: Capture/compare 3 complementary output enable */
+#define TIM_CCER_CC3NE (1 << 10)
+
+/* CC3P: Capture/compare 3 output polarity */
+#define TIM_CCER_CC3P (1 << 9)
+
+/* CC3E: Capture/compare 3 output enable */
+#define TIM_CCER_CC3E (1 << 8)
+
+/* CC2NP: Capture/compare 2 complementary output polarity */
+#define TIM_CCER_CC2NP (1 << 7)
+
+/* CC2NE: Capture/compare 2 complementary output enable */
+#define TIM_CCER_CC2NE (1 << 6)
+
+/* CC2P: Capture/compare 2 output polarity */
+#define TIM_CCER_CC2P (1 << 5)
+
+/* CC2E: Capture/compare 2 output enable */
+#define TIM_CCER_CC2E (1 << 4)
+
+/* CC1NP: Capture/compare 1 complementary output polarity */
+#define TIM_CCER_CC1NP (1 << 3)
+
+/* CC1NE: Capture/compare 1 complementary output enable */
+#define TIM_CCER_CC1NE (1 << 2)
+
+/* CC1P: Capture/compare 1 output polarity */
+#define TIM_CCER_CC1P (1 << 1)
+
+/* CC1E: Capture/compare 1 output enable */
+#define TIM_CCER_CC1E (1 << 0)
+
+/* --- TIMx_CNT values ----------------------------------------------------- */
+
+/* CNT[15:0]: Counter value */
+
+/* --- TIMx_PSC values ----------------------------------------------------- */
+
+/* PSC[15:0]: Prescaler value */
+
+/* --- TIMx_ARR values ----------------------------------------------------- */
+
+/* ARR[15:0]: Prescaler value */
+
+/* --- TIMx_RCR values ----------------------------------------------------- */
+
+/* REP[15:0]: Repetition counter value */
+
+/* --- TIMx_CCR1 values ---------------------------------------------------- */
+
+/* CCR1[15:0]: Capture/compare 1 value */
+
+/* --- TIMx_CCR2 values ---------------------------------------------------- */
+
+/* CCR2[15:0]: Capture/compare 2 value */
+
+/* --- TIMx_CCR3 values ---------------------------------------------------- */
+
+/* CCR3[15:0]: Capture/compare 3 value */
+
+/* --- TIMx_CCR4 values ---------------------------------------------------- */
+
+/* CCR4[15:0]: Capture/compare 4 value */
+
+/* --- TIMx_BDTR values ---------------------------------------------------- */
+
+/* MOE: Main output enable */
+#define TIM_BDTR_MOE (1 << 15)
+
+/* AOE: Automatic output enable */
+#define TIM_BDTR_AOE (1 << 14)
+
+/* BKP: Break polarity */
+#define TIM_BDTR_BKP (1 << 13)
+
+/* BKE: Break enable */
+#define TIM_BDTR_BKE (1 << 12)
+
+/* OSSR: Off-state selection of run mode */
+#define TIM_BDTR_OSSR (1 << 11)
+
+/* OSSI: Off-state selection of idle mode */
+#define TIM_BDTR_OSSI (1 << 10)
+
+/* LOCK[1:0]: Lock configuration */
+#define TIM_BDTR_LOCK_OFF (0x0 << 8)
+#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8)
+#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8)
+#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8)
+
+/* DTG[7:0]: Dead-time generator set-up */
+#define TIM_BDTR_DTG_MASK 0x00FF
+
+/* --- TIMx_DCR values ----------------------------------------------------- */
+
+/* DBL[4:0]: DMA burst length */
+#define TIM_BDTR_DBL_MASK (0x1F << 8)
+
+/* DBA[4:0]: DMA base address */
+#define TIM_BDTR_DBA_MASK (0x1F << 0)
+
+/* --- TIMx_DMAR values ---------------------------------------------------- */
+
+/* DMAB[15:0]: DMA register for burst accesses */
+
+#endif
diff --git a/include/libopencm3/stm32/tools.h b/include/libopencm3/stm32/tools.h
new file mode 100644
index 0000000..ac7f0bf
--- /dev/null
+++ b/include/libopencm3/stm32/tools.h
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_TOOLS_H
+#define LIBOPENCM3_TOOLS_H
+
+/*
+ * Register accessors / manipulators
+ */
+
+/* Get register content. */
+#define GET_REG(REG) ((u16) *REG)
+
+/* Set register content. */
+#define SET_REG(REG, VAL) (*REG = (u16)VAL)
+
+/* Clear register bit. */
+#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT))
+
+/* Clear register bit masking out some bits that must not be touched. */
+#define CLR_REG_BIT_MSK(REG, MSK, BIT) \
+ SET_REG(REG, (GET_REG(REG) & MSK & (~BIT)))
+
+/* Get masked out bit value. */
+#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT)
+
+/*
+ * Set/reset a bit in a masked window by using toggle mechanism.
+ *
+ * This means that we look at the bits in the bit window designated by
+ * the mask. If the bit in the masked window is not matching the
+ * bitmask BIT then we write 1 and if the bit in the masked window is
+ * matching the bitmask BIT we write 0.
+ *
+ * TODO: We may need a faster implementation of that one?
+ */
+#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \
+do { \
+ register u16 toggle_mask = GET_REG(REG) & (MSK); \
+ register u16 bit_selector; \
+ for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \
+ if ((bit_selector & (BIT)) != 0) \
+ toggle_mask ^= bit_selector; \
+ } \
+ SET_REG(REG, toggle_mask); \
+} while(0)
+
+#endif
diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h
new file mode 100644
index 0000000..df6bc08
--- /dev/null
+++ b/include/libopencm3/stm32/usart.h
@@ -0,0 +1,312 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_USART_H
+#define LIBOPENCM3_USART_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+#define USART1 USART1_BASE
+#define USART2 USART2_BASE
+#define USART3 USART3_BASE
+#define UART4 UART4_BASE
+#define UART5 UART5_BASE
+
+/* --- USART registers ----------------------------------------------------- */
+
+/* Status register (USARTx_SR) */
+#define USART_SR(usart_base) MMIO32(usart_base + 0x00)
+#define USART1_SR USART_SR(USART1_BASE)
+#define USART2_SR USART_SR(USART2_BASE)
+#define USART3_SR USART_SR(USART3_BASE)
+#define UART4_SR USART_SR(UART4_BASE)
+#define UART5_SR USART_SR(UART5_BASE)
+
+/* Data register (USARTx_DR) */
+#define USART_DR(usart_base) MMIO32(usart_base + 0x04)
+#define USART1_DR USART_DR(USART1_BASE)
+#define USART2_DR USART_DR(USART2_BASE)
+#define USART3_DR USART_DR(USART3_BASE)
+#define UART4_DR USART_DR(UART4_BASE)
+#define UART5_DR USART_DR(UART5_BASE)
+
+/* Baud rate register (USARTx_BRR) */
+#define USART_BRR(usart_base) MMIO32(usart_base + 0x08)
+#define USART1_BRR USART_BRR(USART1_BASE)
+#define USART2_BRR USART_BRR(USART2_BASE)
+#define USART3_BRR USART_BRR(USART3_BASE)
+#define UART4_BRR USART_BRR(UART4_BASE)
+#define UART5_BRR USART_BRR(UART5_BASE)
+
+/* Control register 1 (USARTx_CR1) */
+#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c)
+#define USART1_CR1 USART_CR1(USART1_BASE)
+#define USART2_CR1 USART_CR1(USART2_BASE)
+#define USART3_CR1 USART_CR1(USART3_BASE)
+#define UART4_CR1 USART_CR1(UART4_BASE)
+#define UART5_CR1 USART_CR1(UART5_BASE)
+
+/* Control register 2 (USARTx_CR2) */
+#define USART_CR2(usart_base) MMIO32(usart_base + 0x10)
+#define USART1_CR2 USART_CR2(USART1_BASE)
+#define USART2_CR2 USART_CR2(USART2_BASE)
+#define USART3_CR2 USART_CR2(USART3_BASE)
+#define UART4_CR2 USART_CR2(UART4_BASE)
+#define UART5_CR2 USART_CR2(UART5_BASE)
+
+/* Control register 3 (USARTx_CR3) */
+#define USART_CR3(usart_base) MMIO32(usart_base + 0x14)
+#define USART1_CR3 USART_CR3(USART1_BASE)
+#define USART2_CR3 USART_CR3(USART2_BASE)
+#define USART3_CR3 USART_CR3(USART3_BASE)
+#define UART4_CR3 USART_CR3(UART4_BASE)
+#define UART5_CR3 USART_CR3(UART5_BASE)
+
+/* Guard time and prescaler register (USARTx_GTPR) */
+#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18)
+#define USART1_GTPR USART_GTPR(USART1_BASE)
+#define USART2_GTPR USART_GTPR(USART2_BASE)
+#define USART3_GTPR USART_GTPR(USART3_BASE)
+#define UART4_GTPR USART_GTPR(UART4_BASE)
+#define UART5_GTPR USART_GTPR(UART5_BASE)
+
+/* --- USART_SR values ----------------------------------------------------- */
+
+/* CTS: CTS flag */
+/* Note: N/A on UART4/5 */
+#define USART_SR_CTS (1 << 9)
+
+/* LBD: LIN break detection flag */
+#define USART_SR_LBD (1 << 8)
+
+/* TXE: Transmit data buffer empty */
+#define USART_SR_TXE (1 << 7)
+
+/* TC: Transmission complete */
+#define USART_SR_TC (1 << 6)
+
+/* RXNE: Read data register not empty */
+#define USART_SR_RXNE (1 << 5)
+
+/* IDLE: Idle line detected */
+#define USART_SR_IDLE (1 << 4)
+
+/* ORE: Overrun error */
+#define USART_SR_ORE (1 << 3)
+
+/* NE: Noise error flag */
+#define USART_SR_NE (1 << 2)
+
+/* FE: Framing error */
+#define USART_SR_FE (1 << 1)
+
+/* PE: Parity error */
+#define USART_SR_PE (1 << 0)
+
+/* --- USART_DR values ----------------------------------------------------- */
+
+/* USART_DR[8:0]: DR[8:0]: Data value */
+#define USART_DR_MASK 0x1FF
+
+/* --- USART_BRR values ---------------------------------------------------- */
+
+/* DIV_Mantissa[11:0]: mantissa of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4)
+/* DIV_Fraction[3:0]: fraction of USARTDIV */
+#define USART_BRR_DIV_FRACTION_MASK 0xF
+
+/* --- USART_CR1 values ---------------------------------------------------- */
+
+/* UE: USART enable */
+#define USART_CR1_UE (1 << 13)
+
+/* M: Word length */
+#define USART_CR1_M (1 << 12)
+
+/* WAKE: Wakeup method */
+#define USART_CR1_WAKE (1 << 11)
+
+/* PCE: Parity control enable */
+#define USART_CR1_PCE (1 << 10)
+
+/* PS: Parity selection */
+#define USART_CR1_PS (1 << 9)
+
+/* PEIE: PE interrupt enable */
+#define USART_CR1_PEIE (1 << 8)
+
+/* TXEIE: TXE interrupt enable */
+#define USART_CR1_TXEIE (1 << 7)
+
+/* TCIE: Transmission complete interrupt enable */
+#define USART_CR1_TCIE (1 << 6)
+
+/* RXNEIE: RXNE interrupt enable */
+#define USART_CR1_RXNEIE (1 << 5)
+
+/* IDLEIE: IDLE interrupt enable */
+#define USART_CR1_IDLEIE (1 << 4)
+
+/* TE: Transmitter enable */
+#define USART_CR1_TE (1 << 3)
+
+/* RE: Receiver enable */
+#define USART_CR1_RE (1 << 2)
+
+/* RWU: Receiver wakeup */
+#define USART_CR1_RWU (1 << 1)
+
+/* SBK: Send break */
+#define USART_CR1_SBK (1 << 0)
+
+/* --- USART_CR2 values ---------------------------------------------------- */
+
+/* LINEN: LIN mode enable */
+#define USART_CR2_LINEN (1 << 14)
+
+/* STOP[13:12]: STOP bits */
+#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */
+#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */
+#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */
+#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */
+#define USART_CR2_STOPBITS_MASK (0x03 << 12)
+#define USART_CR2_STOPBITS_SHIFT 12
+
+/* CLKEN: Clock enable */
+#define USART_CR2_CLKEN (1 << 11)
+
+/* CPOL: Clock polarity */
+#define USART_CR2_CPOL (1 << 10)
+
+/* CPHA: Clock phase */
+#define USART_CR2_CPHA (1 << 9)
+
+/* LBCL: Last bit clock pulse */
+#define USART_CR2_LBCL (1 << 8)
+
+/* LBDIE: LIN break detection interrupt enable */
+#define USART_CR2_LBDIE (1 << 6)
+
+/* LBDL: LIN break detection length */
+#define USART_CR2_LBDL (1 << 5)
+
+/* ADD[3:0]: Addres of the usart node */
+#define USART_CR2_ADD_MASK 0xF
+
+/* --- USART_CR3 values ---------------------------------------------------- */
+
+/* CTSIE: CTS interrupt enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_CTSIE (1 << 10)
+
+/* CTSE: CTS enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_CTSE (1 << 9)
+
+/* RTSE: RTS enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_RTSE (1 << 8)
+
+/* DMAT: DMA enable transmitter */
+/* Note: N/A on UART5 */
+#define USART_CR3_DMAT (1 << 7)
+
+/* DMAR: DMA enable receiver */
+/* Note: N/A on UART5 */
+#define USART_CR3_DMAR (1 << 6)
+
+/* SCEN: Smartcard mode enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_SCEN (1 << 5)
+
+/* NACK: Smartcard NACK enable */
+/* Note: N/A on UART4 & UART5 */
+#define USART_CR3_NACK (1 << 4)
+
+/* HDSEL: Half-duplex selection */
+#define USART_CR3_HDSEL (1 << 3)
+
+/* IRLP: IrDA low-power */
+#define USART_CR3_IRLP (1 << 2)
+
+/* IREN: IrDA mode enable */
+#define USART_CR3_IREN (1 << 1)
+
+/* EIE: Error interrupt enable */
+#define USART_CR3_EIE (1 << 0)
+
+/* --- USART_GTPR values --------------------------------------------------- */
+
+/* GT[7:0]: Guard time value */
+/* Note: N/A on UART4 & UART5 */
+#define USART_GTPR_GT_MASK (0xFF << 8)
+
+/* PSC[7:0]: Prescaler value */
+/* Note: N/A on UART4/5 */
+#define USART_GTPR_PSC_MASK 0xFF
+
+/* TODO */ /* Note to Uwe: what needs to be done here? */
+
+/* --- Convenience defines ------------------------------------------------- */
+
+/* CR1_PCE / CR1_PS combined values */
+#define USART_PARITY_NONE 0x00
+#define USART_PARITY_ODD USART_CR1_PS
+#define USART_PARITY_EVEN (USART_CR1_PS | USART_CR1_PCE)
+#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)
+
+/* CR1_TE/CR1_RE combined values */
+#define USART_MODE_RX USART_CR1_RE
+#define USART_MODE_TX USART_CR1_TE
+#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)
+#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)
+
+#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
+#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */
+#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
+#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */
+
+/* CR3_CTSE/CR3_RTSE combined values */
+#define USART_FLOWCONTROL_NONE 0x00
+#define USART_FLOWCONTROL_RTS USART_CR3_RTSE
+#define USART_FLOWCONTROL_CTS USART_CR3_CTSE
+#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
+#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)
+
+/* --- Function prototypes ------------------------------------------------- */
+
+void usart_set_baudrate(u32 usart, u32 baud);
+void usart_set_databits(u32 usart, u32 bits);
+void usart_set_stopbits(u32 usart, u32 stopbits);
+void usart_set_parity(u32 usart, u32 parity);
+void usart_set_mode(u32 usart, u32 mode);
+void usart_set_flow_control(u32 usart, u32 flowcontrol);
+void usart_enable(u32 usart);
+void usart_disable(u32 usart);
+void usart_send(u32 usart, u16 data);
+u16 usart_recv(u32 usart);
+void usart_wait_send_ready(u32 usart);
+void usart_wait_recv_ready(u32 usart);
+void usart_send_blocking(u32 usart, u16 data);
+u16 usart_recv_blocking(u32 usart);
+
+#endif
diff --git a/include/libopencm3/stm32/usb.h b/include/libopencm3/stm32/usb.h
new file mode 100644
index 0000000..e35075d
--- /dev/null
+++ b/include/libopencm3/stm32/usb.h
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_USB_H
+#define LIBOPENCM3_USB_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/stm32/tools.h>
+
+/* --- USB base addresses -------------------------------------------------- */
+
+#define USB_PMA_BASE 0x40006000L /* USB packet buffer memory base addr. */
+
+/* --- USB general registers ----------------------------------------------- */
+
+/* USB Control register */
+#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40))
+/* USB Interrupt status register */
+#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44))
+/* USB Frame number register */
+#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48))
+/* USB Device address register */
+#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C))
+/* USB Buffer table address register */
+#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50))
+/* USB EP register */
+#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP))
+
+/* --- USB control register masks / bits ----------------------------------- */
+
+/* Interrupt mask bits, set to 1 to enable interrupt generation */
+#define USB_CNTR_CTRM 0x8000
+#define USB_CNTR_PMAOVRM 0x4000
+#define USB_CNTR_ERRM 0x2000
+#define USB_CNTR_WKUPM 0x1000
+#define USB_CNTR_SUSPM 0x0800
+#define USB_CNTR_RESETM 0x0400
+#define USB_CNTR_SOFM 0x0200
+#define USB_CNTR_ESOFM 0x0100
+
+/* Request/Force bits */
+#define USB_CNTR_RESUME 0x0010 /* Resume request */
+#define USB_CNTR_FSUSP 0x0008 /* Force suspend */
+#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */
+#define USB_CNTR_PWDN 0x0002 /* Power down */
+#define USB_CNTR_FRES 0x0001 /* Force reset */
+
+/* --- USB interrupt status register masks / bits -------------------------- */
+
+#define USB_ISTR_CTR 0x8000 /* Correct Transfer */
+#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */
+#define USB_ISTR_ERR 0x2000 /* Error */
+#define USB_ISTR_WKUP 0x1000 /* Wake up */
+#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */
+#define USB_ISTR_RESET 0x0400 /* USB RESET request */
+#define USB_ISTR_SOF 0x0200 /* Start Of Frame */
+#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */
+#define USB_ISTR_DIR 0x0010 /* Direction of transaction */
+#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */
+
+/* --- USB interrupt status register manipulators -------------------------- */
+
+/* Note: CTR is read only! */
+#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR)
+#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR)
+#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP)
+#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP)
+#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET)
+#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
+#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
+
+/* --- USB device addres register masks / bits ----------------------------- */
+
+#define USB_DADDR_ENABLE 0x0080
+#define USB_DADDR_ADDR 0x007F
+
+/* --- USB device addres register manipulators ----------------------------- */
+
+/* --- USB endpoint register offsets --------------------------------------- */
+
+#define USB_EP0 0
+#define USB_EP1 1
+#define USB_EP2 2
+#define USB_EP3 3
+#define USB_EP4 4
+#define USB_EP5 5
+#define USB_EP6 6
+#define USB_EP7 7
+
+/* --- USB endpoint register masks / bits ---------------------------------- */
+
+/* Masks and toggle bits */
+#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */
+#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */
+#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */
+
+#define USB_EP_SETUP 0x0800 /* Setup transaction completed */
+#define USB_EP_TYPE 0x0600 /* Endpoint type */
+#define USB_EP_KIND 0x0100 /* Endpoint kind.
+ * When set and type=bulk -> double buffer
+ * When set and type=control -> status out
+ */
+
+#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */
+#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */
+#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */
+
+#define USB_EP_ADDR 0x000F /* Endpoint Address */
+
+/* Masking all toggle bits */
+#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \
+ USB_EP_SETUP | \
+ USB_EP_TYPE | \
+ USB_EP_KIND | \
+ USB_EP_TX_CTR | \
+ USB_EP_ADDR)
+
+/* All non toggle bits plus EP_RX toggle bits */
+#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK)
+/* All non toggle bits plus EP_TX toggle bits */
+#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK)
+
+/* Endpoint status bits for USB_EP_RX_STAT bit field */
+#define USB_EP_RX_STAT_DISABLED 0x0000
+#define USB_EP_RX_STAT_STALL 0x1000
+#define USB_EP_RX_STAT_NAK 0x2000
+#define USB_EP_RX_STAT_VALID 0x3000
+
+/* Endpoint status bits for USB_EP_TX_STAT bit field */
+#define USB_EP_TX_STAT_DISABLED 0x0000
+#define USB_EP_TX_STAT_STALL 0x0010
+#define USB_EP_TX_STAT_NAK 0x0020
+#define USB_EP_TX_STAT_VALID 0x0030
+
+/* Endpoint type bits for USB_EP_TYPE bit field */
+#define USB_EP_TYPE_BULK 0x0000
+#define USB_EP_TYPE_CONTROL 0x0200
+#define USB_EP_TYPE_ISO 0x0400
+#define USB_EP_TYPE_INTERRUPT 0x0600
+
+/* --- USB endpoint register manipulators ---------------------------------- */
+
+/*
+ * Set USB endpoint tx/rx status.
+ *
+ * USB status field is changed using an awkward toggle mechanism, that
+ * is why we use some helper macros for that.
+ */
+#define USB_SET_EP_RX_STAT(EP, STAT) \
+ TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT)
+
+#define USB_SET_EP_TX_STAT(EP, STAT) \
+ TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT)
+
+/*
+ * Macros for clearing and setting USB endpoint register bits that do
+ * not use the toggle mechanism.
+ *
+ * Because the register contains some bits that use the toggle
+ * mechanism we need a helper macro here. Otherwise the code gets really messy.
+ */
+#define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \
+ CLR_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT)
+
+#define USB_CLR_EP_RX_CTR(EP) \
+ USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_RX_CTR)
+
+#define USB_CLR_EP_TX_CTR(EP) \
+ USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR)
+
+#define USB_SET_EP_TYPE(EP, TYPE) \
+ SET_REG(USB_EP_REG(EP), \
+ (GET_REG(USB_EP_REG(EP)) & \
+ (USB_EP_NTOGGLE_MSK & \
+ (~USB_EP_TYPE))) | TYPE)
+
+#define USB_SET_EP_KIND(EP) \
+ SET_REG(USB_EP_REG(EP), \
+ (GET_REG(USB_EP_REG(EP)) & \
+ (USB_EP_NTOGGLE_MSK & \
+ (~USB_EP_KIND))) | USB_EP_KIND)
+
+#define USB_CLR_EP_KIND(EP) \
+ SET_REG(USB_EP_REG(EP), \
+ (GET_REG(USB_EP_REG(EP)) & \
+ (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))))
+
+#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP)
+#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP)
+
+#define USB_SET_EP_ADDR(EP, ADDR) \
+ SET_REG(USB_EP_REG(EP), \
+ ((GET_REG(USB_EP_REG(EP)) & \
+ (USB_EP_NTOGGLE_MSK & \
+ (~USB_EP_ADDR))) | ADDR))
+
+/* Macros for clearing DTOG bits */
+#define USB_CLR_EP_TX_DTOG(EP) \
+ SET_REG(USB_EP_REG(EP), \
+ GET_REG(USB_EP_REG(EP)) & \
+ (USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG))
+
+#define USB_CLR_EP_RX_DTOG(EP) \
+ SET_REG(USB_EP_REG(EP), \
+ GET_REG(USB_EP_REG(EP)) & \
+ (USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG))
+
+/* --- USB BTABLE registers ------------------------------------------------ */
+
+#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG)
+
+#define USB_EP_TX_ADDR(EP) \
+ ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2))
+
+#define USB_EP_TX_COUNT(EP) \
+ ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2))
+
+#define USB_EP_RX_ADDR(EP) \
+ ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2))
+
+#define USB_EP_RX_COUNT(EP) \
+ ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2))
+
+/* --- USB BTABLE manipulators --------------------------------------------- */
+
+#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP))
+#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP))
+#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP))
+#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP))
+#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR)
+#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT)
+#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR)
+#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)
+
+#define USB_GET_EP_TX_BUFF(EP) \
+ (USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2))
+
+#define USB_GET_EP_RX_BUFF(EP) \
+ (USB_PMA_BASE + (u8 *)(USB_GET_EP_RX_ADDR(EP) * 2))
+
+#endif
diff --git a/include/libopencm3/stm32/usb_desc.h b/include/libopencm3/stm32/usb_desc.h
new file mode 100644
index 0000000..da99bb0
--- /dev/null
+++ b/include/libopencm3/stm32/usb_desc.h
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_USB_DESC
+#define LIBOPENCM3_USB_DESC
+
+/* Descriptor types */
+#define USB_DT_DEVICE 0x01
+#define USB_DT_CONF 0x02
+#define USB_DT_STRING 0x03
+#define USB_DT_INTERFACE 0x04
+#define USB_DT_ENDPOINT 0x05
+
+struct usb_desc_head {
+ u8 length; /* Descriptor size 0x012 */
+ u8 type; /* Descriptor type ID */
+};
+
+struct usb_device_desc {
+ struct usb_desc_head h; /* Size 0x12, ID 0x01 */
+ u16 bcd_usb; /* USB Version */
+ u8 class; /* Device class */
+ u8 sub_class; /* Subclass code */
+ u8 protocol; /* Protocol code */
+ u8 max_psize; /* Maximum packet size -> 64bytes */
+ u16 vendor; /* Vendor number */
+ u16 product; /* Device number */
+ u16 bcd_dev; /* Device version */
+ u8 man_desc; /* Index of manufacturer string desc */
+ u8 prod_desc; /* Index of product string desc */
+ u8 sn_desc; /* Index of serial number string desc */
+ u8 num_conf; /* Number of possible configurations */
+};
+
+struct usb_conf_desc_header {
+ struct usb_desc_head h; /* Size 0x09, Id 0x02 */
+ u16 tot_leng; /* Total length of data */
+ u8 num_int; /* Number of interfaces */
+ u8 conf_val; /* Configuration selector */
+ u8 conf_desc; /* Index of conf string desc */
+ u8 attr; /* Attribute bitmap:
+ * 7 : Bus powered
+ * 6 : Self powered
+ * 5 : Remote wakeup
+ * 4..0 : Reserved -> 0000
+ */
+ u8 max_power; /* Maximum power consumption in 2mA steps */
+};
+
+struct usb_int_desc_header {
+ struct usb_desc_head h; /* Size 0x09, Id 0x04 */
+ u8 iface_num; /* Interface id number */
+ u8 alt_setting; /* Alternative setting selector */
+ u8 num_endp; /* Endpoints used */
+ u8 class; /* Interface class */
+ u8 sub_class; /* Subclass code */
+ u8 protocol; /* Protocol code */
+ u8 iface_desc; /* Index of interface string desc */
+};
+
+struct usb_ep_desc {
+ struct usb_desc_head h; /* Size 0x07, Id 0x05 */
+ u8 ep_addr; /* Endpoint address:
+ 0..3 : Endpoint Number
+ 4..6 : Reserved -> 0
+ 7 : Direction 0=out 1=in */
+ u8 ep_attr; /* Endpoint attributes */
+ u16 max_psize; /* Maximum packet size -> 64bytes */
+ u8 interval; /* Interval for polling endpoint
+ data. Ignored for bulk & control
+ endpoints. */
+};
+
+struct usb_conf_desc {
+ struct usb_conf_desc_header cdh;
+ struct usb_int_desc_header idh;
+ struct usb_ep_desc ep[];
+};
+
+struct usb_string_desc {
+ struct usb_desc_head h; /* Size > 0x02, Id 0x03 */
+ u16 string[]; /* String UTF16 encoded */
+};
+
+#endif
diff --git a/include/libopencm3/stm32/wwdg.h b/include/libopencm3/stm32/wwdg.h
new file mode 100644
index 0000000..552d02e
--- /dev/null
+++ b/include/libopencm3/stm32/wwdg.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_WWDG_H
+#define LIBOPENCM3_WWDG_H
+
+#include <libopencm3/stm32/memorymap.h>
+#include <libopencm3/cm3/common.h>
+
+/* --- WWDG registers ------------------------------------------------------ */
+
+/* Control register (WWDG_CR) */
+#define WWDG_CR MMIO32(WWDG_BASE + 0x00)
+
+/* Configuration register (WWDG_CFR) */
+#define WWDG_CFR MMIO32(WWDG_BASE + 0x04)
+
+/* Status register (WWDG_SR) */
+#define WWDG_SR MMIO32(WWDG_BASE + 0x08)
+
+/* --- WWDG_CR values ------------------------------------------------------ */
+
+/* WDGA: Activation bit */
+#define WWDG_CR_WDGA (1 << 7)
+
+/* T[6:0]: 7-bit counter (MSB to LSB) */
+#define WWDG_CR_T_LSB 0
+#define WWDG_CR_T0 (1 << 0)
+#define WWDG_CR_T1 (1 << 1)
+#define WWDG_CR_T2 (1 << 2)
+#define WWDG_CR_T3 (1 << 3)
+#define WWDG_CR_T4 (1 << 4)
+#define WWDG_CR_T5 (1 << 5)
+#define WWDG_CR_T6 (1 << 6)
+
+/* --- WWDG_CFR values ----------------------------------------------------- */
+
+/* EWI: Early wakeup interrupt */
+#define WWDG_CFR_EWI (1 << 9)
+
+/* WDGTB[8:7]: Timer base */
+#define WWDG_CFR_WDGTB_LSB 7
+#define WWDG_CFR_WDGTB_CK_DIV1 0x0
+#define WWDG_CFR_WDGTB_CK_DIV2 0x1
+#define WWDG_CFR_WDGTB_CK_DIV4 0x2
+#define WWDG_CFR_WDGTB_CK_DIV8 0x3
+
+/* W[6:0]: 7-bit window value */
+#define WWDG_CFG_W_LSB 0
+
+/* --- WWDG_SR values ------------------------------------------------------ */
+
+/* EWIF: Early wakeup interrupt flag */
+#define WWDG_SR_EWIF (1 << 0)
+
+/* --- WWDG funtion prototypes---------------------------------------------- */
+
+#endif