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authorFergus Noble2011-09-12 18:09:10 -0700
committerStephen Caudle2011-10-12 22:13:01 -0400
commit18648708c887e24a1e30a37b133aad15b284a21d (patch)
treea58a2ae3055f3eec82e4e737c9282a0c2b218edf /include/libopencm3/stm32/memorymap.h
parent5ba3e77246fece4883381b6db00974fd1a0c2c34 (diff)
Moving renaming stm32 header files for f1 series.
Diffstat (limited to 'include/libopencm3/stm32/memorymap.h')
-rw-r--r--include/libopencm3/stm32/memorymap.h113
1 files changed, 0 insertions, 113 deletions
diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h
deleted file mode 100644
index e3c57c8..0000000
--- a/include/libopencm3/stm32/memorymap.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef LIBOPENCM3_MEMORYMAP_H
-#define LIBOPENCM3_MEMORYMAP_H
-
-#include <libopencm3/cm3/memorymap.h>
-
-/* --- STM32 specific peripheral definitions ------------------------------- */
-
-/* Memory map for all busses */
-#define PERIPH_BASE 0x40000000
-#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
-#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
-#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000)
-
-/* Register boundary addresses */
-
-/* APB1 */
-#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
-#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
-#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
-#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
-#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
-#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
-#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)
-#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)
-#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
-/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
-#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
-#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
-#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
-/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
-#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800)
-#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00)
-/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
-#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
-#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
-#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
-#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
-#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
-#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
-#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
-#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
-#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
-#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
-/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */
-#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00)
-#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
-#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
-/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */
-
-/* APB2 */
-#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000)
-#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
-#define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800)
-#define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00)
-#define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000)
-#define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400)
-#define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800)
-#define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00)
-#define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000)
-#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)
-#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800)
-#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00)
-#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
-#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)
-#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
-#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00)
-/* PERIPH_BASE_APB2 + 0x4000 (0x4001 4000 - 0x4001 4FFF): Reserved */
-#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00)
-#define TIM10_BASE (PERIPH_BASE_APB2 + 0x5000)
-#define TIM11_BASE (PERIPH_BASE_APB2 + 0x5400)
-/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */
-
-/* AHB */
-#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000)
-/* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */
-#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000)
-#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400)
-/* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */
-#define RCC_BASE (PERIPH_BASE_AHB + 0x09000)
-/* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */
-#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000)
-#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000)
-/* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */
-#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)
-/* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */
-#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000)
-
-/* PPIB */
-#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
-
-/* FSMC */
-#define FSMC_BASE (PERIPH_BASE + 0x60000000)
-
-#endif