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authorStephen Caudle2011-11-02 22:37:17 -0400
committerStephen Caudle2011-11-02 22:37:47 -0400
commit30b5c89726d4e30802d356bdf00acd8fab243af8 (patch)
treef1e7674fed158c69cb6dcf5d14dd333e6cf4eb39 /include/libopencm3/stm32/f4
parent44bf853e6e71071abfc7d115875a51a046f6d508 (diff)
Add USART6 definitions to STM32F3 & STM32F4
Diffstat (limited to 'include/libopencm3/stm32/f4')
-rw-r--r--include/libopencm3/stm32/f4/usart.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/include/libopencm3/stm32/f4/usart.h b/include/libopencm3/stm32/f4/usart.h
index d59f906..7543fd3 100644
--- a/include/libopencm3/stm32/f4/usart.h
+++ b/include/libopencm3/stm32/f4/usart.h
@@ -2,6 +2,7 @@
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
+ * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,6 +23,33 @@
#include <libopencm3/stm32/usart.h>
+/* --- Convenience macros -------------------------------------------------- */
+
+#define USART6 USART6_BASE
+
+/* --- USART registers ----------------------------------------------------- */
+
+/* Status register (USARTx_SR) */
+#define USART6_SR USART_SR(USART6_BASE)
+
+/* Data register (USARTx_DR) */
+#define USART6_DR USART_DR(USART6_BASE)
+
+/* Baud rate register (USARTx_BRR) */
+#define USART6_BRR USART_BRR(USART6_BASE)
+
+/* Control register 1 (USARTx_CR1) */
+#define USART6_CR1 USART_CR1(USART6_BASE)
+
+/* Control register 2 (USARTx_CR2) */
+#define USART6_CR2 USART_CR2(USART6_BASE)
+
+/* Control register 3 (USARTx_CR3) */
+#define USART6_CR3 USART_CR3(USART6_BASE)
+
+/* Guard time and prescaler register (USARTx_GTPR) */
+#define USART6_GTPR USART_GTPR(USART6_BASE)
+
/* --- USART_CR1 values ---------------------------------------------------- */
/* OVER8: Oversampling mode */