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authorStephen Caudle2011-10-31 11:11:03 -0400
committerStephen Caudle2011-10-31 11:11:03 -0400
commit1fea1df39abde97d1e84f5b99f9793701b1691b7 (patch)
treeec0122ab2b80cea63969cbfb12d19eee15741a5e /include/libopencm3/stm32/f4/rcc.h
parent6da485f06dedb5a0401bdec2ce5ea1c9752f5397 (diff)
Fix more STM32 whitespace issues
Diffstat (limited to 'include/libopencm3/stm32/f4/rcc.h')
-rw-r--r--include/libopencm3/stm32/f4/rcc.h16
1 files changed, 8 insertions, 8 deletions
diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
index debeeda..a01aaad 100644
--- a/include/libopencm3/stm32/f4/rcc.h
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -133,14 +133,14 @@
/* HPRE: AHB high-speed prescaler */
#define RCC_CFGR_HPRE_SHIFT 4
#define RCC_CFGR_HPRE_DIV_NONE 0x0
-#define RCC_CFGR_HPRE_DIV_2 (0x8+0)
-#define RCC_CFGR_HPRE_DIV_4 (0x8+1)
-#define RCC_CFGR_HPRE_DIV_8 (0x8+2)
-#define RCC_CFGR_HPRE_DIV_16 (0x8+3)
-#define RCC_CFGR_HPRE_DIV_64 (0x8+4)
-#define RCC_CFGR_HPRE_DIV_128 (0x8+5)
-#define RCC_CFGR_HPRE_DIV_256 (0x8+6)
-#define RCC_CFGR_HPRE_DIV_512 (0x8+7)
+#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0)
+#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1)
+#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2)
+#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3)
+#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4)
+#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5)
+#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6)
+#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7)
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SHIFT 2