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authorPiotr Esden-Tempski2011-01-31 16:30:12 -0800
committerPiotr Esden-Tempski2011-01-31 16:30:12 -0800
commit92edc113f9825f333ea66e41e8fcdbeb45da9cd6 (patch)
tree29fdc2f094b5ce5f0ce6f2cd05b1f758911612e9
parente85c55a9a70f8f357aceba4cbacd7762ca773d7b (diff)
Added timer reset function.
-rw-r--r--examples/stm32/stm32-h103/pwm_6step/pwm_6step.c3
-rw-r--r--include/libopencm3/stm32/timer.h1
-rw-r--r--lib/stm32/timer.c67
3 files changed, 71 insertions, 0 deletions
diff --git a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
index cf53ac6..505b3c8 100644
--- a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
+++ b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
@@ -121,6 +121,9 @@ void tim_setup(void)
/* Enable TIM1 commutation interrupt. */
nvic_enable_irq(NVIC_TIM1_TRG_COM_IRQ);
+ /* Reset TIM1 peripheral */
+ timer_reset(TIM1);
+
/* Clock division. */
timer_set_clock_division(TIM1, TIM_CR1_CKD_CK_INT);
diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index c3bc195..b11802e 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -852,6 +852,7 @@ enum tim_oc_mode {
};
/* --- TIM functions ------------------------------------------------------- */
+void timer_reset(u32 timer_peripheral);
void timer_enable_irq(u32 timer_peripheral, u32 irq);
void timer_disable_irq(u32 timer_peripheral, u32 irq);
void timer_clear_flag(u32 timer_peripheral, u32 flag);
diff --git a/lib/stm32/timer.c b/lib/stm32/timer.c
index 8c612ed..9a6534d 100644
--- a/lib/stm32/timer.c
+++ b/lib/stm32/timer.c
@@ -26,6 +26,73 @@
*/
#include <libopencm3/stm32/timer.h>
+#include <libopencm3/stm32/rcc.h>
+
+void timer_reset(u32 timer_peripheral)
+{
+ switch (timer_peripheral)
+ {
+ case TIM1:
+ rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST);
+ rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST);
+ break;
+ case TIM2:
+ rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST);
+ rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST);
+ break;
+ case TIM3:
+ rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST);
+ rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST);
+ break;
+ case TIM4:
+ rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST);
+ rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST);
+ break;
+ case TIM5:
+ rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST);
+ rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST);
+ break;
+ case TIM6:
+ rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST);
+ rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST);
+ break;
+ case TIM7:
+ rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST);
+ rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST);
+ break;
+ case TIM8:
+ rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST);
+ rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST);
+ break;
+/* These timers are not supported in libopencm3 yet */
+/*
+ case TIM9:
+ rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST);
+ rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST);
+ break;
+ case TIM10:
+ rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST);
+ rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST);
+ break;
+ case TIM11:
+ rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST);
+ rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST);
+ break;
+ case TIM12:
+ rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST);
+ rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST);
+ break;
+ case TIM13:
+ rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST);
+ rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST);
+ break;
+ case TIM14:
+ rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST);
+ rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST);
+ break;
+*/
+ }
+}
void timer_enable_irq(u32 timer_peripheral, u32 irq)
{