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authorPiotr Esden-Tempski2011-01-28 16:04:36 -0800
committerPiotr Esden-Tempski2011-01-28 16:04:36 -0800
commit59293a9640cc1daf8ba7a04aece0de8c394521e8 (patch)
tree9559da33f1d0ba298d0054d516ba4d20ba6c7261
parenta1bd228c87d1b73f6cfecf000eec0a8765a11b01 (diff)
Added break and dead time convenience functions. Adapted 6step example to reflect that.
-rw-r--r--examples/stm32/stm32-h103/pwm_6step/pwm_6step.c11
-rw-r--r--include/libopencm3/stm32/timer.h14
-rw-r--r--lib/stm32/timer.c112
3 files changed, 136 insertions, 1 deletions
diff --git a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
index d769e3a..f93378d 100644
--- a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
+++ b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
@@ -94,6 +94,15 @@ void tim_setup(void)
/* Period (32kHz) */
timer_set_period(TIM1, 72000000 / 32000);
+ /* Configure break and deadtime */
+ timer_set_deadtime(TIM1, 0);
+ timer_set_enabled_off_state_in_idle_mode(TIM1);
+ timer_set_enabled_off_state_in_run_mode(TIM1);
+ timer_disable_break(TIM1);
+ timer_set_break_polarity_high(TIM1);
+ timer_disable_break_automatic_output(TIM1);
+ timer_set_break_lock(TIM1, TIM_BDTR_LOCK_OFF);
+
/* -- OC1 and OC1N configuration -- */
/* Disable outputs. */
@@ -180,7 +189,7 @@ void tim_setup(void)
timer_enable_preload(TIM1);
/* Enable outputs in the break subsystem */
- TIM1_BDTR |= TIM_BDTR_MOE;
+ timer_enable_break_main_output(TIM1);
/* Counter enable */
timer_enable_counter(TIM1);
diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index 1cd5d0e..befe156 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -894,5 +894,19 @@ void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value);
+void timer_enable_break_main_output(u32 timer_peripheral);
+void timer_disable_break_main_output(u32 timer_peripheral);
+void timer_enable_break_automatic_output(u32 timer_peripheral);
+void timer_disable_break_automatic_output(u32 timer_peripheral);
+void timer_set_break_polarity_high(u32 timer_peripheral);
+void timer_set_break_polarity_low(u32 timer_peripheral);
+void timer_enable_break(u32 timer_peripheral);
+void timer_disable_break(u32 timer_peripheral);
+void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral);
+void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral);
+void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral);
+void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral);
+void timer_set_break_lock(u32 timer_peripheral, u32 lock);
+void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
#endif
diff --git a/lib/stm32/timer.c b/lib/stm32/timer.c
index 25001a1..125bdff 100644
--- a/lib/stm32/timer.c
+++ b/lib/stm32/timer.c
@@ -717,3 +717,115 @@ void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value)
break;
}
}
+
+void timer_enable_break_main_output(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) |= TIM_BDTR_MOE;
+ }
+}
+
+void timer_disable_break_main_output(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_MOE;
+ }
+}
+
+void timer_enable_break_automatic_output(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) |= TIM_BDTR_AOE;
+ }
+}
+
+void timer_disable_break_automatic_output(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_AOE;
+ }
+}
+
+void timer_set_break_polarity_high(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKP;
+ }
+}
+
+void timer_set_break_polarity_low(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKP;
+ }
+}
+
+void timer_enable_break(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKE;
+ }
+}
+
+void timer_disable_break(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKE;
+ }
+}
+
+void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSR;
+ }
+}
+
+void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSR;
+ }
+}
+
+void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSI;
+ }
+}
+
+void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSI;
+ }
+}
+
+void timer_set_break_lock(u32 timer_peripheral, u32 lock)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) |= lock;
+ }
+}
+
+void timer_set_deadtime(u32 timer_peripheral, u32 deadtime)
+{
+ if ((timer_peripheral == TIM1) ||
+ (timer_peripheral == TIM8)) {
+ TIM_BDTR(timer_peripheral) |= deadtime;
+ }
+}