aboutsummaryrefslogtreecommitdiff
path: root/src/cortexm.c
diff options
context:
space:
mode:
authorGareth McMullin2015-03-15 16:02:09 -0700
committerGareth McMullin2015-03-15 16:02:09 -0700
commit2bf54f9a72bd9ee57e668f09075b65486e418216 (patch)
tree6bf9acfd7f7b44637f12ca79ed23a691bc580a6e /src/cortexm.c
parentee3af96a736139b71678a0e590865f9ffafc2f35 (diff)
Replace adiv5_ap_mem* functions with inline wrappers to target mem*.
Diffstat (limited to 'src/cortexm.c')
-rw-r--r--src/cortexm.c100
1 files changed, 47 insertions, 53 deletions
diff --git a/src/cortexm.c b/src/cortexm.c
index fcc6a9d..4bfb4d9 100644
--- a/src/cortexm.c
+++ b/src/cortexm.c
@@ -228,16 +228,16 @@ cortexm_probe(struct target_s *target)
target_add_commands(target, cortexm_cmd_list, cortexm_driver_str);
/* Probe for FP extension */
- ADIv5_AP_t *ap = adiv5_target_ap(target);
- uint32_t cpacr = adiv5_ap_mem_read(ap, CORTEXM_CPACR);
+ uint32_t cpacr = target_mem_read32(target, CORTEXM_CPACR);
cpacr |= 0x00F00000; /* CP10 = 0b11, CP11 = 0b11 */
- adiv5_ap_mem_write(ap, CORTEXM_CPACR, cpacr);
- if (adiv5_ap_mem_read(ap, CORTEXM_CPACR) == cpacr) {
+ target_mem_write32(target, CORTEXM_CPACR, cpacr);
+ if (target_mem_read32(target, CORTEXM_CPACR) == cpacr) {
target->target_options |= TOPT_FLAVOUR_V7MF;
target->regs_size += sizeof(regnum_cortex_mf);
target->tdesc = tdesc_cortex_mf;
}
+ ADIv5_AP_t *ap = adiv5_target_ap(target);
struct cortexm_priv *priv = calloc(1, sizeof(*priv));
ap->priv = priv;
ap->priv_free = free;
@@ -284,35 +284,35 @@ bool cortexm_attach(struct target_s *target)
return false;
/* Request halt on reset */
- adiv5_ap_mem_write(ap, CORTEXM_DEMCR, priv->demcr);
+ target_mem_write32(target, CORTEXM_DEMCR, priv->demcr);
/* Reset DFSR flags */
- adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL);
+ target_mem_write32(target, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL);
/* size the break/watchpoint units */
priv->hw_breakpoint_max = CORTEXM_MAX_BREAKPOINTS;
- r = adiv5_ap_mem_read(ap, CORTEXM_FPB_CTRL);
+ r = target_mem_read32(target, CORTEXM_FPB_CTRL);
if (((r >> 4) & 0xf) < priv->hw_breakpoint_max) /* only look at NUM_COMP1 */
priv->hw_breakpoint_max = (r >> 4) & 0xf;
priv->hw_watchpoint_max = CORTEXM_MAX_WATCHPOINTS;
- r = adiv5_ap_mem_read(ap, CORTEXM_DWT_CTRL);
+ r = target_mem_read32(target, CORTEXM_DWT_CTRL);
if ((r >> 28) > priv->hw_watchpoint_max)
priv->hw_watchpoint_max = r >> 28;
/* Clear any stale breakpoints */
for(i = 0; i < priv->hw_breakpoint_max; i++) {
- adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0);
+ target_mem_write32(target, CORTEXM_FPB_COMP(i), 0);
priv->hw_breakpoint[i] = 0;
}
/* Clear any stale watchpoints */
for(i = 0; i < priv->hw_watchpoint_max; i++) {
- adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0);
+ target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0);
priv->hw_watchpoint[i].type = 0;
}
/* Flash Patch Control Register: set ENABLE */
- adiv5_ap_mem_write(ap, CORTEXM_FPB_CTRL,
+ target_mem_write32(target, CORTEXM_FPB_CTRL,
CORTEXM_FPB_CTRL_KEY | CORTEXM_FPB_CTRL_ENABLE);
target->set_hw_bp = cortexm_set_hw_bp;
target->clear_hw_bp = cortexm_clear_hw_bp;
@@ -336,14 +336,14 @@ void cortexm_detach(struct target_s *target)
/* Clear any stale breakpoints */
for(i = 0; i < priv->hw_breakpoint_max; i++)
- adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0);
+ target_mem_write32(target, CORTEXM_FPB_COMP(i), 0);
/* Clear any stale watchpoints */
for(i = 0; i < priv->hw_watchpoint_max; i++)
- adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0);
+ target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0);
/* Disable debug */
- adiv5_ap_mem_write(ap, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY);
+ target_mem_write32(target, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY);
}
static int
@@ -422,10 +422,8 @@ cortexm_regs_write(struct target_s *target, const void *data)
static uint32_t
cortexm_pc_read(struct target_s *target)
{
- ADIv5_AP_t *ap = adiv5_target_ap(target);
-
- adiv5_ap_mem_write(ap, CORTEXM_DCRSR, 0x0F);
- return adiv5_ap_mem_read(ap, CORTEXM_DCRDR);
+ target_mem_write32(target, CORTEXM_DCRSR, 0x0F);
+ return target_mem_read32(target, CORTEXM_DCRDR);
return 0;
}
@@ -433,10 +431,8 @@ cortexm_pc_read(struct target_s *target)
static int
cortexm_pc_write(struct target_s *target, const uint32_t val)
{
- ADIv5_AP_t *ap = adiv5_target_ap(target);
-
- adiv5_ap_mem_write(ap, CORTEXM_DCRDR, val);
- adiv5_ap_mem_write(ap, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | 0x0F);
+ target_mem_write32(target, CORTEXM_DCRDR, val);
+ target_mem_write32(target, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | 0x0F);
return 0;
}
@@ -446,26 +442,24 @@ cortexm_pc_write(struct target_s *target, const uint32_t val)
static void
cortexm_reset(struct target_s *target)
{
- ADIv5_AP_t *ap = adiv5_target_ap(target);
-
jtagtap_srst(true);
jtagtap_srst(false);
/* Read DHCSR here to clear S_RESET_ST bit before reset */
- adiv5_ap_mem_read(ap, CORTEXM_DHCSR);
+ target_mem_read32(target, CORTEXM_DHCSR);
/* Request system reset from NVIC: SRST doesn't work correctly */
/* This could be VECTRESET: 0x05FA0001 (reset only core)
* or SYSRESETREQ: 0x05FA0004 (system reset)
*/
- adiv5_ap_mem_write(ap, CORTEXM_AIRCR,
- CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
+ target_mem_write32(target, CORTEXM_AIRCR,
+ CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
/* Poll for release from reset */
- while(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST);
+ while (target_mem_read32(target, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST);
/* Reset DFSR flags */
- adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL);
+ target_mem_write32(target, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL);
}
static void
@@ -474,8 +468,9 @@ cortexm_halt_request(struct target_s *target)
ADIv5_AP_t *ap = adiv5_target_ap(target);
ap->dp->allow_timeout = false;
- adiv5_ap_mem_write(ap, CORTEXM_DHCSR,
- CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT | CORTEXM_DHCSR_C_DEBUGEN);
+ target_mem_write32(target, CORTEXM_DHCSR,
+ CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT |
+ CORTEXM_DHCSR_C_DEBUGEN);
}
static int
@@ -483,14 +478,14 @@ cortexm_halt_wait(struct target_s *target)
{
ADIv5_AP_t *ap = adiv5_target_ap(target);
struct cortexm_priv *priv = ap->priv;
- if (!(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_HALT))
+ if (!(target_mem_read32(target, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_HALT))
return 0;
ap->dp->allow_timeout = false;
/* We've halted. Let's find out why. */
- uint32_t dfsr = adiv5_ap_mem_read(ap, CORTEXM_DFSR);
- adiv5_ap_mem_write(ap, CORTEXM_DFSR, dfsr); /* write back to reset */
+ uint32_t dfsr = target_mem_read32(target, CORTEXM_DFSR);
+ target_mem_write32(target, CORTEXM_DFSR, dfsr); /* write back to reset */
if ((dfsr & CORTEXM_DFSR_VCATCH) && cortexm_fault_unwind(target))
return SIGSEGV;
@@ -502,7 +497,7 @@ cortexm_halt_wait(struct target_s *target)
* call. */
uint32_t pc = cortexm_pc_read(target);
uint16_t bkpt_instr;
- target_mem_read(target, &bkpt_instr, pc, 2);
+ bkpt_instr = target_mem_read16(target, pc);
if (bkpt_instr == 0xBEAB) {
int n = cortexm_hostio_request(target);
if (n > 0) {
@@ -535,27 +530,26 @@ void cortexm_halt_resume(struct target_s *target, bool step)
/* Disable interrupts while single stepping... */
if(step != priv->stepping) {
- adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr | CORTEXM_DHCSR_C_HALT);
+ target_mem_write32(target, CORTEXM_DHCSR, dhcsr | CORTEXM_DHCSR_C_HALT);
priv->stepping = step;
}
if (priv->on_bkpt) {
uint32_t pc = cortexm_pc_read(target);
- if ((adiv5_ap_mem_read_halfword(ap, pc) & 0xFF00) == 0xBE00)
+ if ((target_mem_read16(target, pc) & 0xFF00) == 0xBE00)
cortexm_pc_write(target, pc + 2);
}
- adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr);
+ target_mem_write32(target, CORTEXM_DHCSR, dhcsr);
ap->dp->allow_timeout = true;
}
static int cortexm_fault_unwind(struct target_s *target)
{
- ADIv5_AP_t *ap = adiv5_target_ap(target);
- uint32_t hfsr = adiv5_ap_mem_read(ap, CORTEXM_HFSR);
- uint32_t cfsr = adiv5_ap_mem_read(ap, CORTEXM_CFSR);
- adiv5_ap_mem_write(ap, CORTEXM_HFSR, hfsr);/* write back to reset */
- adiv5_ap_mem_write(ap, CORTEXM_CFSR, cfsr);/* write back to reset */
+ uint32_t hfsr = target_mem_read32(target, CORTEXM_HFSR);
+ uint32_t cfsr = target_mem_read32(target, CORTEXM_CFSR);
+ target_mem_write32(target, CORTEXM_HFSR, hfsr);/* write back to reset */
+ target_mem_write32(target, CORTEXM_CFSR, cfsr);/* write back to reset */
/* We check for FORCED in the HardFault Status Register or
* for a configurable fault to avoid catching core resets */
if((hfsr & CORTEXM_HFSR_FORCED) || cfsr) {
@@ -598,7 +592,7 @@ static int cortexm_fault_unwind(struct target_s *target)
/* Reset exception state to allow resuming from restored
* state.
*/
- adiv5_ap_mem_write(ap, CORTEXM_AIRCR,
+ target_mem_write32(target, CORTEXM_AIRCR,
CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_VECTCLRACTIVE);
/* Write pre-exception registers back to core */
@@ -630,7 +624,7 @@ cortexm_set_hw_bp(struct target_s *target, uint32_t addr)
priv->hw_breakpoint[i] = addr | 1;
- adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), val);
+ target_mem_write32(target, CORTEXM_FPB_COMP(i), val);
return 0;
}
@@ -649,7 +643,7 @@ cortexm_clear_hw_bp(struct target_s *target, uint32_t addr)
priv->hw_breakpoint[i] = 0;
- adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0);
+ target_mem_write32(target, CORTEXM_FPB_COMP(i), 0);
return 0;
}
@@ -683,7 +677,7 @@ cortexm_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t
for(i = 0; i < priv->hw_watchpoint_max; i++)
if((priv->hw_watchpoint[i].type == 0) &&
- ((adiv5_ap_mem_read(ap, CORTEXM_DWT_FUNC(i)) & 0xF) == 0))
+ ((target_mem_read32(target, CORTEXM_DWT_FUNC(i)) & 0xF) == 0))
break;
if(i == priv->hw_watchpoint_max) return -2;
@@ -692,9 +686,9 @@ cortexm_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t
priv->hw_watchpoint[i].addr = addr;
priv->hw_watchpoint[i].size = len;
- adiv5_ap_mem_write(ap, CORTEXM_DWT_COMP(i), addr);
- adiv5_ap_mem_write(ap, CORTEXM_DWT_MASK(i), len);
- adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), type |
+ target_mem_write32(target, CORTEXM_DWT_COMP(i), addr);
+ target_mem_write32(target, CORTEXM_DWT_MASK(i), len);
+ target_mem_write32(target, CORTEXM_DWT_FUNC(i), type |
((target->target_options & TOPT_FLAVOUR_V6M) ? 0: CORTEXM_DWT_FUNC_DATAVSIZE_WORD));
return 0;
@@ -732,7 +726,7 @@ cortexm_clear_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_
priv->hw_watchpoint[i].type = 0;
- adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0);
+ target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0);
return 0;
}
@@ -747,7 +741,7 @@ cortexm_check_hw_wp(struct target_s *target, uint32_t *addr)
for(i = 0; i < priv->hw_watchpoint_max; i++)
/* if SET and MATCHED then break */
if(priv->hw_watchpoint[i].type &&
- (adiv5_ap_mem_read(ap, CORTEXM_DWT_FUNC(i)) &
+ (target_mem_read32(target, CORTEXM_DWT_FUNC(i)) &
CORTEXM_DWT_FUNC_MATCHED))
break;
@@ -781,7 +775,7 @@ static bool cortexm_vector_catch(target *t, int argc, char *argv[])
else
priv->demcr &= ~tmp;
- adiv5_ap_mem_write(ap, CORTEXM_DEMCR, priv->demcr);
+ target_mem_write32(t, CORTEXM_DEMCR, priv->demcr);
}
gdb_out("Catching vectors: ");