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authorGareth McMullin2013-01-11 10:02:34 -0800
committerGareth McMullin2013-01-11 10:02:34 -0800
commit2a46994b42f3fab67a8969ae0440c764e6b25b6e (patch)
treeb8e3b054c00c0180b4afb7e0467e7c8c074d48d8 /src/cortexm.c
parentad9c76e97f1e20d3a564d296d156e67a80fbd6dc (diff)
Fixed magic numbers for CSW access.
Diffstat (limited to 'src/cortexm.c')
-rw-r--r--src/cortexm.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cortexm.c b/src/cortexm.c
index 4430e6e..9ec96d6 100644
--- a/src/cortexm.c
+++ b/src/cortexm.c
@@ -459,7 +459,8 @@ cortexm_regs_read(struct target_s *target, void *data)
unsigned i;
/* FIXME: Describe what's really going on here */
- adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000052);
+ adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+ ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
/* Map the banked data registers (0x10-0x1c) to the
* debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */
@@ -490,7 +491,8 @@ cortexm_regs_write(struct target_s *target, const void *data)
unsigned i;
/* FIXME: Describe what's really going on here */
- adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000052);
+ adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+ ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
/* Map the banked data registers (0x10-0x1c) to the
* debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */