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authorGareth McMullin2012-07-05 20:12:18 +1200
committerGareth McMullin2012-07-05 20:12:18 +1200
commit0c379744e9585eb41739dc45d45be34f83f5b713 (patch)
tree20991fcba3ee2f672a9698000ace223e22a57857 /src/cortexm.c
parent00c4dbfb11e389176bdb2d45a262eb47229cd80b (diff)
cortexm: Poll for S_RESET_ST in DHCSR to detect release from reset.
Diffstat (limited to 'src/cortexm.c')
-rw-r--r--src/cortexm.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cortexm.c b/src/cortexm.c
index e6f2a99..5ec89dd 100644
--- a/src/cortexm.c
+++ b/src/cortexm.c
@@ -515,6 +515,9 @@ cortexm_reset(struct target_s *target)
jtagtap_srst();
+ /* Read DHCSR here to clear S_RESET_ST bit before reset */
+ adiv5_ap_mem_read(ap, CORTEXM_DHCSR);
+
/* Request system reset from NVIC: SRST doesn't work correctly */
/* This could be VECTRESET: 0x05FA0001 (reset only core)
* or SYSRESETREQ: 0x05FA0004 (system reset)
@@ -523,10 +526,7 @@ cortexm_reset(struct target_s *target)
CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
/* Poll for release from reset */
- while(adiv5_ap_mem_read(ap, CORTEXM_AIRCR) &
- (CORTEXM_AIRCR_VECTRESET | CORTEXM_AIRCR_SYSRESETREQ));
-
- platform_delay(2);
+ while(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST);
/* Reset DFSR flags */
adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL);