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authorGareth McMullin2013-06-19 21:05:53 +1200
committerGareth McMullin2013-06-19 21:05:53 +1200
commitd8f737fc53fa27bb13a934f94e39157748401ce4 (patch)
tree82c8b008e1eceafe240f8e394266be818c9d7aa0
parentd90e10cdbaa05509d1ee78f982d3aa0a2c94e972 (diff)
Disable ADIv5 timeout while target is running.
-rw-r--r--src/adiv5_jtagdp.c6
-rw-r--r--src/adiv5_swdp.c4
-rw-r--r--src/cortexm.c4
-rw-r--r--src/include/adiv5.h2
4 files changed, 13 insertions, 3 deletions
diff --git a/src/adiv5_jtagdp.c b/src/adiv5_jtagdp.c
index 693b94e..4306101 100644
--- a/src/adiv5_jtagdp.c
+++ b/src/adiv5_jtagdp.c
@@ -92,10 +92,14 @@ static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t R
jtag_dev_write_ir(dp->dev, APnDP?IR_APACC:IR_DPACC);
+ int tries = 1000;
do {
jtag_dev_shift_dr(dp->dev, (uint8_t*)&response, (uint8_t*)&request, 35);
ack = response & 0x07;
- } while(ack == JTAGDP_ACK_WAIT);
+ } while(--tries && (ack == JTAGDP_ACK_WAIT));
+
+ if (dp->allow_timeout && (ack == JTAGDP_ACK_WAIT))
+ return 0;
if((ack != JTAGDP_ACK_OK)) {
/* Fatal error if invalid ACK response */
diff --git a/src/adiv5_swdp.c b/src/adiv5_swdp.c
index 839127d..c021190 100644
--- a/src/adiv5_swdp.c
+++ b/src/adiv5_swdp.c
@@ -135,8 +135,8 @@ static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW
ack = swdptap_seq_in(3);
} while(--tries && ack == SWDP_ACK_WAIT);
- if(!tries)
- PLATFORM_FATAL_ERROR(1);
+ if (dp->allow_timeout && (ack == SWDP_ACK_WAIT))
+ return 0;
if(ack == SWDP_ACK_FAULT) {
dp->fault = 1;
diff --git a/src/cortexm.c b/src/cortexm.c
index 7819598..a8bb34b 100644
--- a/src/cortexm.c
+++ b/src/cortexm.c
@@ -584,6 +584,7 @@ cortexm_halt_request(struct target_s *target)
{
ADIv5_AP_t *ap = adiv5_target_ap(target);
+ ap->dp->allow_timeout = false;
adiv5_ap_mem_write(ap, CORTEXM_DHCSR,
CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT | CORTEXM_DHCSR_C_DEBUGEN);
}
@@ -596,6 +597,8 @@ cortexm_halt_wait(struct target_s *target)
if (!(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_HALT))
return 0;
+ ap->dp->allow_timeout = false;
+
/* We've halted. Let's find out why. */
uint32_t dfsr = adiv5_ap_mem_read(ap, CORTEXM_DFSR);
adiv5_ap_mem_write(ap, CORTEXM_DFSR, dfsr); /* write back to reset */
@@ -654,6 +657,7 @@ cortexm_halt_resume(struct target_s *target, bool step)
}
adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr);
+ ap->dp->allow_timeout = true;
}
static int cortexm_fault_unwind(struct target_s *target)
diff --git a/src/include/adiv5.h b/src/include/adiv5.h
index 1bfb5a1..64b6a28 100644
--- a/src/include/adiv5.h
+++ b/src/include/adiv5.h
@@ -106,6 +106,8 @@ typedef struct ADIv5_DP_s {
uint32_t idcode;
+ bool allow_timeout;
+
void (*dp_write)(struct ADIv5_DP_s *dp, uint8_t addr, uint32_t value);
uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint8_t addr);