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authorGareth McMullin2015-03-08 12:55:59 -0700
committerGareth McMullin2015-03-19 07:48:47 -0700
commitc2462a6788c119edd9995fa46f1316a9c0431e0b (patch)
treeef75072d2228b362f535efcf3839b7d56aa3253a
parente380ced5171dc3c9098005924f61051a43b79428 (diff)
Add cortexm generic stub call, and use in stm32f1 driver.
-rw-r--r--src/cortexm.c30
-rw-r--r--src/include/cortexm.h3
-rw-r--r--src/stm32f1.c13
3 files changed, 37 insertions, 9 deletions
diff --git a/src/cortexm.c b/src/cortexm.c
index 4bfb4d9..0327edc 100644
--- a/src/cortexm.c
+++ b/src/cortexm.c
@@ -603,6 +603,35 @@ static int cortexm_fault_unwind(struct target_s *target)
return 0;
}
+int cortexm_run_stub(struct target_s *target, uint32_t loadaddr,
+ const uint16_t *stub, uint32_t stublen,
+ uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3)
+{
+ uint32_t regs[target->regs_size / 4];
+
+ memset(regs, 0, sizeof(regs));
+ regs[0] = r0;
+ regs[1] = r1;
+ regs[2] = r2;
+ regs[3] = r3;
+ regs[15] = loadaddr;
+ regs[16] = 0x1000000;
+ regs[19] = 0;
+
+ target_mem_write(target, loadaddr, stub, stublen);
+ cortexm_regs_write(target, regs);
+
+ if (target_check_error(target))
+ return -1;
+
+ /* Execute the stub */
+ cortexm_halt_resume(target, 0);
+ while (!cortexm_halt_wait(target))
+ ;
+
+ return 0;
+}
+
/* The following routines implement hardware breakpoints.
* The Flash Patch and Breakpoint (FPB) system is used. */
@@ -648,7 +677,6 @@ cortexm_clear_hw_bp(struct target_s *target, uint32_t addr)
return 0;
}
-
/* The following routines implement hardware watchpoints.
* The Data Watch and Trace (DWT) system is used. */
diff --git a/src/include/cortexm.h b/src/include/cortexm.h
index 1fd77e6..8f4d45d 100644
--- a/src/include/cortexm.h
+++ b/src/include/cortexm.h
@@ -146,6 +146,9 @@
bool cortexm_attach(struct target_s *target);
void cortexm_detach(struct target_s *target);
void cortexm_halt_resume(struct target_s *target, bool step);
+int cortexm_run_stub(struct target_s *target, uint32_t loadaddr,
+ const uint16_t *stub, uint32_t stublen,
+ uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
#endif
diff --git a/src/stm32f1.c b/src/stm32f1.c
index 0e87c21..daba1b0 100644
--- a/src/stm32f1.c
+++ b/src/stm32f1.c
@@ -32,9 +32,12 @@
#include "general.h"
#include "adiv5.h"
#include "target.h"
+#include "cortexm.h"
#include "command.h"
#include "gdb_packet.h"
+#define SRAM_BASE 0x20000000
+
static bool stm32f1_cmd_erase_mass(target *t);
static bool stm32f1_cmd_option(target *t, int argc, char *argv[]);
@@ -257,15 +260,9 @@ static int stm32f1_flash_write(struct target_s *target, uint32_t dest,
memcpy((uint8_t *)&data[2] + offset, src, len);
/* Write stub and data to target ram and set PC */
- target_mem_write(target, 0x20000000, stm32f1_flash_write_stub, 0x2C);
target_mem_write(target, 0x2000002C, data, sizeof(data));
- target_pc_write(target, 0x20000000);
- if(target_check_error(target))
- return -1;
-
- /* Execute the stub */
- target_halt_resume(target, 0);
- while(!target_halt_wait(target));
+ cortexm_run_stub(target, SRAM_BASE, stm32f1_flash_write_stub, 0x2C,
+ 0, 0, 0, 0);
/* Check for error */
if (target_mem_read32(target, FLASH_SR) & SR_ERROR_MASK)