From 495cc1df494505378977995eeb76b05f20f0b235 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Sun, 13 Jun 2010 17:49:42 +0200 Subject: import firmware from LEGO v1.29 --- AT91SAM7S256/Source/d_ioctrl.r | 315 ++++++++++++++++------------------------- 1 file changed, 121 insertions(+), 194 deletions(-) (limited to 'AT91SAM7S256/Source/d_ioctrl.r') diff --git a/AT91SAM7S256/Source/d_ioctrl.r b/AT91SAM7S256/Source/d_ioctrl.r index 71bf0f4..1071276 100644 --- a/AT91SAM7S256/Source/d_ioctrl.r +++ b/AT91SAM7S256/Source/d_ioctrl.r @@ -1,13 +1,13 @@ // // Date init 14.12.2004 // -// Revision date $Date:: 16-05-06 9:50 $ +// Revision date $Date:: 7-12-07 14:09 $ // // Filename $Workfile:: d_ioctrl.r $ // -// Version $Revision:: 21 $ +// Version $Revision:: 4 $ // -// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Source/d_ioctrl.r $ +// Archive $Archive:: /LMS2006/Sys01/Main_V02/Firmware/Source/d_ioct $ // // Platform C // @@ -15,39 +15,61 @@ #ifdef SAM7S256 +extern void I2cHandler(void); + +enum +{ + I2C_IDLE = 1, + I2C_ERROR = 2, + I2C_TX = 3, + I2C_RX = 4 +}; + #define NO_TO_TX BYTES_TO_TX + 1 #define NO_TO_RX BYTES_TO_RX + 1 -#define TIMEOUT 2100 +#define TIMEOUT (((OSC/16)/1000)*30) /* 100 ms timeout on I2C*/ +#define I2CCLK 400000L +#define TIME400KHZ (((OSC/16L)/(I2CCLK * 2)) + 1) +#define CLDIV (((OSC/I2CCLK)/2)-3) +#define DEVICE_ADR 0x01 +static UBYTE *pIrq; +static UBYTE volatile Cnt; +static UBYTE I2cStatus; +static UBYTE I2cLastStatus; +static UBYTE I2cInBuffer[NO_TO_RX]; +static UBYTE I2cOutBuffer[COPYRIGHTSTRINGLENGTH + 1]; +static UBYTE RxSum; +static ULONG I2CTimerValue; -extern void I2cHandler(void); -static UBYTE *pIrq; -static UBYTE Cnt; -static UBYTE NoToTx; -static UBYTE I2cStatus; -static UBYTE I2cInBuffer[NO_TO_RX]; -static UBYTE I2cOutBuffer[NO_TO_TX]; -static UBYTE RxSum; +#define DISABLEI2cIrqs *AT91C_TWI_IDR = 0x000001C7 +#define ISSUEStopCond *AT91C_TWI_CR = AT91C_TWI_STOP +#define INSERTPower(Power) IoToAvr.Power = Power +#define INSERTPwm(Pwm) IoToAvr.PwmFreq = Pwm +#define SETTime I2CTimerValue = ((*AT91C_PITC_PIIR) & AT91C_PITC_CPIV) -#define I2C_IDLE 1 -#define I2C_ERROR 2 -#define I2C_TX 3 -#define I2C_RX 4 -#define I2CClk 400000L -#define TIME400KHz (((OSC/16L)/(I2CClk * 2)) + 1) -#define CLDIV (((OSC/I2CClk)/2)-3) +#define DISABLETwi *AT91C_PIOA_PPUDR = (AT91C_PA4_TWCK | AT91C_PA3_TWD);/* no pull up */\ + *AT91C_PIOA_MDER = (AT91C_PA4_TWCK | AT91C_PA3_TWD);/* SCL + SDA is open drain*/\ + *AT91C_PIOA_SODR = (AT91C_PA4_TWCK | AT91C_PA3_TWD);/* SCL + SDA is high */\ + *AT91C_PIOA_OER = (AT91C_PA4_TWCK | AT91C_PA3_TWD);/* SCL + SDA is output */\ + *AT91C_PIOA_PER = (AT91C_PA4_TWCK | AT91C_PA3_TWD);/* Disable peripheal */\ -#define DEVICE_ADR 0x01 -#define DISABLEI2cIrqs *AT91C_TWI_IDR = 0x000001C7 -#define ISSUEStopCond *AT91C_TWI_CR = AT91C_TWI_STOP + +#define STARTIrqTx I2cStatus = I2C_TX;\ + I2cLastStatus = I2C_TX;\ + pIrq = I2cOutBuffer;\ + *AT91C_TWI_CR = AT91C_TWI_MSEN;\ + *AT91C_TWI_MMR = (AT91C_TWI_IADRSZ_NO | (DEVICE_ADR << 16)); /* no int. adr, write dir */\ + *AT91C_TWI_IER = 0x00000104; /* Enable TX related irq */\ + *AT91C_TWI_THR = *pIrq #define WAITClk {\ ULONG PitTmr;\ - PitTmr = (*AT91C_PITC_PIIR & AT91C_PITC_CPIV) + TIME400KHz;\ + PitTmr = (*AT91C_PITC_PIIR & AT91C_PITC_CPIV) + TIME400KHZ;\ if (PitTmr >= (*AT91C_PITC_PIMR & AT91C_PITC_CPIV))\ {\ PitTmr -= (*AT91C_PITC_PIMR & AT91C_PITC_CPIV);\ @@ -56,247 +78,152 @@ static UBYTE RxSum; } - #define RESETI2c {\ UBYTE Tmp;\ - *AT91C_PMC_PCER = (1L<