From 495cc1df494505378977995eeb76b05f20f0b235 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Sun, 13 Jun 2010 17:49:42 +0200 Subject: import firmware from LEGO v1.29 --- AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.mac | 143 +++++++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.mac (limited to 'AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.mac') diff --git a/AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.mac b/AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.mac new file mode 100644 index 0000000..6e30936 --- /dev/null +++ b/AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.mac @@ -0,0 +1,143 @@ +// --------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// --------------------------------------------------------- +// The software is delivered "AS IS" without warranty or +// condition of any kind, either express, implied or +// statutory. This includes without limitation any warranty +// or condition with respect to merchantability or fitness +// for any particular purpose, or against the infringements of +// intellectual property rights of others. +// --------------------------------------------------------- +// File: SAM7_RAM.mac +// +// User setup file for CSPY debugger to simulate interrupt +// driven Fibonacchi data input. +// 1.1 18/Aug/04 JPP : Creation +// 1.2 27/Aug/04 JPP : PLL setting +// 1.3 04/Apr/05 JPP : Change variable name +// +// $Revision: 1.2 $ +// +// --------------------------------------------------------- + +__var __mac_i; +__var __mac_pt; + +execUserFlashInit() +{ + __message " ---------------------------------------- FLASH Download V1.1"; + PllSetting(); + execUserPreload(); + execUserSetup(); +} +execUserPreload() +{ +//* + __message "-------------------------------Set CPSR ----------------------------------"; + __writeMemory32(0xffffffff,0xFFFFFC14,"Memory"); + __writeMemory32(0xD3,0x98,"Register"); + __mac_i=__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X; + +//* Init AIC + +// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; + __writeMemory32(0xffffffff,0xFFFFF124,"Memory"); + __writeMemory32(0xffffffff,0xFFFFF128,"Memory"); + +// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register + __readMemory32(0xFFFA0020,"Memory"); + __readMemory32(0xFFFA0060,"Memory"); + __readMemory32(0xFFFA00A0,"Memory"); +// disable peripheral clock Peripheral Clock Disable Register + __writeMemory32(0xffffffff,0xFFFFFC14,"Memory"); + + for (__mac_i=0;__mac_i < 8; __mac_i++) + { + // AT91C_BASE_AIC->AIC_EOICR + __mac_pt = __readMemory32(0xFFFFF130,"Memory"); + + } + + PllSetting(); +//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area + CheckNoRemap(); +//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R + __mac_i=__readMemory32(0xFFFFF240,"Memory"); + __message " ---------------------------------------- Chip ID 0x",__mac_i:%X; + __mac_i=__readMemory32(0xFFFFF244,"Memory"); + __message " ---------------------------------------- Extention 0x",__mac_i:%X; + __mac_i=__readMemory32(0xFFFFFF6C,"Memory"); + __message " ---------------------------------------- Flash Version 0x",__mac_i:%X; +//* Get the chip status + +//* Watchdog Disable +// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS; + __writeMemory32(0x00008000,0xFFFFFD44,"Memory"); +} +//----------------------------------------------------------------------------- +// PllSetting +//------------------------------- +// Set PLL +//----------------------------------------------------------------------------- +PllSetting() +{ +// -1- Enabling the Main Oscillator: +//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register + +//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600 +// AT91C_CKGR_MOSCEN )); //0x0000 0001 +__writeMemory32(0x00000601,0xFFFFFC20,"Memory"); + +// -2- Wait +// -3- Setting PLL and divider: +// - div by 5 Fin = 3,6864 =(18,432 / 5) +// - Mul 25+1: Fout = 95,8464 =(3,6864 *26) +// for 96 MHz the erroe is 0.16% +// Field out NOT USED = 0 +// PLLCOUNT pll startup time esrtimate at : 0.844 ms +// PLLCOUNT 28 = 0.000844 /(1/32768) +// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005 +// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00 +// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000 +__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory"); +// -2- Wait +// -5- Selection of Master Clock and Processor Clock +// select the PLL clock divided by 2 +// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003 +// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004 +__writeMemory32(0x00000007,0xFFFFFC30,"Memory"); + + __message " ---------------------------------------- PLL Enable "; +} + +CheckNoRemap() +{ +//* Read the value at 0x0 + __mac_i=__readMemory32(0x00000000,"Memory"); + __mac_i=__mac_i+1; + __writeMemory32(__mac_i,0x00,"Memory"); + __mac_pt=__readMemory32(0x00000000,"Memory"); + + if (__mac_i == __mac_pt) + { + __message "------------------------------- The Remap is done ----------------------------------------"; + + } else { + __message "------------------------------- The Remap is NOT -----------------------------------------"; +//* Toggel RESET The remap + __writeMemory32(0x00000001,0xFFFFFF00,"Memory"); + } + +} + +execUserSetup() +{ + __writeMemory32(0x0D3,0x98,"Register"); + __message "-------------------------------Set PC ----------------------------------------"; + __writeMemory32(0x00000000,0xB4,"Register"); +} + -- cgit v1.2.3