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-rw-r--r--AT91SAM7S256/armdebug/Debugger/_c_arm_macros.h88
-rw-r--r--AT91SAM7S256/armdebug/Debugger/debug_comm.S763
-rw-r--r--AT91SAM7S256/armdebug/Debugger/debug_comm.h50
-rw-r--r--AT91SAM7S256/armdebug/Debugger/debug_macros.h311
-rw-r--r--AT91SAM7S256/armdebug/Debugger/debug_runlooptasks.S87
-rw-r--r--AT91SAM7S256/armdebug/Debugger/debug_stack.ld15
-rw-r--r--AT91SAM7S256/armdebug/Debugger/debug_stub.S1817
-rw-r--r--AT91SAM7S256/armdebug/Debugger/debug_stub.h299
-rw-r--r--AT91SAM7S256/armdebug/Debugger/debug_test.S53
-rw-r--r--AT91SAM7S256/armdebug/Debugger/debug_test.h35
-rw-r--r--AT91SAM7S256/armdebug/Debugger/undef_handler.S111
11 files changed, 3629 insertions, 0 deletions
diff --git a/AT91SAM7S256/armdebug/Debugger/_c_arm_macros.h b/AT91SAM7S256/armdebug/Debugger/_c_arm_macros.h
new file mode 100644
index 0000000..025542e
--- /dev/null
+++ b/AT91SAM7S256/armdebug/Debugger/_c_arm_macros.h
@@ -0,0 +1,88 @@
+/** @file _c_arm_macros.h
+ * @brief Define macros to support shared C and ASM headers
+ *
+ */
+
+/* Copyright (C) 2010 the NxOS developers
+ *
+ * Module Developed by: TC Wan <tcwan@cs.usm.my>
+ *
+ * Thanks to Bartli (forum post @ embdev.net ARM programming with GCC/GNU tools forum)
+ *
+ * See AUTHORS for a full list of the developers.
+ *
+ * See COPYING for redistribution license
+ *
+ */
+
+#ifndef __C_ARM_MACROS__
+#define __C_ARM_MACROS__
+
+
+#ifdef __ASSEMBLY__
+
+#define NULL 0x0
+#define FALSE 0
+#define TRUE ~FALSE
+
+#define TYPEDEF @
+#define FUNCDEF @
+
+ .set last_enum_value, 0
+ .macro enum_val name
+ .equiv \name, last_enum_value
+ .set last_enum_value, last_enum_value + 1
+ .endm
+
+#define ENUM_BEGIN .set last_enum_value, 0
+
+#define ENUM_VAL(name) enum_val name
+#define ENUM_VALASSIGN(name, value) \
+ .set last_enum_value, value ;\
+ enum_val name
+#define ENUM_END(enum_name)
+
+#else /* C Defines */
+/** Macro to control typedef generation
+ *
+ */
+#define TYPEDEF typedef
+
+/** Macro to control extern generation
+ *
+ */
+#ifndef FUNCDEF
+#define FUNCDEF extern
+#endif
+
+/** Macro to control typedef enum generation
+ *
+ */
+#define ENUM_BEGIN typedef enum {
+
+/** Macro to specify enum instance (auto value assignment)
+ *
+ */
+#define ENUM_VAL(name) name,
+
+/** Macro to control enum specification and value assignment
+*
+*/
+#define ENUM_VALASSIGN(name, value) name = value,
+
+/** Macro to control enum named type generation
+ *
+ */
+#define ENUM_END(enum_name) } enum_name;
+
+#endif
+
+/* Example of how to use the ENUM definition macros
+ENUM_BEGIN
+ENUM_VAL(INIT)
+ENUM_VAL(RESET)
+ENUM_VAL(CONFIGURED)
+ENUM_END(enum_label)
+*/
+
+#endif /* __C_ARM_MACROS__ */
diff --git a/AT91SAM7S256/armdebug/Debugger/debug_comm.S b/AT91SAM7S256/armdebug/Debugger/debug_comm.S
new file mode 100644
index 0000000..44a3a7a
--- /dev/null
+++ b/AT91SAM7S256/armdebug/Debugger/debug_comm.S
@@ -0,0 +1,763 @@
+/** @file debug_comm.S
+ * @brief GDB Server communications support routines
+ *
+ */
+
+/* Copyright (C) 2007-2011 the NxOS developers
+ *
+ * Module Developed by: TC Wan <tcwan@cs.usm.my>
+ *
+ * See AUTHORS for a full list of the developers.
+ *
+ * See COPYING for redistribution license
+ *
+ */
+
+
+/* #define __NXOS__ */ /* Defined externally in SConstruct */
+
+#define __ASSEMBLY__
+#include "debug_macros.h"
+#include "debug_stub.h"
+#include "debug_comm.h"
+
+.bss
+.align 4
+
+debug_InUSBBuf:
+ .space USB_BUFSIZE,0
+debug_OutUSBBuf:
+ .space USB_BUFSIZE,0
+
+debug_msgRxBufPtr:
+ .word 0x0
+debug_msgTxBufPtr:
+ .word 0x0
+
+debug_msgRxBuf_AppendPtr:
+ .word 0x0
+debug_msgTxBuf_AppendPtr:
+ .word 0x0
+
+ .equ RXAPPENDPTR_OFFSET, (debug_msgRxBuf_AppendPtr - debug_msgRxBufPtr)
+ .equ TXAPPENDPTR_OFFSET, (debug_msgTxBuf_AppendPtr - debug_msgTxBufPtr)
+
+debug_segmentRxNum: /* Current Rx Segment Number */
+ .word 0x0
+
+#ifndef __NXOS__
+debug_nxtMsgLength: /* NXT Firmware Received USB Message Length */
+ .word 0x0
+#endif
+
+.data
+.align 4
+
+nxt_usbcmd_header:
+ .byte USB_NXT_TELEGRAMTYPE, 0x00, 0x00 /* padded to 3 bytes */
+
+hex2char_lut:
+ .ascii "0123456789ABCDEF"
+
+/* Macros
+ */
+
+
+/* _hex2char_lut
+ * Internal routine to intialize the LUT address pointer
+ */
+ .macro _hex2char_lut addrptr
+ ldr \addrptr, =hex2char_lut
+ .endm
+
+/* _hex2char_cont
+ * Internal routine that assumes that the LUT has been loaded.
+ * This macro accepts a byte sized hex value as a parameter register(7:0) and returns the
+ * ASCII equivalent in in the same register(7:0)
+ * The second parameter is the LUT address pointer register to use (assumed to be initialized)
+ * WARNING: Assumes that the value in register is sanity checked before invoking macro
+ */
+ .macro _hex2char_cont reg, addrptr
+ ldrb \reg, [\addrptr, \reg]
+ .endm
+
+/* _hex2char
+ * This macro accepts a byte sized hex value as a parameter register(7:0) and returns the
+ * ASCII equivalent in in the same register(7:0)
+ * The second parameter is the LUT address pointer register to use (register content is destroyed)
+ * WARNING: Assumes that the value in register is sanity checked before invoking macro
+ */
+ .macro _hex2char reg, addrptr
+ _hex2char_lut \addrptr
+ _hex2char_cont \reg, \addrptr
+ .endm
+
+/* _char2hex
+ * This macro accepts an ASCII char as a parameter register(7:0) and returns the
+ * equivalent byte sized hex value in in the same register(7:0)
+ * WARNING: Assumes that the char in register is a valid hex char before invoking macro
+ */
+ .macro _char2hex reg
+ cmp \reg, #'A' /* If Alpha */
+ bichs \reg, \reg, #ASCII_LOWER2UPPER_MASK /* Convert to Uppercase */
+ subhs \reg, \reg, #7 /* Adjustment to allow for subtraction with 0x30 */
+ sub \reg, \reg, #0x30 /* get final hex value */
+ .endm
+
+
+.code 32
+.text
+.align 4
+
+
+/* Utility Routines
+ */
+
+/* hex2char
+ * This routine accepts a byte sized hex value in R0(7:0) and returns the
+ * ASCII equivalent in R0(7:0)
+ */
+ .global hex2char
+
+hex2char:
+ stmfd sp!, {r1,lr}
+ and r0, #NIBBLE0 /* make sure that input is sane */
+ _hex2char r0, r1
+ ldmfd sp!, {r1,pc}
+
+/* char2hex
+ * This routine accepts an ASCII character in R0(7:0) and returns the
+ * equivalent byte sized hex value in R0(7:0)
+ */
+ .global char2hex
+
+char2hex:
+ and r0, #BYTE0 /* make sure that input is sane */
+ cmp r0, #'0'
+ blo exit_char2hex
+ cmp r0, #'F'
+ bhi exit_char2hex
+ _char2hex r0
+exit_char2hex:
+ bx lr
+
+/* byte2ascii_cont
+ * (Shared routine, does not perform sanity checks)
+ * On entry:
+ * R0: ASCII buffer pointer
+ * R1[7:0]: byte value
+ * On exit:
+ * R0: Address of next empty char slot in buffer
+ * R1: Destroyed
+ *
+ * This routine accepts an ASCII buffer pointer in R0 and a byte value in R1,
+ * and stores the ASCII equivalent byte value in the buffer pointed to by R0.
+ * Note: On return, R0 points to next empty char slot in buffer
+ */
+byte2ascii_cont:
+ stmfd sp!, {r2,r3,r4, lr}
+ lsl r2, r1, #24 /* Keep copy of input byte value R1[7:0], shifted to MSB R2[31:24] */
+ mov r4, #2 /* Loop counter */
+ _hex2char_lut r3 /* initialize LUT pointer */
+1: ror r2, r2, #28 /* Rotate MSNibble R2[31:28] into LSNibble position R2[3:0] */
+ and r1, r2, #NIBBLE0 /* Mask out everything else, store Nibble in R1 */
+ _hex2char_cont r1, r3 /* Convert nibble to ASCII char */
+ strb r1, [r0], #1
+ subs r4, r4, #1 /* decrement loop counter */
+ bne 1b
+ ldmfd sp!, {r2,r3,r4, pc}
+
+/* byte2ascii
+ * On entry:
+ * R0: ASCII buffer pointer
+ * R1[7:0]: Byte value
+ * On exit:
+ * R0: Address of next empty char slot in buffer
+ * R1: Original Address of Buffer
+ *
+ * This routine accepts an ASCII buffer pointer in R0 and a byte value in R1,
+ * and stores the ASCII equivalent byte value in the buffer pointed to by R0.
+ * Note: On return, R0 points to the next empty char slot in buffer
+ */
+ .global byte2ascii
+
+byte2ascii:
+ stmfd sp!, {r0, lr} /* Keep ASCII buffer pointer */
+ and r1, #BYTE0 /* sanitize input */
+ bl byte2ascii_cont
+ ldmfd sp!, {r1, pc} /* return original string pointer in R1 */
+
+/* halfword2ascii
+ * On entry:
+ * R0: ASCII buffer pointer
+ * R1[15:0]: Halfword value
+ * On exit:
+ * R0: Address of next empty char slot in buffer
+ * R1: Original Address of Buffer
+ *
+ * This routine accepts an ASCII buffer pointer in R0 and a halfword value in R1,
+ * and stores the ASCII equivalent halfword value in the buffer pointed to by R0.
+ * Note: On return, R0 points to the next empty char slot in buffer
+ */
+ .global halfword2ascii
+halfword2ascii:
+ stmfd sp!, {r0,r2,r3, lr} /* Keep ASCII buffer pointer */
+ mov r2, r1, lsl #16 /* copy of input halfword value R1[15:0], shifted to MSH R2[31:16] */
+ mov r3, #2 /* Loop Counter */
+ b _conv_byte2ascii /* goto Byte conversion loop */
+
+/* word2ascii
+ * On entry:
+ * R0: ASCII buffer pointer
+ * R1[31:0]: Word value
+ * On exit:
+ * R0: Address of next empty char slot in buffer
+ * R1: Original Address of Buffer
+ *
+ * This routine accepts an ASCII buffer pointer in R0 and a word value in R1,
+ * and stores the ASCII equivalent word value in the buffer pointed to by R0.
+ * Note: On return, R0 points to the next empty char slot in buffer
+ */
+ .global word2ascii
+word2ascii:
+ stmfd sp!, {r0,r2,r3, lr} /* Keep ASCII buffer pointer */
+ mov r2, r1 /* copy of input word value R1[31:0] */
+ mov r3, #4 /* Loop Counter */
+
+ /* Fall through to byte coversion loop */
+
+_conv_byte2ascii:
+ ror r2, r2, #24 /* Rotate MSB R2[31:24] into LSB position R2[7:0] */
+ and r1, r2, #BYTE0 /* Copy byte value in R2[7:0] into R1 */
+ bl byte2ascii_cont /* R0: next ASCII buffer location pointer, R1: destroyed */
+ subs r3, r3, #1
+ bne _conv_byte2ascii
+ ldmfd sp!, {r1,r2,r3, pc}
+
+
+/* ascii2byte
+ * On entry:
+ * R0: ASCII buffer pointer
+ * On exit:
+ * R0[7:0]: Byte value
+ * R1: Address of next char slot in buffer
+ *
+ * This routine accepts an ASCII buffer pointer in R0,
+ * and returns the byte value in R0[7:0].
+ * Note: On return, R1 points to the ASCII buffer location after the current 2 chars.
+ * WARNING: This routine assumes that the input buffer was sanitized and contains valid Hex chars,
+ * otherwise it will return invalid results.
+ */
+ .global ascii2byte
+
+ascii2byte:
+ stmfd sp!, {r2,r3, lr}
+ mov r3, #2 /* Loop counter */
+ b _conv_ascii2byte
+
+/* ascii2halfword
+ * On entry:
+ * R0: ASCII buffer pointer
+ * On exit:
+ * R0[15:0]: Halfword value
+ * R1: Address of next char slot in buffer
+ *
+ * This routine accepts an ASCII buffer pointer in R0,
+ * and returns the Halfword value in R0[15:0].
+ * Note: On return, R1 points to the ASCII buffer location after the current 4 chars.
+ * WARNING: This routine assumes that the input buffer was sanitized and contains valid Hex chars,
+ * otherwise it will return invalid results.
+ */
+ .global ascii2halfword
+
+ascii2halfword:
+ stmfd sp!, {r2,r3, lr}
+ mov r3, #4 /* Loop counter */
+ b _conv_ascii2byte
+
+
+/* ascii2word
+ * On entry:
+ * R0: ASCII buffer pointer
+ * On exit:
+ * R0[31:0]: Word value
+ * R1: Address of next char slot in buffer
+ *
+ * This routine accepts an ASCII buffer pointer in R0,
+ * and returns the word value in R0[31:0].
+ * Note: On return, R1 points to the ASCII buffer location after the current 8 chars.
+ * WARNING: This routine assumes that the input buffer was sanitized and contains valid Hex chars,
+ * otherwise it will return invalid results.
+ */
+ .global ascii2word
+
+ascii2word:
+ stmfd sp!, {r2,r3, lr}
+ mov r3, #8 /* Loop counter */
+
+ /* Fall through to byte coversion loop */
+
+_conv_ascii2byte:
+ teq r0, #0
+ beq _exit_conv_ascii2byte /* exit if NULL pointer in R0 */
+ mov r1, r0 /* Copy of ASCII buffer pointer */
+ mov r2, #0 /* Initialize results */
+2: ldrb r0, [r1], #1 /* Load ASCII char */
+ bl char2hex /* on return, hex value in R0 */
+ orr r2, r0, r2, lsl #4 /* merge Nibble into results */
+ subs r3, r3, #1
+ bne 2b
+ mov r0, r2 /* Copy it to R0 as return value */
+_exit_conv_ascii2byte:
+ ldmfd sp!, {r2,r3, pc} /* return hex value in R0 */
+
+
+
+
+/* Debugger Communications Routines
+ * It does not make sense to pass information from the Debugger Module to the Comm. link one character
+ * at a time, especially if we're not using a native serial interface (e.g., EIA-232). Consequently
+ * a Message interface has been defined. This can still call getChar() and putChar() subroutines
+ * if so desired, but it'll be a purely internal matter.
+ *
+ * Message Format
+ * Since we need to use EP1&2 (Bulk channels) to communicate with the PC Host, the messages should
+ * follow the NXT Direct Commands message structure (this will allow for interoperability with NXT Firmware
+ * in addition to NxOS). The maximum length of any USB communications via the Bulk channel is 64 bytes.
+ * There is a one byte Telegram Type field which identifies the type of telegram, followed by the
+ * Telegram header and actual message.
+ *
+ * The LEGO Mindstorms Communications Protocol Direct Commands GDB Message format (including all headers)
+ * is as follows:
+ *
+ * GDB Command
+ * ===========
+ * Byte 0: Telegram Type Field (0x8d Direct Command, No response required) | USB Channel Header
+ * Byte 1: Segment No (1-255, 0: Last Segment; limit is MSG_NUMSEGMENTS) |
+ * Byte 2: Telegram Size (Len of USB Buffer - 3, max is MSG_SEGMENTSIZE) |
+ * Byte 3-N: Message data | GDB Command
+ *
+ * The GDB Command (of size M) has the following format:
+ * Offset 0: '$'
+ * Offset 1: GDB Command char
+ * Offset 2 - (M-4): Command packet info
+ * Offset M-3: '#'
+ * Offset M-2: MSB of Checksum
+ * Offset M-1: LSB of Checksum
+ *
+ * The maximum size of a GDB Command packet is MSGBUF_SIZE - 4 ('$', '#', 2 byte checksum)
+ *
+ * GDB Response
+ * ============
+ * Byte 0: Telegram Type Field (0x8d Direct Command, No response required) | USB Channel Header
+ * Byte 1: Segment No (1-255, 0: Last Segment; limit is MSG_NUMSEGMENTS) |
+ * Byte 2: Telegram Size (Len of USB Buffer - 3, max is MSG_SEGMENTSIZE) |
+ * Byte 3-N: Message data | GDB Response
+ *
+ * The GDB Response (of size M) has the following format:
+ * Offset 0: '+' or '-' Command Received Status
+ * Offset 1: '$'
+ * Offset 2 - (M-4): Response packet info
+ * Offset M-3: '#'
+ * Offset M-2: MSB of Checksum
+ * Offset M-1: LSB of Checksum
+ *
+ * The maximum size of a GDB Response packet is MSGBUF_SIZE - 5 ('-'/'+', '$', '#', 2 byte checksum)
+ *
+ * Note: The Telegram Size is the actual size of the Message Data portion
+ * (i.e., excludes the three header bytes, includes the GDB Command/Response Packet checksum bytes
+ * in the last segment)
+ */
+
+ .global dbg__comm_init
+/* dbg__comm_init
+ * Initialize communications channel.
+ * On Entry:
+ * R0: MSG Rx Buf Pointer
+ * R1: MSG Tx Buf Pointer
+ */
+
+dbg__comm_init:
+ stmfd sp!, {lr}
+ ldr r2, =debug_msgRxBufPtr
+ stmia r2!, {r0, r1} /* debug_msgRxBufPtr and debug_msgTxBufPtr */
+ stmia r2!, {r0, r1} /* debug_msgRxBuf_AppendPtr and debug_msgTxBuf_AppendPtr */
+ bl _dbg__usb_readbuf_reset
+ ldmfd sp!, {pc}
+
+_dbg__usb_readbuf_reset:
+#ifdef __NXOS__
+ stmfd sp!, {lr}
+ ldr r0, =debug_InUSBBuf
+ mov r1, #USB_BUFSIZE
+ ldr r2, =nx_usb_read
+ mov lr, pc
+ bx r2
+ ldmfd sp!, {pc}
+#else
+ ldr r1, =debug_nxtMsgLength
+ mov r0, #0
+ str r0, [r1] /* Clear NXT USB Received Message Length */
+ bx lr
+
+ .global dbg__copyNxtDebugMsg
+/* dbg__copyNxtDebugMsg
+ * Copy NXT Firmware Debug Message to our own Buffers, indicate Msg Received status.
+ * On Entry:
+ * R0: NXT USB Input Buf Pointer
+ * R1: USB Command Bit
+ * R2: USB Raw Message Length
+ * On Exit:
+ * R0-R3: Destroyed
+ */
+
+dbg__copyNxtDebugMsg:
+ ldr r1, =debug_nxtMsgLength
+ str r2, [r1]
+ ldr r1, =debug_InUSBBuf
+ _dbg_memcpy r1, r0, r2, r3 /* r3: scratch register */
+ bx lr
+#endif
+
+/* _dbg_reset_msgTxBuf_AppendPtr
+ * Internal variable to reset pointers.
+ * On Exit:
+ * R0: debug_msgTxBuf_AppendPtr
+ * R1: destroyed
+ */
+_dbg_reset_msgTxBuf_AppendPtr:
+ ldr r1, =debug_msgTxBufPtr /* Should not be modified */
+ ldr r0, [r1]
+ str r0, [r1, #TXAPPENDPTR_OFFSET]
+ mov pc, lr
+
+/* _dbg__usbHasMsg
+ * Internal Segment Reassembly Routine.
+ * On exit:
+ * r0: !0: (Availale Telegram Message Size), 0: no incoming message/segment
+ * r1: message segment number
+ */
+_dbg__usbHasMsg:
+ stmfd sp!, {lr}
+#ifdef __NXOS__
+ ldr r2, =nx_usb_data_read
+ mov lr,pc
+ bx r2 /* Number of bytes read in R0 */
+ /* Note: The return value in R0 is the USB Buffer Size, includes NXT Direct Command Header */
+#else
+ ldr r0, =debug_nxtMsgLength
+ ldr r0, [r0] /* R0 contains the USB Buffer Size, including the NXT Direct Command Header */
+#endif
+
+ ldr r2, =debug_InUSBBuf
+ ldrb r1, [r2, #USB_NXT_TELEGRAMTYPE_OFFSET]
+ cmp r1, #USB_NXT_TELEGRAMTYPE
+ bne invalid_USBMsg /* Invalid telegram type, ignore */
+
+ ldrb r1, [r2, #USB_NXT_TELEGRAMSIZE_OFFSET]
+ sub r0, r0, r1 /* USB Buffer Size - Telegram Size = 3 (header size) */
+ cmp r0, #USB_GDBMSG_START /* Start offset is equal to header size */
+ bne invalid_USBMsg /* Invalid Message Length, ignore */
+
+ mov r0, r1 /* Telegram Message Size */
+ ldrb r1, [r2, #USB_NXT_SEGNUM_OFFSET]
+ b _exit_dbg__usbHasMsg
+
+invalid_USBMsg:
+ mov r0, #0
+_exit_dbg__usbHasMsg:
+ ldmfd sp!, {pc}
+
+/* _copy_msg_from_usbbuf
+ * Internal USB buffer copy routine, handles segment reassembly.
+ * On entry:
+ * r0: number of bytes to copy
+ * r1: segment number
+ * On exit:
+ * r0: cummulative message length
+ * r1: segment number
+ * r2, r3: Destroyed
+ */
+_copy_msg_from_usbbuf:
+ stmfd sp!, {r1,r4,r5,r6,lr}
+ movs r4, r0
+ beq _exit_copy_msg_from_usbbuf
+
+ ldr r6, =debug_msgRxBufPtr /* Address of Pointers */
+ ldr r5, [r6] /* Rx buffer Start Address */
+ ldr r2, [r6, #RXAPPENDPTR_OFFSET] /* Append Pointer */
+
+ sub r3, r2, r5 /* r3: current length of message */
+ add r3, r3, r4 /* new cummulative length of message */
+ cmp r3, #MSGBUF_SIZE
+ movhi r4, #0 /* Buffer overflow! */
+ strhi r5, [r6, #RXAPPENDPTR_OFFSET] /* Reset AppendPtr to beginning of Rx Buffer */
+ bhi _exit_copy_msg_from_usbbuf
+
+ ldr r3, =debug_InUSBBuf
+ add r3, r3, #USB_GDBMSG_START
+ _dbg_memcpy r2, r3, r4, r0 /* r2 updated to point to next empty char slot in Rx buffer */
+ sub r4, r2, r5 /* r4: cummulative length of message */
+
+ /* Update debug_msgRxBuf_AppendPtr */
+ teq r1, #0 /* Check if this is last segment (segment 0) */
+ streq r5, [r6, #RXAPPENDPTR_OFFSET] /* Reset AppendPtr to beginning of Rx Buffer if so */
+ strne r2, [r6, #RXAPPENDPTR_OFFSET] /* Otherwise, update Append Pointer to receive next segment */
+
+_exit_copy_msg_from_usbbuf:
+ bl _dbg__usb_readbuf_reset /* Next USB telegram transaction */
+ mov r0, r4 /* Return cummulative message length in R0 */
+ ldmfd sp!, {r1,r4,r5,r6,pc} /* Return segment number in R1 */
+
+
+/* _msgbuf_checksum
+ * Internal routine to calculate checksum character buffer.
+ * On entry:
+ * r0: pointer to character buffer to checksum (assume ASCIIZ terminated)
+ * On exit:
+ * r0: pointer to character buffer after ASCIIZ
+ * r1: checksum (8-bit binary)
+ * r2: message length
+ * r3: destroyed
+ */
+_msgbuf_checksum:
+ mov r1, #0 /* clear checksum */
+ mov r2, #0 /* clear length */
+1: ldrb r3, [r0], #1 /* Iterate through buffer */
+ add r1, r1, r3 /* cummulative sum of char */
+ teq r3, #0
+ addne r2, r2, #1 /* increment message length */
+ bne 1b /* until ASCIIZ found */
+ and r1, #BYTE0 /* Modulo 256 */
+ mov pc, lr
+
+ .global dbg__getDebugMsg
+/* dbg__getDebugMsg
+ * Retrieve pending Debugger Message if available (Non-Blocking).
+ * On entry:
+ * No parameters (assume pointers were initialized previously using dbg__comm_init)
+ * On exit:
+ * r0: >0 = Valid GDB Message Length (incl '$', excluding '#' and checksum),
+ * 0 = no valid message (yet), -1 = error
+ * r1, r2, r3: Destroyed
+ * Note: If GDB Message were returned, it is ASCIIZ terminated, does not include '#' and checksum
+ */
+dbg__getDebugMsg:
+ stmfd sp!, {r4,lr}
+ bl _dbg__usbHasMsg /* r0: message length, r1: segment number */
+ teq r0, #0
+ beq exit_dbg__getDebugMsg /* no new message, exit with R0 = 0 */
+
+ ldr r4, =debug_segmentRxNum
+ ldr r2, [r4] /* Get current Segment Number */
+ add r2, r2, #1 /* Expected Segment Number for comparison */
+ teq r1, #0
+ streq r1, [r4] /* Update current Segment Number with 0 since it is the last segment */
+ beq _hasMsg2Copy
+ cmp r1, #MSG_NUMSEGMENTS /* Segment Number < MSG_NUMSEGMENTS? */
+ bhs _invalid_segment
+ teq r1, r2 /* Valid Segment Number, check against Expected Segment Number */
+ beq _hasMsg2Copy /* Segment Number matches Expected Segment Number, update buffers */
+
+_invalid_segment:
+ bl _dbg__usb_readbuf_reset /* Invalid, Next USB telegram transaction */
+ mov r0, #0 /* Reset Segment Number */
+ str r0, [r4] /* Update current Segment Number with 0 to prepare for new message */
+ b exit_dbg__getMsgError /* Exit with error */
+
+_hasMsg2Copy:
+ str r1, [r4] /* Update current Segment Number */
+ bl _copy_msg_from_usbbuf /* r0: cummulative message length, r1: segment number */
+ teq r1, #0
+ movne r0, #0 /* Incomplete message, ignore for now */
+ bne exit_dbg__getDebugMsg /* Message not complete yet, exit */
+
+ /* Check for valid GDB message */
+ mov r4, r0 /* keep message length in R4, assume to be within MSGBUF_SIZE */
+ ldr r3, =debug_msgRxBufPtr
+ ldr r3, [r3] /* Rx buffer Start Address */
+
+#ifdef CHECK_GDBSTARTCHAR
+ /* Checked in dbg__bkpt_waitCMD */
+ ldrb r0, [r3]
+ teq r0, #MSGBUF_STARTCHAR /* Look for '$' */
+ bne exit_dbg__getMsgError /* No start char '$', exit with error */
+#endif
+
+ sub r2, r4, #MSGBUF_CHKSUMOFFSET /* Look for '#': Message Length - 3 = '#' offset */
+ ldrb r0, [r3, r2]
+ teq r0, #MSGBUF_CHKSUMCHAR
+ bne exit_dbg__getMsgError /* No checksum char '#', exit with error */
+
+ mov r1, #0
+ strb r1, [r3, r2] /* Zero out '#' char for checksum calc later */
+
+ add r0, r3, #1 /* Checksum packet data (excl '$') */
+ bl _msgbuf_checksum /* R2: length (excl '$'), R1: calculated checksum, R0: pointer to checksum in receive buffer */
+ mov r3, r1 /* Keep calculated checksum in R3 (R1 destroyed by ascii2byte) */
+ bl ascii2byte /* R0: received checksum, R1: address of next buffer location */
+ teq r0, r3 /* Compare calculated checksum in R3 against received checksum in R0 */
+ bne exit_dbg__getMsgError /* Checksums do not match, exit with error */
+
+ subeq r0, r4, #MSGBUF_CHKSUMOFFSET /* Update message length (incl '$') as return parameter */
+ add r2, r2, #1 /* expected message length (from _msgbuf_checksum) */
+ teq r0, r2
+ beq exit_dbg__getDebugMsg /* Valid length, return */
+
+exit_dbg__getMsgError:
+ mov r0, #MSGBUF_MSGERROR
+exit_dbg__getDebugMsg:
+ ldmfd sp!, {r4,pc}
+
+/* _dbg__sendUSBMsg
+ * Internal USB send routine (interfaces with drivers).
+ * On entry:
+ * R0: Total USB Message Buffer length
+ * On exit:
+ R0: Tx Status (TRUE if data sent)
+ */
+_dbg__sendUSBMsg:
+ stmfd sp!, {r4, lr}
+ mov r4, r0 /* Keep USB Buffer length in R4 */
+#ifdef __NXOS__
+ /* Check USB bus status, transmit message if possible */
+ bl nx_usb_is_connected /* R0 = True if USB is ready */
+ cmp r0, #TRUE
+ bne _exit_dbg__sendUSBMsg
+
+ /* Actual transmission (blocking) */
+ ldr r0, =debug_OutUSBBuf /* data pointer parameter */
+ mov r1, r4 /* USB buffer length */
+ bl nx_usb_write
+
+1: bl nx_usb_data_written /* R0 = True if data has been sent */
+ cmp r0, #TRUE
+ /* FIXME: implement timeout */
+ bne 1b /* Busy Wait Loop */
+#else
+ /* Check USB bus status, transmit message if possible */
+ bl dUsbIsConfigured /* R0: UByte status, TRUE / FALSE */
+ teq r0, #nxt_UBYTE_TRUE
+ movne r0, #FALSE
+ bne _exit_dbg__sendUSBMsg
+
+ /* Actual transmission (blocking) */
+ ldr r0, =debug_OutUSBBuf /* data pointer parameter */
+ mov r1, r4 /* USB buffer length */
+ bl dUsbWrite /* call NXT Firmware USB driver, return 0: done, !0: remaining chars */
+ teq r0, #0 /* Tx done if returned length is 0 */
+ movne r0, #FALSE
+ moveq r0, #TRUE /* Convert NXT firmware return value to our Status (TRUE/FALSE) */
+#endif
+
+_exit_dbg__sendUSBMsg:
+ ldmfd sp!, {r4, pc}
+
+
+/* _copy_msg_to_usbbuf
+ * Internal USB buffer copy routine, handles segment fragmentation.
+ * On entry:
+ * r0: number of bytes to copy
+ * r1: segment number
+ * On exit:
+ * r0: cummulative message length
+ * r1: segment number
+ * r2, r3: Destroyed
+ */
+_copy_msg_to_usbbuf:
+ stmfd sp!, {r1,r4,r5,r6,lr}
+ ldr r6, =debug_msgTxBufPtr /* Address of Pointers */
+ ldr r5, [r6, #TXAPPENDPTR_OFFSET] /* Retrieve Tx Append Pointer */
+
+ movs r4, r0
+ beq _exit_copy_msg_to_usbbuf
+
+#ifdef CHECK_TXLEN
+ add r0, r4, #USB_GDBMSG_START /* offset = header size */
+ cmp r0, #USB_BUFSIZE
+ bhi _exit_copy_msg_to_usbbuf /* We let calling routine detect problem (segment number will increment) */
+#endif
+
+ /* Fill in USB Message Header */
+ ldr r3, =debug_OutUSBBuf
+ mov r2, #USB_NXT_TELEGRAMTYPE
+ strb r2, [r3], #1 /* Telegram type */
+ strb r1, [r3], #1 /* Segment Number */
+ strb r0, [r3], #1 /* Message Length */
+
+ mov r2, r5 /* Copy to R2 for updating */
+ mov r1, r4 /* actual GDB message fragment length (exclude USB header) */
+ _dbg_memcpy r3, r2, r1, r0 /* This copies over the message fragment, r3, r2 updated */
+ mov r5, r2 /* Updated Tx Append Pointer, keep in R5 for now */
+
+ add r0, r4, #USB_GDBMSG_START /* Total USB Buffer Size for Tx (USB_GDBMSG_START offset = header size) */
+ bl _dbg__sendUSBMsg /* Common interface routine to USB drivers */
+ cmp r0, #TRUE
+ ldrne r5, [r6, #TXAPPENDPTR_OFFSET] /* Tx failed, Retrieve Original Tx Append Pointer */
+ streq r5, [r6, #TXAPPENDPTR_OFFSET] /* Tx succeeded, Update Tx Append Pointer to new position */
+
+_exit_copy_msg_to_usbbuf:
+ ldr r6, [r6] /* Retrieve Tx Buffer Start Address */
+ sub r0, r5, r6 /* Return calculated cummulative message length (R0) */
+ ldmfd sp!, {r1,r4,r5,r6,pc} /* Return segment number in R1 */
+
+ .global dbg__putDebugMsg
+/* dbg__putDebugMsg
+ * Sends Debugger Message from calling routine after appending checksum (Blocking) .
+ * On entry:
+ * No parameters (assume pointers were initialized previously using dbg__comm_init)
+ * On exit:
+ * r0: status (0: success, -1: error)
+ * Note: GDB Message to be sent must be ASCIIZ terminated, does not include '#' and checksum
+ * Response packets start with '+'/'-' followed by '$' (2 bytes prefix)
+ */
+dbg__putDebugMsg:
+ stmfd sp!, {r4,r5,lr}
+ /* Perform Checksum Calculation */
+ ldr r5, =debug_msgTxBufPtr /* R5: data structure base pointer */
+ ldr r4, [r5] /* Tx buffer Start Address */
+ str r4, [r5, #TXAPPENDPTR_OFFSET] /* Reset Tx buffer Append Pointer */
+ add r0, r4, #2 /* skip '+'/'-' and '$' */
+ bl _msgbuf_checksum /* R2: length (excl '+'/'-' and '$'), R1: calculated checksum, R0: pointer to checksum in tx buffer */
+
+#ifdef CHECK_TXLEN
+ add r2, r2, #2 /* r2: returned length from _msgbuf_checksum, added with prefix length */
+ sub r3, r0, r4 /* r3: calculated length from pointers (incl. prefix length) */
+ teq r2, r3
+ bne exit_dbg__putMsgError
+#endif
+
+ mov r3, #MSGBUF_CHKSUMCHAR
+ strb r3, [r0, #-1] /* Insert '#' */
+ bl byte2ascii /* On return, R0 points to location after checksum bytes, R1 is original pointer to checksum */
+ sub r4, r0, r4 /* R4 = Calculated total message length (incl '+'/'-' and '$', '#' and checksum bytes */
+ cmp r4, #MSG_SEGMENTSIZE /* If total message length > MSG_SEGMENTSIZE */
+ mov r1, #0 /* Initialize Segment Number = 0 (last segment) first */
+ mov r0, #0 /* Initial cummulative message length */
+ mov r5, #0 /* Previous cummulative message length */
+
+ /* We assume unsigned message lengths, so the arithmetic MUST NOT result in negative values */
+_cont_putMsg:
+ cmp r4, r0
+ movls r0, #0 /* R0: Exit status (success) */
+ bls exit_dbg__putDebugMsg /* If Total message length (r4) <= Cummulative message length (r0), we're done */
+ add r2, r0, #MSG_SEGMENTSIZE /* R2: calculate new Max cummulative message length */
+ cmp r4, r2 /* Check total message length (R4) against new Max cummulative message length (R2) */
+ subls r0, r4, r0 /* if total message length (R4) <= new Max cummulative message length (R2), send remainder */
+ movls r1, #0 /* Flag as last segment (Segment Number = 0) */
+ movhi r0, #MSG_SEGMENTSIZE /* else send MSG_SEGMENTSIZE bytes */
+ addhi r1, r1, #1 /* Increment Segment Number */
+ cmp r1, #MSG_NUMSEGMENTS
+ bhs exit_dbg__putMsgError /* If Segment Number >= MSG_NUMSEGMENTS, flag error */
+ bl _copy_msg_to_usbbuf /* R0: cummulative message length, R1: segment number */
+ teq r5, r0 /* Check if we managed to transmit the previous message */
+ beq exit_dbg__putMsgError /* No, flag error */
+ movne r5, r0 /* Update previous cummulative message length */
+ b _cont_putMsg
+
+exit_dbg__putMsgError:
+ mov r0, #MSGBUF_MSGERROR
+exit_dbg__putDebugMsg:
+ ldmfd sp!, {r4,r5,pc}
+
+
diff --git a/AT91SAM7S256/armdebug/Debugger/debug_comm.h b/AT91SAM7S256/armdebug/Debugger/debug_comm.h
new file mode 100644
index 0000000..1be5e7b
--- /dev/null
+++ b/AT91SAM7S256/armdebug/Debugger/debug_comm.h
@@ -0,0 +1,50 @@
+/** @file debug_comm.h
+ * @brief Shared C/ASM header file for debugger communications
+ *
+ */
+
+/* Copyright (C) 2007-2010 the NxOS developers
+ *
+ * Module Developed by: TC Wan <tcwan@cs.usm.my>
+ *
+ * See AUTHORS for a full list of the developers.
+ *
+ * See COPYING for redistribution license
+ *
+ */
+
+#ifndef __DEBUG_COMM_H__
+#define __DEBUG_COMM_H__
+
+#include "_c_arm_macros.h"
+
+/* This is a place holder header file to allow for interfacing with C Routines in either
+ * NxOS or NXT Firmware.
+ *
+ * Since the header files from the original source trees were meant for C programs, we can't
+ * include them directly. Here we just use .extern to reference the routines.
+ */
+
+#ifdef __NXOS__
+
+ .extern nx_usb_is_connected
+ .extern nx_usb_can_write
+ .extern nx_usb_write
+ .extern nx_usb_data_written
+ .extern nx_usb_read
+ .extern nx_usb_data_read
+
+#else /* NXT Firmware */
+
+ .extern cCommInit
+ .extern cCommCtrl
+ .extern cCommExit
+ .extern dUsbWrite
+ .extern dUsbRead
+ .extern dUsbIsConfigured
+ .equ nxt_UBYTE_TRUE, 1
+ .equ nxt_UBYTE_FALSE, 0
+
+#endif
+
+#endif
diff --git a/AT91SAM7S256/armdebug/Debugger/debug_macros.h b/AT91SAM7S256/armdebug/Debugger/debug_macros.h
new file mode 100644
index 0000000..dc1efba
--- /dev/null
+++ b/AT91SAM7S256/armdebug/Debugger/debug_macros.h
@@ -0,0 +1,311 @@
+/** @file debug_macros.h
+ * @brief internal macros used by debug_stub routines
+ *
+ */
+
+/* Copyright (C) 2007-2010 the NxOS developers
+ *
+ * Module Developed by: TC Wan <tcwan@cs.usm.my>
+ *
+ * See AUTHORS for a full list of the developers.
+ *
+ * See COPYING for redistribution license
+ *
+ */
+
+#ifndef __DEBUG_MACROS_H__
+#define __DEBUG_MACROS_H__
+
+
+
+/** @addtogroup debug_macros */
+/*@{*/
+
+/* _dbg_jumpTableHandler
+ * Call Jump Table Routine based on Index
+ * On entry:
+ * jumptableaddr is the address (constant) of the Jump Table
+ * jumpreg is the register used to perform the indirect jump
+ * indexreg contains jump table index value
+ */
+ .macro _dbg_jumpTableHandler jumptableaddr, jumpreg, indexreg
+
+ ldr \jumpreg, =\jumptableaddr
+ ldr \jumpreg, [\jumpreg, \indexreg, lsl #2]
+ mov lr, pc
+ bx \jumpreg /* Call Command Handler Routine */
+ .endm
+
+
+/* _dbg_thumbDecodeEntry
+ * Load Thumb Instruction Decoder Entry
+ * On entry:
+ * instrreg is the register to load the instruction into
+ * instrmask is the register to load the instruction mask into
+ * codehandler is the register to load the code handling routine into
+ * indexreg contains decode table index value
+ * NOTE: instrreg, instrmask, codehandler must be in increasing register number order
+ */
+ .macro _dbg_thumbDecodeEntry instrreg, instrmask, codehandler, indexreg
+
+ ldr \instrmask, =debug_thumbDecodeTable /* Temporary register */
+ add \instrmask, \instrmask, \indexreg, lsl #3
+ ldm \instrmask, {\instrreg, \codehandler} /* LSHW: IID, MSHW: IBM */
+ mov \instrmask, \instrreg, lsr #16
+ and \instrreg, \instrreg, #HLFWRD0
+ .endm
+
+/* _dbg_armDecodeEntry
+ * Load ARM Instruction Decoder Entry
+ * On entry:
+ * instrreg is the register to load the instruction into
+ * instrmask is the register to load the instruction mask into
+ * codehandler is the register to load the code handling routine into
+ * indexreg contains decode table index value
+ * NOTE: instrreg, instrmask, codehandler must be in increasing register number order
+ */
+ .macro _dbg_armDecodeEntry instrreg, instrmask, codehandler, indexreg
+
+ ldr \instrmask, =debug_thumbDecodeTable /* Temporary register */
+ add \instrmask, \instrmask, \indexreg, lsl #3
+ add \instrmask, \instrmask, \indexreg, lsl #2 /* 12 byte entries */
+ ldm \instrmask, {\instrreg, \instrmask, \codehandler}
+ .endm
+
+/* _asciiz
+ * Terminate string given string buffer pointer in \strptr
+ * scratchreg is used as a scratch register (destroyed)
+ *
+ */
+ .macro _asciiz strptr, scratchreg
+ mov \scratchreg, #0 /* ASCIIZ character */
+ strb \scratchreg, [\strptr] /* Terminate ASCII string */
+ .endm
+
+
+/* _dbg_stpcpy
+ * _dbg_stpcpy macro
+ * On entry:
+ * deststrptr: Destination string
+ * sourcestrptr: Source string
+ * scratchreg: scratch register for copying
+ * On exit:
+ * deststrptr: Pointer to ASCIIZ character in destination string
+ * sourcestrptr: Pointer to next character slot in source string (after ASCIIZ)
+ * scratchreg: destroyed
+ */
+ .macro _dbg_stpcpy deststrptr, sourcestrptr, scratchreg
+1: ldrb \scratchreg, [\sourcestrptr], #1
+ strb \scratchreg, [\deststrptr], #1
+ teq \scratchreg, #0
+ bne 1b
+ sub \deststrptr, \deststrptr, #1 /* Adjust Destination string pointer to point at ASCIIZ character */
+ .endm
+
+/* _dbg_memcpy
+ * _dbg_stpcpy macro
+ * On entry:
+ * deststrptr: Destination string
+ * sourcestrptr: Source string
+ * sizereg: Number of bytes to copy
+ * scratchreg: scratch register for copying
+ * On exit:
+ * deststrptr: Pointer to next character slot in destination string
+ * sourcestrptr: Pointer to next character slot in source string
+ * sizereg, scratchreg: destroyed
+ */
+ .macro _dbg_memcpy deststrptr, sourcestrptr, sizereg, scratchreg
+1: ldrb \scratchreg, [\sourcestrptr], #1
+ strb \scratchreg, [\deststrptr], #1
+ subs \sizereg, \sizereg, #1
+ bne 1b
+ .endm
+
+/* _dbg_outputMsgValidResponse
+ * Return Message with valid response ('+$')
+ * On exit:
+ * R0: Pointer to Output Buffer next character slot location
+ * R1: destroyed
+ * R2: destroyed
+ */
+ .macro _dbg_outputMsgValidResponse
+ ldr r0, =debug_OutMsgBuf
+ ldr r1, =debug_ValidResponsePrefix
+ _dbg_stpcpy r0, r1, r2
+ .endm
+
+
+/* _dbg_outputMsgStatusOk
+ * Return Message with Ok ('+$OK') status
+ * On exit:
+ * R0: Pointer to Output Buffer ASCIIZ location
+ * R1: destroyed
+ * R2: destroyed
+ */
+ .macro _dbg_outputMsgStatusOk
+ ldr r0, =debug_OutMsgBuf
+ ldr r1, =debug_OkResponse /* ASCIIZ terminated */
+ _dbg_stpcpy r0, r1, r2
+ .endm
+
+/* _dbg_outputMsgStatusErr
+ * Return Message with Error ('-$ENN') status
+ * On entry:
+ * R0: error code
+ * On exit:
+ * R0: Pointer to Output Buffer ASCIIZ location
+ * R1: destroyed
+ * R2: destroyed
+ * R3: destroyed
+ */
+ .macro _dbg_outputMsgStatusErr
+ mov r1, r0
+ ldr r0, =debug_OutMsgBuf
+ ldr r2, =debug_ErrorResponsePrefix
+ _dbg_stpcpy r0, r2, r3
+ bl byte2ascii /* R0 points to buffer position after byte value */
+ _asciiz r0, r1
+ .endm
+
+/* _dbg_outputMsgStatusErrCode
+ * Return Message with Error ('-$ENN') status
+ * On exit:
+ * R0: Pointer to Output Buffer ASCIIZ location
+ * R1: destroyed
+ * R2: destroyed
+ */
+ .macro _dbg_outputMsgStatusErrCode errcode
+ ldr r0, =debug_OutMsgBuf
+ ldr r1, =debug_ErrorResponsePrefix
+ _dbg_stpcpy r0, r1, r2
+ mov r1, #\errcode
+ bl byte2ascii /* R0 points to buffer position after byte value */
+ _asciiz r0, r1
+ .endm
+
+/* _dbg_outputMsgStatusSig
+ * Return Message with Signal ('+$SNN') status
+ * On exit:
+ * R0: Pointer to Output Buffer ASCIIZ location
+ * R1: destroyed
+ * R2: destroyed
+ */
+ .macro _dbg_outputMsgStatusSig statuscode
+ ldr r0, =debug_OutMsgBuf
+ ldr r1, =debug_SignalResponsePrefix
+ _dbg_stpcpy r0, r1, r2
+ mov r1, #\statuscode
+ bl byte2ascii /* R0 points to buffer position after byte value */
+ _asciiz r0, r1
+ .endm
+
+/* _getdbgregisterfromindex
+ * Retrieve register contents from debugger stack given index
+ *
+ * On entry:
+ * indexreg contains debugger stack index value (0-max index)
+ * On exit:
+ * indexreg: Breakpoint index (preserved)
+ * contentsreg: Register Contents for given index
+ */
+ .macro _getdbgregisterfromindex indexreg, contentsreg
+ ldr \contentsreg, =__debugger_stack_bottom__
+ ldr \contentsreg, [\contentsreg, \indexreg, lsl #2]
+ .endm
+
+/* _setdbgregisterfromindex
+ * Store register contents to debugger stack given index
+ *
+ * On entry:
+ * indexreg contains debugger stack index value (0-max index)
+ * contentsreg: Register Contents for given index
+ * addressreg: Scratch register for address pointer
+ * On exit:
+ * indexreg: Breakpoint index (preserved)
+ * contentsreg: Register Contents for given index
+ */
+ .macro _setdbgregisterfromindex indexreg, contentsreg, addressreg
+ ldr \addressreg, =__debugger_stack_bottom__
+ str \contentsreg, [\addressreg, \indexreg, lsl #2]
+ .endm
+
+
+/* _index2bkptindex_addr
+ * Convert Breakpoint index to breakpoing entry address
+ *
+ * On entry:
+ * indexreg contains breakpoint index value
+ * On exit:
+ * indexreg: Breakpoint index (preserved)
+ * addrreg: Breakpoint Entry Address
+ */
+ .macro _index2bkptindex_addr indexreg, addrreg
+ ldr \addrreg, =__breakpoints_start__
+ add \addrreg, \addrreg, \indexreg, lsl #3 /* Calculate Breakpoint Entry Address */
+ .endm
+
+/* _dbg_getstate
+ * Get Debugger State
+ * On exit:
+ * reg: Debugger State enum
+ */
+ .macro _dbg_getstate reg
+ ldr \reg, =debug_state
+ ldr \reg, [\reg]
+ .endm
+
+/* _dbg_setstate
+ * Set Debugger State to given value
+ * On exit:
+ * r0, r1: destroyed
+ */
+ .macro _dbg_setstate state
+ ldr r0, =\state
+ ldr r1, =debug_state
+ str r0, [r1]
+ .endm
+
+/* _dbg_getcurrbkpt_index
+ * Get current breakpoint index
+ * On exit:
+ * reg: Breakpoint index
+ */
+ .macro _dbg_getcurrbkpt_index reg
+ ldr \reg, =debug_curr_breakpoint
+ ldr \reg, [\reg]
+ .endm
+
+/* _dbg_setcurrbkpt_index
+ * Set current breakpoint index
+ * On exit:
+ * r1: destroyed
+ */
+ .macro _dbg_setcurrbkpt_index reg
+ ldr r1, =debug_curr_breakpoint
+ str \reg, [r1]
+ .endm
+
+/* _dbg_getabortedinstr_addr
+ * Get aborted instruction address
+ * On exit:
+ * reg: aborted instruction address
+ */
+ .macro _dbg_getabortedinstr_addr reg
+ ldr \reg, =__debugger_stack_bottom__
+ ldr \reg, [\reg]
+ .endm
+
+/* _dbg_setabortedinstr_addr
+ * Set aborted instruction address
+ * On exit:
+ * r1: destroyed
+ */
+ .macro _dbg_setabortedinstr_addr reg
+ ldr r1, =__debugger_stack_bottom__
+ str \reg, [r1]
+ .endm
+
+
+ /*@}*/
+
+#endif /* __DEBUG_MACROS_H__ */
diff --git a/AT91SAM7S256/armdebug/Debugger/debug_runlooptasks.S b/AT91SAM7S256/armdebug/Debugger/debug_runlooptasks.S
new file mode 100644
index 0000000..fd17412
--- /dev/null
+++ b/AT91SAM7S256/armdebug/Debugger/debug_runlooptasks.S
@@ -0,0 +1,87 @@
+/** @file debug_runloop.S
+ * @brief GDB Server platform Run Loop
+ *
+ */
+
+/* Copyright (C) 2007-2011 the NxOS developers
+ *
+ * Module Developed by: TC Wan <tcwan@cs.usm.my>
+ *
+ * See AUTHORS for a full list of the developers.
+ *
+ * See COPYING for redistribution license
+ *
+ */
+
+
+/*
+ * The Debugger has to implement a Run Loop in ABORT mode
+ * since the hardware is still running. Consequently,
+ * the communications subsystems such as USB (and Bluetooth?)
+ * which is used to communicate with the Host needs to be
+ * serviced in order for actual data transmission and reception
+ * to take place. Currently we're reusing the platform's
+ * communication routines to do the actual tx/rx, so it means
+ * that it is not possible to set breakpoints in those modules.
+ * In addition, since the platform communication modules may
+ * handle other tasks, it is currently possible to enter an
+ * indeterminate state where certain communication messages trigger
+ * a platform response which cannot be handled by the Debugger Run Loop.
+ * The alternative is to implement our own communications routines, but
+ * that will take even more code.
+ *
+ * FIXME: It may become necessary to hack the platform communications
+ * routines to detect that we're in the Debugger Run Loop and not the
+ * normal run loop to avoid system crashes, but the current goal is to
+ * have as minimal changes to the platform code as possible.
+ *
+ * Since there are two Run Loops for the platform, the way in which
+ * they interact is as follows:
+ *
+ * [Platform Run Loop] - DBG_INIT/ GDB Cmd/ BKPT -> [Debugger Run Loop]
+ * \ <------ GO/ STEP/ CONT ----- /
+ * ... ...
+ * ... Handle GDB Cmd/Resp
+ * ... ...
+ * {normal runloop {communications /
+ * processing} watchdog routines}
+ * ^-------v v-------^
+ *
+ * The Platform will invoke dbg__bkpt_init() after hardware and system initialization,
+ * before entering the Platform Run Loop. This switches processing over to the
+ * Debugger Run Loop which will wait for the GDB command to Go/Step/Cont before
+ * returning control to the Platform Run Loop.
+ *
+ * Subsequently, Debugger Run Loop will be triggered by Breakpoints, or
+ * when the communications subsystem receives a GDB Command.
+ *
+ * The Debugger Run Loop is actually dbg__bkpt_waitCMD(), this file contains
+ * the Run Loop Tasks which needs to be invoked periodically by the Run Loop,
+ * to minimize the coupling between the ARMDEBUG modules and the Platform.
+ *
+ * Note: The Debugger Run Loop does not handle Hardware Shutdown, it is
+ * assumed that we wouldn't need to do so in Debug Mode.
+ *
+ */
+#define __ASSEMBLY__
+
+ .global dbg__runloopTasks
+
+
+#ifdef __NXOS__
+/* NxOS Run Loop */
+dbg__runloopTasks:
+/* Currently, there's nothing that needs to be done in the NxOS Run Loop */
+ bx lr
+
+#else
+/* NXT Firmware Run Loop */
+ .extern cCommCtrl
+
+dbg__runloopTasks:
+ push {lr}
+ /* FIXME: Add necessary cXXXCtrl calls here */
+ bl cCommCtrl
+ /* OSWatchdogWrite is a NULL function in the NXT Firmware?! */
+ pop {pc}
+#endif
diff --git a/AT91SAM7S256/armdebug/Debugger/debug_stack.ld b/AT91SAM7S256/armdebug/Debugger/debug_stack.ld
new file mode 100644
index 0000000..8fc4cb7
--- /dev/null
+++ b/AT91SAM7S256/armdebug/Debugger/debug_stack.ld
@@ -0,0 +1,15 @@
+/* The following linker definitions should be placed in the stack section */
+
+ /* debugger state */
+ __debugger_stack_bottom__ = . ;
+ . += 0x48; /* 16 previous mode registers + SPSR + UNDEF Next Instruction Address */
+ __debugger_stack__ = .;
+ __debugger_stack_top__ = . ;
+
+ /* breakpoints */
+ __breakpoints_start__ = . ;
+ . += 0x40; /* Single Stepping Breakpoint + 7 Breakpoints */
+ __breakpoints_end__ = . ;
+
+/* Symbols */
+ __breakpoints_num__ = (__breakpoints_end__ - __breakpoints_start__) / 8;
diff --git a/AT91SAM7S256/armdebug/Debugger/debug_stub.S b/AT91SAM7S256/armdebug/Debugger/debug_stub.S
new file mode 100644
index 0000000..f40b6fb
--- /dev/null
+++ b/AT91SAM7S256/armdebug/Debugger/debug_stub.S
@@ -0,0 +1,1817 @@
+/** @file debug_stub.S
+ * @brief ARM Breakpoint Debugger support routines
+ *
+ */
+
+/* Copyright (C) 2007-2011 the NxOS developers
+ *
+ * Module Developed by: TC Wan <tcwan@cs.usm.my>
+ *
+ * See AUTHORS for a full list of the developers.
+ *
+ * See COPYING for redistribution license
+ *
+ */
+
+ /* GDB sparc-stub.c comments header included below to document GDB Server Remote protocol */
+ /* This header has been modified to include additional commands not documented in the header stub */
+
+ /****************************************************************************
+
+ THIS SOFTWARE IS NOT COPYRIGHTED
+
+ HP offers the following for use in the public domain. HP makes no
+ warranty with regard to the software or it's performance and the
+ user accepts the software "AS IS" with all faults.
+
+ HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
+ TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+
+****************************************************************************/
+
+/****************************************************************************
+ * Header: remcom.c,v 1.34 91/03/09 12:29:49 glenne Exp $
+ *
+ * Module name: remcom.c $
+ * Revision: 1.34 $
+ * Date: 91/03/09 12:29:49 $
+ * Contributor: Lake Stevens Instrument Division$
+ *
+ * Description: low level support for gdb debugger. $
+ *
+ * Considerations: only works on target hardware $
+ *
+ * Written by: Glenn Engel $
+ * ModuleState: Experimental $
+ *
+ * NOTES: See Below $
+ *
+ * Modified for SPARC by Stu Grossman, Cygnus Support.
+ *
+ * This code has been extensively tested on the Fujitsu SPARClite demo board.
+ *
+ * To enable debugger support, two things need to happen. One, a
+ * call to set_debug_traps() is necessary in order to allow any breakpoints
+ * or error conditions to be properly intercepted and reported to gdb.
+ * Two, a breakpoint needs to be generated to begin communication. This
+ * is most easily accomplished by a call to breakpoint(). Breakpoint()
+ * simulates a breakpoint by executing a trap #1.
+ *
+ *************
+ *
+ * The following gdb commands are supported:
+ *
+ * command function Return value
+ *
+ * g return the value of the CPU registers hex data or ENN
+ * GrrrrRRRR.. set the value of the CPU registers OK or ENN
+ * where register values are given as
+ * 32-bit hex values in the sequence:
+ * User CPSR, R0, R1, ..., R15
+ * px get the value of one register (x) hex data or ENN
+ * Px=rrrr set the value of one register (x) to OK or ENN
+ * 32-bit hex value rrrr.
+ * x = ['0','F'] for R0-R15, '!' for User CPSR
+ *
+ * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
+ * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
+ *
+ * c Resume at current address SNN ( signal NN)
+ * cAA..AA Continue at address AA..AA SNN
+ *
+ * s Step one instruction SNN
+ * sAA..AA Step one instruction from AA..AA SNN
+ *
+ * k kill
+ *
+ * ? What was the last sigval ? SNN (signal NN)
+ *
+ * zt,AA..AA,k Remove a Breakpoint of type t at addr OK or ENN
+ * AA..AA of kind k
+ * Zt,AA..AA,k Insert a Breakpoint of type t at addr OK or ENN
+ * AA..AA of kind k
+ * t 0: memory breakpoint
+ * 1: hardware breakpoint
+ * 2: write watchpoint
+ * 3: read watchpoint
+ * 4: access watchpoint
+ * k: 2 (16-bit Thumb), 3 (32-bit Thumb2)
+ * or 4 (32-bit ARM) for t=[0,1]
+ * Num. bytes to watch for t=[3,4]
+ *
+ * All commands and responses are sent with a packet which includes a
+ * checksum. A packet consists of
+ *
+ * $<packet info>#<checksum>.
+ *
+ * where
+ * <packet info> :: <characters representing the command or response>
+ * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
+ *
+ * When a packet is received, it is first acknowledged with either '+' or '-'.
+ * '+' indicates a successful transfer. '-' indicates a failed transfer.
+ *
+ * Example:
+ *
+ * Host: Reply:
+ * $m0,10#2a +$00010203040506070809101112131415#42
+ *
+ ****************************************************************************/
+ /* Modified GDB Server Remote Protocol definition from GDB's sparc-stub.c Comment Header included above
+ * Additional commands from GDB Reference Appendix D.2
+ */
+
+#define __ASSEMBLY__
+#include "debug_stub.h"
+#include "debug_macros.h"
+
+/* Macro definitions */
+
+/* _check_msgseparator
+ * Look for separator ','
+ * On entry:
+ * bufferptr: points to the parameter buffer [can't be R0]
+ * On exit:
+ * R0: destroyed
+ * bufferptr: points to the next character location in the parameter buffer
+ * Flags: Updated
+ */
+
+ .macro _check_msgseparator bufferptr
+ ldrb r0, [\bufferptr], #1 /* get separator */
+ cmp r0, #MSGBUF_SEPCHAR
+ .endm
+
+/* _check_msgassignment
+ * Look for assignment '='
+ * On entry:
+ * bufferptr: points to the parameter buffer [can't be R0]
+ * On exit:
+ * R0: destroyed
+ * bufferptr: points to the next character location in the parameter buffer
+ * Flags: Updated
+ */
+
+ .macro _check_msgassignment bufferptr
+ ldrb r0, [\bufferptr], #1 /* get separator */
+ cmp r0, #MSGBUF_SETCHAR
+ .endm
+
+.bss
+.align 4
+debug_state:
+ .word 0x0
+debug_curr_breakpoint:
+ .word 0x0
+debug_InMsgBuf:
+ .space MSGBUF_SIZE,0
+debug_OutMsgBuf:
+ .space MSGBUF_SIZE,0
+
+.data
+.align 4
+debug_ValidResponsePrefix:
+ .byte '+','$',0
+
+debug_ErrorResponsePrefix:
+ .byte '-','$','E',0
+
+debug_SignalResponsePrefix:
+ .byte '+','$','S',0
+
+debug_OkResponse:
+ .byte '+','$','O','K',0
+
+/* The CmdIndexTable and CmdJumpTable must be kept in sync */
+debug_cmdIndexTable:
+ .byte 'g','G','p','P','m','M','c','s','k','z','Z','?',0
+
+/* Command Handlers
+ * On entry:
+ * R0: Input Message Parameter Buffer address pointer (points to contents after '$' and '<cmdchar>')
+ */
+debug_cmdJumpTable:
+ .word _dbg__cmd_GetAllRegs /* 'g' */
+ .word _dbg__cmd_SetAllRegs /* 'G' */
+ .word _dbg__cmd_GetOneReg /* 'p' */
+ .word _dbg__cmd_SetOneReg /* 'P' */
+ .word _dbg__nop /* 'm' */
+ .word _dbg__nop /* 'M' */
+ .word _dbg__nop /* 'c' */
+ .word _dbg__nop /* 's' */
+ .word _dbg__nop /* 'k' */
+ .word _dbg__cmd_remove_breakpoint /* 'z' */
+ .word _dbg__cmd_insert_breakpoint /* 'Z' */
+ .word _dbg__nop /* '?' */
+ .word 0
+
+/*
+ * To determine the next instruction to execute, we need to check current (breakpointed) instruction
+ * and determine whether it will be executed or not. This necessitates a mini instruction decoder
+ * that can check the type of instruction, as well as if it'll affect the PC.
+ * The instruction decoder used here is table based. Each entry in the table consists of:
+ * Instruction Identifier (IID), Instruction Bitmask (IBM), Instruction Handler Address (IHA)
+ * Null entries are placed at the end of the table.
+ *
+ * This allows for a flexible approach to handling instructions that we're interested in, at the expense
+ * of memory usage.
+ *
+ * For ARM, the IID & IBM are both 4 bytes, whereas the Thumb IID & IBM are 2 bytes.
+ * The IHA is always 4 bytes.
+ */
+
+/* ARM Instruction Decode Table
+ * .word IID, IBM, IHA (12 bytes)
+ */
+
+debug_armDecodeTable:
+ .word 0x0000f000, 0x0c00f000, _arm_data_instr_handler /* Data Processing instr with Rd = R15 */
+ .word 0x012fff10, 0x0ffffff0, _arm_bx_blx_handler /* BX or BLX */
+ .word 0x0410f000, 0x0410f000, _arm_ldr_pc_handler /* LDR with Rd = PC */
+/* .word 0x06000010, 0x0e000010, _arm_undef_handler */ /* Undefined instr: shouldn't occur, as it would've been trapped already. See _dbg_next_instruction_addr */
+ .word 0x08108000, 0x0e108000, _arm_ldm_pc_handler /* LDM {pc} */
+ .word 0x0a000000, 0x0e000000, _arm_b_bl_handler /* B or BL. Note v4t does not have BLX instr */
+ .word 0x0c000000, 0x0c000000, _arm_coproc_swi_handler /* Coprocessor instr or SWI */
+ .word 0x0,0x0,0x0 /* Null Entry */
+
+/* Thumb Instruction Decode Table
+ * .hword IID, IBM
+ * .word IHA (8 bytes)
+ */
+
+debug_thumbDecodeTable:
+ .hword 0x4700, 0xff07
+ .word _thumb_bx_blx_handler /* BX or BLX. Note: b7 (H1) is not matched in the mask */
+ .hword 0xbd00, 0xff00
+ .word _thumb_poppc_handler /* PUSH/POP, specifically POP {Rlist,PC} */
+ .hword 0xd000, 0xf000
+ .word _thumb_bcond_swi_handler /* B<cond> or SWI */
+ .hword 0xe000, 0xf800
+ .word _thumb_b_handler /* B */
+ .hword 0xf000, 0xf000
+ .word _thumb_long_b_handler /* Long BL or BLX (4 bytes) Note: b11 (H) indicates 1st or 2nd instr */
+ .hword 0x0,0x0
+ .word 0x0 /* Null Entry */
+
+/* ARM Condition Code Mapping Table
+ * Converts Instruction encoding to SPSR Flags.
+ * b31 b30 b29 b28
+ * N Z C V
+ * Indexed according to Instruction Encoding order (pg 30, Table 6, ATMEL ARM7TDMI Data Sheet)
+ * Condition Code stored in MSN(set), LSN(clr) order
+ * Note1: 0x00 = AL. NV is deprecated, treat as AL
+ * Note2: 0xFF indicates that the condition checks needs to be handled separately (complex checks)
+ *
+ * EQ: Z set
+ * NE: Z clr
+ * HS/CS: C set
+ * LO/CC: C clr
+ * MI: N set
+ * PL: N clr
+ * VS: V set
+ * VC: V clr
+ * HI: C set AND Z clr
+ * LS: C clr AND Z set
+ */
+
+
+debug_armCondCodeTable:
+ /* EQ, NE, HS/CS, LO/CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV */
+ .byte 0x40, 0x04, 0x20, 0x02, 0x80, 0x08, 0x10, 0x01, 0x24, 0x42, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00
+
+/* ARM Complex Condition Code Mapping Table
+ * Converts Instruction encoding to SPSR Flags.
+ * b31 b30 b29 b28
+ * N Z C V
+ * Indexed according to Instruction Encoding order (pg 30, Table 6, ATMEL ARM7TDMI Data Sheet)
+ * for GE, LT, GT and LE instructions only
+ * Condition Code stored in the following order:
+ * b7 b6 b5 b4 b3 b2 b1 b0
+ * - - - ANDOR - Z set AND N==V (bit set = 1)
+ * - - - ANDOR - Z clr OR N!=V (bit clr = 0)
+ *
+ * GE: N == V
+ * LT: N != V
+ * GT: Z clr AND (N == V)
+ * LE: Z set OR (N != V)
+ */
+
+#define COMPLEX_CONDCODE_START 0x0A
+#define COMPLEX_CONDCODE_NEQV_MASK 0x01
+#define COMPLEX_CONDCODE_AND_MASK 0x02
+#define COMPLEX_CONDCODE_ZSET_MASK 0x04
+#define COMPLEX_CONDCODE_ANDOR_MASK 0x10
+
+#define COMPLEX_CONDCODE_NFLAG 0x08
+#define COMPLEX_CONDCODE_ZFLAG 0x04
+#define COMPLEX_CONDCODE_CFLAG 0x02
+#define COMPLEX_CONDCODE_VFLAG 0x01
+
+
+debug_armComplexCCTable:
+ /* GE, LT, GT, LE */
+ .byte 0x01, 0x00, 0x15, 0x12
+
+.code 32
+.text
+.align 4
+ .extern __breakpoints_num__
+ .extern dbg__hasDebugMsg /* Check for message from the communications link */
+ .extern dbg__getDebugMsg /* Read a message from the communications link */
+ .extern dbg__putDebugMsg /* Write a message to the communications link */
+ .extern dbg__runloopTasks /* Platform specific Run Loop processing */
+
+
+/* The Debugger Interface can handle a total of (n-1) Breakpoint States and 1 Single Stepping State,
+ * where n is a power of 2. The value of n is given by __breakpoints_num__ defined in the linker file.
+ *
+ * In addition, a Debugger Stack contains the User Mode Register Stack Frame + SPSR + Bkpt Instr Addr.
+ * These are currently stored in the .stack area in RAM, so there is no fixed address
+ * location that is used for this purpose.
+ *
+ * The Breakpoint feature assumes that the program is executed in RAM. It is not possible
+ * to set dynamic breakpoints for programs executed from Flash in the AT91SAM7S which lacks
+ * instruction breakpointing support in hardware without using JTAG. The only type of breakpoints
+ * that can be supported in Flash based programs are Static (predefined) breakpoints inserted into
+ * the code.
+ *
+ * Each Breakpoint State i is a struct comprising the Breakpoint Address + Memory Contents
+ * stored in 8 bytes as:
+ * [High Memory Address]
+ * ADDR [i*8+4]: Memory Contents (32 bits)
+ * ADDR [i*8]: Breakpoint Address (31 bits, b0 = THUMB flag [not implemented yet])
+ * [Low Memory Address]
+ *
+ * A Non-zero Breakpoint Address means that the breakpoint is active, whereas the memory contents
+ * contains the instruction which resided at that address initially (now replaced by a BKPT <index>
+ * instruction).
+ * Note: Currently it is not possible to resume execution of a program with breakpoints enabled
+ * after a RESET, since the RESET will clear all contents of the stack, destroying the instruction
+ * contained in a given breakpoint.
+ * Fortunately the NXT will also need to reload the program into RAM so this is not expected to be
+ * an issue.
+ *
+ * The Memory Map for the Debugger State is as follows:
+ *
+ * [High Memory Address] __breakpoints_end__
+ * Breakpoint 07 State
+ * Breakpoint 06 State
+ * ...
+ * Breakpoint 02 State
+ * Breakpoint 01 State
+ * Single Step State __debugger_stack__ / __breakpoints_start__
+ * User Mode R15
+ * User Mode R14
+ * ...
+ * User Mode R02
+ * User Mode R01
+ * User Mode R00
+ * User Mode CPSR (UNDEF SPSR)
+ * UNDEF Next Instr Addr __debugger_stack_bottom__
+ * [Low Memory Address]
+ *
+ * Each Breakpoint State will initially be zeroed.
+ *
+ */
+ /* FIXME: The Debugger Stack Frame is probably not 100% consistent with the order that
+ GDB expects in the g/G messages. CSPR is probably located above R15 */
+
+#ifndef __NXOS__
+/****************************************************************************
+ *
+ * GDB Debugger Invocation Routine for NXT Firmware
+ *
+ ****************************************************************************/
+ .code 16
+ .align 2
+ .global cCommHandleDebug
+ .thumb_func
+/* cCommHandleDebug
+ * Switch Mode to Debugger.
+ * Used by NXT Firmware only
+ *
+ * UWORD cCommHandleDebug(UBYTE *pInBuf, UBYTE CmdBit, UWORD MsgLength);
+ *
+ * On Entry, we're in SVC mode. We need to setup the USB Buffers, and switch mode to
+ * ABORT mode to handle the incoming message using a Manual Breakpoint instruction.
+ * When DEBUG is exited, the execution resumes from the instruction following the Breakpoint.
+ */
+cCommHandleDebug:
+ push {r0-r3} /* store all argX registers */
+ bl dbg__copyNxtDebugMsg /* setup Debugger Message Buffers, validate input */
+ pop {r0-r3} /* restore all values */
+ dbg__bkpt_thumb
+ mov r0, #0 /* FIXME: Return Status */
+ bx lr
+#endif
+
+/****************************************************************************
+ *
+ * GDB Debugger Init and Breakpoint Handler Routines
+ *
+ ****************************************************************************/
+ .code 32
+ .align 4
+ .global dbg__bkpt_init
+/* dbg__bkpt_init
+ * GDB set_debug_traps() routine
+ */
+dbg__bkpt_init:
+ push {lr}
+ bl _dbg__clear_breakpoints
+ mov r2, #0
+ ldr r1, =debug_curr_breakpoint
+ str r2, [r1]
+ ldr r0, =debug_InMsgBuf
+ strb r2, [r0]
+ ldr r1, =debug_OutMsgBuf
+ strb r2, [r1]
+ bl dbg__comm_init /* Pass R0: Rx Buffer, R1: Tx Buffer to comm submodule */
+
+/* FIXME: Initialize other stuff here */
+ _dbg_setstate DBG_INIT
+ pop {lr}
+ bx lr /* Must return via BX; may have been called from Thumb mode (NXT Firmware) */
+
+
+/* _dbg__flush_icache
+ * Flush the Instruction cache
+ * Defined by GDB Stub, but not needed for ARMv4T architecture
+ */
+_dbg__flush_icache:
+ /* nop */
+ bx lr
+
+
+ .global dbg__thumb_bkpt_handler
+/* dbg__thumb_bkpt_handler
+ * GDB handle_exception() routine (Thumb Mode)
+ */
+dbg__thumb_bkpt_handler:
+/* On entry, r0 contains breakpoint index value */
+ mov r4, #BKPT16_AUTO_BKPT
+ and r4, r0, #BKPT16_AUTO_BKPT /* keep AUTO flag value in r4 */
+ bic r0, r0, #BKPT16_AUTO_BKPT /* mask out AUTO flag */
+ _dbg_setcurrbkpt_index r0 /* keep current breakpoint index in memory */
+ ldr r1, =BKPT16_MANUAL_BKPT
+ teq r0, r1
+ beq _process_manual_breakpoint_thumb
+ ldr r1, =__breakpoints_num__
+ cmp r0, r1 /* Sanity check that index is in range */
+ bhs dbg__bkpt_offset_outofrange
+/* Valid index value found */
+ teq r4, #0 /* Check if AUTO flag set */
+ bne _process_auto_breakpoint
+/* else */
+ _dbg_setstate DBG_NORMAL_BKPT_THUMB
+ b _process_normal_breakpoint
+
+ .global dbg__arm_bkpt_handler
+/* dbg__arm_bkpt_handler
+ * GDB handle_exception() routine (ARM Mode)
+ */
+dbg__arm_bkpt_handler:
+/* On entry, r0 contains breakpoint index value */
+ mov r4, #BKPT32_AUTO_BKPT
+ and r4, r0, #BKPT32_AUTO_BKPT /* keep AUTO flag value in r4 */
+ bic r0, r0, #BKPT32_AUTO_BKPT /* mask out AUTO flag */
+ _dbg_setcurrbkpt_index r0 /* keep current breakpoint index in memory */
+ ldr r1, =BKPT32_MANUAL_BKPT
+ teq r0, r1
+ beq _process_manual_breakpoint_arm
+ ldr r1, =__breakpoints_num__
+ cmp r0, r1 /* Sanity check that index is in range */
+ bhs dbg__bkpt_offset_outofrange
+/* Valid index value found */
+ teq r4, #0 /* Check if AUTO flag set */
+ bne _process_auto_breakpoint
+/* else */
+ _dbg_setstate DBG_NORMAL_BKPT_ARM
+/* b _process_normal_breakpoint */
+
+_process_normal_breakpoint:
+ bl _dbg__restore_breakpoints
+ bl _dbg__restore_singlestep
+ bl _dbg__clear_singlestep
+ bl _dbg__flush_icache
+ b dbg__bkpt_waitCMD
+
+_process_auto_breakpoint:
+/* Load Auto BKPT for Breakpoint index given in r0 */
+ _index2bkptindex_addr r0, r1 /* Calculate Breakpoint Entry Address */
+ ldm r1, {r1, r2} /* r1: Breakpoint Address, r2: Breakpoint Instruction */
+ teq r1, #0 /* Check that Breakpoint is active */
+ beq dbg__bkpt_inactive
+ bl _dbg__activate_one_breakpoint
+ bl _dbg__restore_singlestep
+ bl _dbg__clear_singlestep
+ b __dbg__resume_execution
+
+_process_manual_breakpoint_thumb:
+ _dbg_setstate DBG_MANUAL_BKPT_THUMB
+ b dbg__bkpt_waitCMD
+
+_process_manual_breakpoint_arm:
+ _dbg_setstate DBG_MANUAL_BKPT_ARM
+/* b dbg__bkpt_waitCMD */
+
+dbg__bkpt_inactive:
+/* b dbg__bkpt_waitCMD */
+
+dbg__bkpt_offset_outofrange:
+/* b dbg__bkpt_waitCMD */
+
+ .global dbg__bkpt_waitCMD
+/* dbg__bkpt_waitCMD
+ * GDB Stub Remote Command Handler
+ */
+
+/****************************************************************************
+ *
+ * GDB Server Command Processing Routines
+ *
+ ****************************************************************************/
+dbg__bkpt_waitCMD:
+ bl dbg__getDebugMsg /* Read new message from Debugger, message buffer length in R0, 0 if none, -1 if error */
+ cmp r0, #0
+ beq _dbg__housekeeping /* No message yet, do housekeeping tasks */
+ movlt r0, #MSG_ERRCHKSUM /* Message invalid, checksum error? */
+ blt _dbg__cmdError /* Send response to GDB server */
+/* Message now has $<packet info>\0 */
+ ldr r4, =debug_msgRxBufPtr
+ ldr r4, [r4] /* Rx buffer Start Address */
+ ldrb r0, [r4], #1 /* Look for '$' */
+ teq r0, #MSGBUF_STARTCHAR
+ movne r0, #MSG_ERRFORMAT /* Message Format invalid (not '$') */
+ bne _dbg__cmdError /* Shouldn't happen */
+ ldrb r0, [r4], #1 /* Look for command char */
+ bl _dbg__cmdChar2Index /* Index in R0 */
+ mov r1, #CMDINDEX_OUTOFRANGE
+ teq r0, r1
+ moveq r0, #MSG_UNKNOWNCMD /* Out of range, Command character not recognized */
+ beq _dbg__cmdError /* Send response to GDB server */
+
+_dbg__cmdExists:
+ mov r3, r0 /* put Command Handler Index in R3 */
+ mov r0, r4 /* R0 now contains Input Message Buffer Parameter Pointer (previously in R4) */
+ _dbg_jumpTableHandler debug_cmdJumpTable, r2, r3 /* Call Command Handler Routine, use R2 as jump address pointer */
+ b dbg__bkpt_waitCMD
+
+_dbg__cmdError:
+ _dbg_outputMsgStatusErr
+ bl dbg__putDebugMsg /* Send error response to the GDB server */
+_dbg__housekeeping:
+ bl dbg__runloopTasks /* Execute platform run loop tasks while in ABRT mode */
+ b dbg__bkpt_waitCMD
+
+
+/* _dbg__cmdChar2Index
+ * Convert Command Character to Jump Table Index
+ * On entry:
+ * r0: command character
+ * On exit:
+ * r0: jump table index (-1 for command not found)
+ * R1: destroyed
+ * R2: destroyed
+ * R3: destroyed
+ */
+_dbg__cmdChar2Index:
+ mov r1, r0 /* Copy command character to r1 */
+ mov r0, #0 /* Clear return value */
+ ldr r3, =debug_cmdIndexTable /* Convert command to index using r3 as Index Lookup Address Pointer */
+1: ldrb r2, [r3, r0] /* Get table entry */
+ teq r2, #0
+ moveq r0, #CMDINDEX_OUTOFRANGE /* End of Index Table, Not found */
+ beq _exit_cmdIndexTable
+ teq r1, r2
+ addne r0, #1 /* Increment Index */
+ bne 1b /* No match, skip to next command char */
+_exit_cmdIndexTable:
+ bx lr
+
+/* __dbg__cmdParamLen
+ * Determines the length of the parameter buffer for a given command
+ * On entry:
+ * R0: parameter buffer pointer (contents after '$' and '<cmdchar>')
+ * On exit:
+ * R0: Address of parameter buffer (preserved)
+ * R1: length
+ */
+__dbg__cmdParamLen:
+ stmfd sp!, {r0,r2,lr} /* R2: scratch register */
+ mov r1, #0
+1: ldrb r2, [r0], #1
+ teq r2, #0
+ addne r1, r1, #1
+ bne 1b
+ ldmfd sp!, {r0,r2,pc}
+
+/* __dbg__procCmdOk
+ * Common subroutine exit stub to return Command Ok Status for Command Handlers
+ * DO NOT CALL THIS STUB DIRECTLY! It Assumes that the return address is in the stack.
+ *
+ */
+__dbg__procCmdOk:
+ _dbg_outputMsgStatusOk
+ bl dbg__putDebugMsg /* Send error response to the GDB server */
+ ldmfd sp!, {pc}
+
+/* __dbg__procCmdParamError
+ * Common subroutine exit stub to handle Command Parameter Error for Command Handlers
+ * DO NOT CALL THIS STUB DIRECTLY! It Assumes that the return address is in the stack.
+ *
+ */
+__dbg__procCmdParamError:
+ _dbg_outputMsgStatusErrCode MSG_UNKNOWNPARAM
+ bl dbg__putDebugMsg /* Send error response to the GDB server */
+ ldmfd sp!, {pc}
+
+
+/* __dbg__procBreakpointAddrError
+ * Common subroutine exit stub to handle Breakpoint Address Error for Breakpoint Insert/Remove Handlers
+ * DO NOT CALL THIS STUB DIRECTLY! It Assumes that the return address is in the stack.
+ *
+ */
+__dbg__procBreakpointAddrError:
+ _dbg_outputMsgStatusErrCode MSG_UNKNOWNBRKPT
+ bl dbg__putDebugMsg /* Send error response to the GDB server */
+ ldmfd sp!, {pc}
+
+
+
+/* _dbg__cmd_GetOneReg
+ * Get One Register Value Command Handler
+ * Valid command parameter x is from '0' to 'F' for User Mode Registers R0-R15
+ * CPSR register is '!'
+ * On entry:
+ * r0: parameter buffer pointer (contents after '$' and '<cmdchar>')
+ * x
+ * On exit:
+ * r0, r1, r2, r3: destroyed
+ *
+ */
+_dbg__cmd_GetOneReg:
+ stmfd sp!, {lr}
+ bl __dbg__cmdParamLen
+ teq r1, #CMD_REG_GETONE_PARAMLEN /* Check for correct length */
+ bne __dbg__procCmdParamError /* Unexpected input, report error */
+ ldrb r0, [r0] /* Load Register index parameter */
+ teq r0, #MSGBUF_CPSRREG /* Check for CPSR register indicator */
+ moveq r0, #DBGSTACK_USERCPSR_OFFSET /* Put offset from User Registers (-1) into index, so that after adjustment it points to CPSR slot */
+ beq _dbg__proc_getRegister /* Handle User CPSR */
+ bl char2hex /* Convert to Hex value (assume input is valid) */
+ cmp r0, #NIBBLE0 /* sanity check, (though it is not foolproof as input char in 0x0-0xF (ctrl-chars) will pass through) */
+ bhi __dbg__procCmdParamError /* Non-hex char, report error */
+
+_dbg__proc_getRegister:
+ mov r3, r0 /* Keep register index safe */
+ _dbg_outputMsgValidResponse /* R0: address of output message buffer data pointer (after response prefix) */
+ mov r1, r3 /* Move register index value to R1 */
+ bl _dbg_outputOneRegValue /* update output buffer */
+ _asciiz r0, r1
+ bl dbg__putDebugMsg /* Send response to the GDB server */
+ ldmfd sp!, {pc}
+
+/* _dbg_outputOneRegValue
+ * Given Register Index (-1: CPSR, 0-F: R0-R15), output hex char to buffer
+ * On entry:
+ * r0: output message buffer pointer
+ * r1: register index (-1, 0-F)
+ * On exit:
+ * r0: updated (points to next character slot at end of Output Buffer)
+ * r1: original output message buffer pointer
+ * r2: destroyed
+ */
+_dbg_outputOneRegValue:
+ stmfd sp!, {lr}
+ add r2, r1, #DBGSTACK_USERREG_INDEX /* Convert register index to Debug Stack index */
+ _getdbgregisterfromindex r2, r1 /* Retrieve Register contents into R1 */
+ bl word2ascii /* Convert and put hex chars into Output Message Buffer */
+ ldmfd sp!, {pc}
+
+/* _dbg__cmd_GetAllRegs
+ * Get All Register Values Command Handler
+ * Output Buffer returns register values in the order: User CPSR, R0, R1, R2, ..., R15
+ * On entry:
+ * r0: parameter buffer pointer (contents after '$' and '<cmdchar>')
+ * <NULL> (no parameters)
+ * On exit:
+ * r0, r1, r2, r3: destroyed
+ */
+_dbg__cmd_GetAllRegs:
+ stmfd sp!, {lr}
+ bl __dbg__cmdParamLen
+ teq r1, #CMD_REG_GETALL_PARAMLEN /* Check for correct length */
+ bne __dbg__procCmdParamError /* Unexpected input, report error */
+
+ _dbg_outputMsgValidResponse /* Setup R1 with address of output message buffer data pointer (after response prefix) */
+ mov r3, #DBGSTACK_USERCPSR_OFFSET /* Output User CPSR Value first */
+1: mov r1, r3
+ bl _dbg_outputOneRegValue /* update output buffer */
+ add r3, r3, #1 /* increment index */
+ cmp r3, #0xF
+ ble 1b /* process all the registers */
+
+ _asciiz r0, r1
+ bl dbg__putDebugMsg /* Send response to the GDB server */
+ ldmfd sp!, {pc}
+
+/* _dbg__cmd_SetOneReg
+ * Set One Register Value Command Handler
+ * Valid command parameter x is from '0' to 'F' for User Mode Registers R0-R15
+ * CPSR register is '!'
+ * On entry:
+ * r0: parameter buffer pointer (contents after '$' and '<cmdchar>')
+ * x=rrrr
+ * On exit:
+ * r0, r1, r2, r3: destroyed
+ *
+ */
+
+_dbg__cmd_SetOneReg:
+ stmfd sp!, {lr}
+ bl __dbg__cmdParamLen
+ teq r1, #CMD_REG_SETONE_PARAMLEN /* Check for correct length */
+ bne __dbg__procCmdParamError /* Unexpected input, report error */
+ mov r3, r0 /* Keep parameter buffer address in R3 */
+ ldrb r1, [r3], #1 /* Load Register index parameter */
+ _check_msgassignment r3
+ bne __dbg__procCmdParamError /* Can't find '=' */
+ mov r0, r1 /* Move register index to R0 for subsequent processing */
+ teq r0, #MSGBUF_CPSRREG /* Check for CPSR register indicator */
+ moveq r0, #DBGSTACK_USERCPSR_OFFSET /* Put offset from User Registers (-1) into index, so that after adjustment it points to CPSR slot */
+ beq _dbg__proc_setRegister /* Handle User CPSR */
+ bl char2hex /* Convert to Hex value (assume input is valid) */
+ cmp r0, #NIBBLE0 /* sanity check, (though it is not foolproof as input char in 0x0-0xF (ctrl-chars) will pass through) */
+ bhi __dbg__procCmdParamError /* Non-hex char, report error */
+
+_dbg__proc_setRegister:
+ add r2, r0, #DBGSTACK_USERREG_INDEX /* Convert register index to Debug Stack index, keep in R2 */
+ mov r0, r3 /* Retrieve parameter buffer pointer */
+ bl ascii2word
+ _setdbgregisterfromindex r2, r0, r3 /* Set Register contents in R0, using index in R2, and scratch register R3 */
+ b __dbg__procCmdOk
+
+/* _dbg__cmd_SetAllReg
+ * Set All Register Values Command Handler
+ * On entry:
+ * r0: parameter buffer pointer (contents after '$' and '<cmdchar>')
+ * rrrrRRRRrrrr... (17 registers)
+ * On exit:
+ * r0, r1, r2, r3: destroyed
+ *
+ */
+_dbg__cmd_SetAllRegs:
+/* FIXME: Assumes that the registers are in the sequence CPSR, R0, R1, ... R15 -- May not be GDB ordering */
+ stmfd sp!, {lr}
+ bl __dbg__cmdParamLen /* R0: pointer to parameters in buffer */
+ teq r1, #CMD_REG_SETALL_PARAMLEN /* Check for correct length */
+ bne __dbg__procCmdParamError /* Unexpected input, report error */
+ mov r2, #DBGSTACK_USERCPSR_INDEX /* R2: register index, starting with CPSR */
+1: bl ascii2word /* R0: value, R1: pointer to next char in buffer */
+ _setdbgregisterfromindex r2, r0, r3 /* Set Register contents in R0, using index in R2, and scratch register R3 */
+ add r2, r2, #1 /* increment index */
+ ldrb r0, [r1]
+ teq r0, #0 /* Look for ASCIIZ character to terminate loop */
+ mov r0, r1 /* setup R0 for next ascii2word call */
+ bne 1b /* continue only if ASCIIZ not found */
+ b __dbg__procCmdOk
+
+/* _dbg__nop
+ * NOP Command Handler (placeholder)
+ * On entry:
+ * r0: parameter buffer (contents after '$' and '<cmdchar>')
+ * On exit:
+ * r0, r1, r2, r3: destroyed
+ */
+_dbg__nop:
+ stmfd sp!, {lr}
+ _dbg_outputMsgStatusErrCode MSG_ERRIMPL /* Stub, not implemented yet */
+ bl dbg__putDebugMsg /* Send error response to the GDB server */
+ ldmfd sp!, {pc}
+
+
+
+/* _dbg__proc_brkpt_params
+ * Process Breakpoint Parameters
+ * On entry:
+ * r0: parameter buffer pointer (contents after '$' and '<cmdchar>')
+ * t,AA..AA,k
+ * On exit:
+ * r0: non-zero = breakpoint address; 0 = parameter error
+ * r1: destroyed
+ * r2: destroyed
+ * r3: destroyed
+ */
+_dbg__proc_brkpt_params:
+ /* FIXME: Add support for watchpoints */
+ stmfd sp!, {lr}
+ mov r3, r0 /* Keep parameter buffer address in R3 */
+ ldrb r0, [r3], #1 /* get breakpoint type t */
+ bl char2hex
+ cmp r0, #CMD_BKPT_TYPE_BREAK_MEMORY
+ bne _dbg__proc_brkpt_params_error /* We only support memory breakpoints for now */
+ _check_msgseparator r3
+ bne _dbg__proc_brkpt_params_error /* Something wrong with the parameters */
+ mov r0, r3 /* Check Address */
+ bl ascii2word /* R0: value, R1: pointer to next char slot */
+ mov r3, r0 /* Keep breakpoint address in R3 */
+ _check_msgseparator r1
+ bne _dbg__proc_brkpt_params_error /* Something wrong with the parameters */
+ ldrb r0, [r1], #1 /* get breakpoint kind k */
+ bl char2hex
+ cmp r0, #CMD_BKPT_KIND_THUMB
+ orreq r3, r3, #1 /* Mark Thumb breakpoints */
+ beq _exit_dbg__proc_brkpt_params
+ cmp r0, #CMD_BKPT_KIND_ARM
+ beq _exit_dbg__proc_brkpt_params /* ARM breakpoint */
+
+_dbg__proc_brkpt_params_error:
+ mov r3, #0 /* Unrecognized breakpoint type */
+_exit_dbg__proc_brkpt_params:
+ mov r0, r3 /* return breakpoint address */
+ ldmfd sp!, {pc}
+
+/* _dbg__cmd_insert_breakpoint
+ * Add Breakpoint
+ * On entry:
+ * r0: parameter buffer pointer (contents after '$' and '<cmdchar>')
+ * t,AA..AA,k
+ * On exit:
+ * r0, r1, r2, r3: destroyed
+ */
+_dbg__cmd_insert_breakpoint:
+ stmfd sp!, {lr}
+ bl __dbg__cmdParamLen
+ teq r1, #CMD_BKPT_INSERT_PARAMLEN /* Check for correct length */
+ bne __dbg__procCmdParamError /* Unexpected input, report error */
+ bl _dbg__proc_brkpt_params /* R0: Breakpoint Address */
+ teq r0, #0
+ beq __dbg__procBreakpointAddrError /* Thumb2 instructions, or unknown kind */
+ mov r3, r0 /* Keep breakpoint address in R3 */
+ mov r0, #0 /* Empty Breakpoint entry */
+ bl _dbg_find_breakpoint_slot /* Look for an available breakpoint slot, return index in R0 */
+ cmp r0, #CMD_BKPT_NOTFOUND
+ beq __dbg__procBreakpointAddrError /* No empty slot! */
+ mov r1, r3 /* Move breakpoint address to R1 */
+ bl _dbg__install_one_breakpoint /* r0: index, r1: instruction address */
+ b __dbg__procCmdOk
+
+/* _dbg__cmd_remove_breakpoint
+ * Remove Breakpoint
+ * On entry:
+ * r0: parameter buffer pointer (contents after '$' and '<cmdchar>')
+ * t,AA..AA,k
+ * On exit:
+ * r0, r1, r2, r3: destroyed
+ */
+_dbg__cmd_remove_breakpoint:
+ stmfd sp!, {lr}
+ bl __dbg__cmdParamLen
+ teq r1, #CMD_BKPT_REMOVE_PARAMLEN /* Check for correct length */
+ bne __dbg__procCmdParamError /* Unexpected input, report error */
+ bl _dbg__proc_brkpt_params /* R0: Breakpoint Address */
+ teq r0, #0
+ beq __dbg__procBreakpointAddrError /* Thumb2 instructions, or unknown kind */
+ bl _dbg_find_breakpoint_slot /* Look for matching breakpoint slot, return index in R0 */
+ cmp r0, #CMD_BKPT_NOTFOUND
+ beq __dbg__procBreakpointAddrError /* Specified Breakpoint not found! */
+ _index2bkptindex_addr r0, r1 /* Calculate Breakpoint Entry Address */
+ mov r0, r1 /* Move it to R0 for subroutine call */
+ bl _dbg__clear_one_breakpoint /* R0: address of breakpoint to clear */
+ b __dbg__procCmdOk
+
+
+/* _dbg__cmd_run
+ * Continue execution of program
+ */
+_dbg__cmd_run:
+ bl _dbg__activate_breakpoints
+ b __dbg__resume_execution
+
+/* _dbg__cmd_step
+ * Single Step execution of program
+ */
+_dbg__cmd_step:
+ bl _dbg_next_instruction_addr /* next instruction address returned in r1 */
+ bl _dbg__install_singlestep /* Setup Single Step */
+ bl _dbg__activate_singlestep
+ b __dbg__resume_execution
+
+/* _dbg__cmd_cont
+ * Continue execution of program.
+ * If this is a Normal Breakpoint, then we need to install an Autobreakpoint at next instruction address
+ * and resume from current (Breakpoint) exception address
+ * Else (it is a Manual Breakpoint)
+ * We need to resume from the next instruction address
+ */
+_dbg__cmd_cont:
+/* FIXME: What happens if we call this when we did not stop at a Breakpoint previously? */
+ _dbg_getstate r0
+ ldr r1, =DBG_MANUAL_BKPT_ARM
+ teq r0, r1
+ beq __dbg_is_manual_breakpoint
+
+ bl _dbg_next_instruction_addr /* next instruction address returned in r1 */
+ bl _dbg__install_singlestep /* Setup Single Step, next instruction address returned in r1 */
+ _dbg_getcurrbkpt_index r0 /* load current breakpoint index in memory */
+ bl _dbg__activate_autobreakpoint /* pass next instruction address in r1 */
+ b __dbg__resume_execution
+
+__dbg_is_manual_breakpoint:
+ bl _dbg_next_instruction_addr /* Skip Manual Breakpoint Instruction(s) */
+ bl _dbg__activate_breakpoints
+ b __dbg__resume_execution
+
+/****************************************************************************
+// Selected Routines from the eCos arm_stub.c related to next instruction address
+// determination in ARM processors.
+
+//========================================================================
+//
+// arm_stub.c
+//
+// Helper functions for stub, generic to all ARM processors
+//
+//========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Red Hat, gthomas
+// Contributors: Red Hat, gthomas, jskov
+// Date: 1998-11-26
+// Purpose:
+// Description: Helper functions for stub, generic to all ARM processors
+// Usage:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+
+static int
+ins_will_execute(unsigned long ins)
+{
+ unsigned long psr = get_register(PS); // condition codes
+ int res = 0;
+ switch ((ins & 0xF0000000) >> 28) {
+ case 0x0: // EQ
+ res = (psr & PS_Z) != 0;
+ break;
+ case 0x1: // NE
+ res = (psr & PS_Z) == 0;
+ break;
+ case 0x2: // CS
+ res = (psr & PS_C) != 0;
+ break;
+ case 0x3: // CC
+ res = (psr & PS_C) == 0;
+ break;
+ case 0x4: // MI
+ res = (psr & PS_N) != 0;
+ break;
+ case 0x5: // PL
+ res = (psr & PS_N) == 0;
+ break;
+ case 0x6: // VS
+ res = (psr & PS_V) != 0;
+ break;
+ case 0x7: // VC
+ res = (psr & PS_V) == 0;
+ break;
+ case 0x8: // HI
+ res = ((psr & PS_C) != 0) && ((psr & PS_Z) == 0);
+ break;
+ case 0x9: // LS
+ res = ((psr & PS_C) == 0) || ((psr & PS_Z) != 0);
+ break;
+ case 0xA: // GE
+ res = ((psr & (PS_N|PS_V)) == (PS_N|PS_V)) ||
+ ((psr & (PS_N|PS_V)) == 0);
+ break;
+ case 0xB: // LT
+ res = ((psr & (PS_N|PS_V)) == PS_N) ||
+ ((psr & (PS_N|PS_V)) == PS_V);
+ break;
+ case 0xC: // GT
+ res = ((psr & (PS_N|PS_V)) == (PS_N|PS_V)) ||
+ ((psr & (PS_N|PS_V)) == 0);
+ res = ((psr & PS_Z) == 0) && res;
+ break;
+ case 0xD: // LE
+ res = ((psr & (PS_N|PS_V)) == PS_N) ||
+ ((psr & (PS_N|PS_V)) == PS_V);
+ res = ((psr & PS_Z) == PS_Z) || res;
+ break;
+ case 0xE: // AL
+ res = TRUE;
+ break;
+ case 0xF: // NV
+ if (((ins & 0x0E000000) >> 24) == 0xA)
+ res = TRUE;
+ else
+ res = FALSE;
+ break;
+ }
+ return res;
+}
+
+static unsigned long
+RmShifted(int shift)
+{
+ unsigned long Rm = get_register(shift & 0x00F);
+ int shift_count;
+ if ((shift & 0x010) == 0) {
+ shift_count = (shift & 0xF80) >> 7;
+ } else {
+ shift_count = get_register((shift & 0xF00) >> 8);
+ }
+ switch ((shift & 0x060) >> 5) {
+ case 0x0: // Logical left
+ Rm <<= shift_count;
+ break;
+ case 0x1: // Logical right
+ Rm >>= shift_count;
+ break;
+ case 0x2: // Arithmetic right
+ Rm = (unsigned long)((long)Rm >> shift_count);
+ break;
+ case 0x3: // Rotate right
+ if (shift_count == 0) {
+ // Special case, RORx
+ Rm >>= 1;
+ if (get_register(PS) & PS_C) Rm |= 0x80000000;
+ } else {
+ Rm = (Rm >> shift_count) | (Rm << (32-shift_count));
+ }
+ break;
+ }
+ return Rm;
+}
+
+// Decide the next instruction to be executed for a given instruction
+static unsigned long *
+target_ins(unsigned long *pc, unsigned long ins)
+{
+ unsigned long new_pc, offset, op2;
+ unsigned long Rn;
+ int i, reg_count, c;
+
+ switch ((ins & 0x0C000000) >> 26) {
+ case 0x0:
+ // BX or BLX
+ if ((ins & 0x0FFFFFD0) == 0x012FFF10) {
+ new_pc = (unsigned long)get_register(ins & 0x0000000F);
+ return ((unsigned long *)new_pc);
+ }
+ // Data processing
+ new_pc = (unsigned long)(pc+1);
+ if ((ins & 0x0000F000) == 0x0000F000) {
+ // Destination register is PC
+ if ((ins & 0x0FBF0000) != 0x010F0000) {
+ Rn = (unsigned long)get_register((ins & 0x000F0000) >> 16);
+ if ((ins & 0x000F0000) == 0x000F0000) Rn += 8; // PC prefetch!
+ if ((ins & 0x02000000) == 0) {
+ op2 = RmShifted(ins & 0x00000FFF);
+ } else {
+ op2 = ins & 0x000000FF;
+ i = (ins & 0x00000F00) >> 8; // Rotate count
+ op2 = (op2 >> (i*2)) | (op2 << (32-(i*2)));
+ }
+ switch ((ins & 0x01E00000) >> 21) {
+ case 0x0: // AND
+ new_pc = Rn & op2;
+ break;
+ case 0x1: // EOR
+ new_pc = Rn ^ op2;
+ break;
+ case 0x2: // SUB
+ new_pc = Rn - op2;
+ break;
+ case 0x3: // RSB
+ new_pc = op2 - Rn;
+ break;
+ case 0x4: // ADD
+ new_pc = Rn + op2;
+ break;
+ case 0x5: // ADC
+ c = (get_register(PS) & PS_C) != 0;
+ new_pc = Rn + op2 + c;
+ break;
+ case 0x6: // SBC
+ c = (get_register(PS) & PS_C) != 0;
+ new_pc = Rn - op2 + c - 1;
+ break;
+ case 0x7: // RSC
+ c = (get_register(PS) & PS_C) != 0;
+ new_pc = op2 - Rn +c - 1;
+ break;
+ case 0x8: // TST
+ case 0x9: // TEQ
+ case 0xA: // CMP
+ case 0xB: // CMN
+ break; // PC doesn't change
+ case 0xC: // ORR
+ new_pc = Rn | op2;
+ break;
+ case 0xD: // MOV
+ new_pc = op2;
+ break;
+ case 0xE: // BIC
+ new_pc = Rn & ~op2;
+ break;
+ case 0xF: // MVN
+ new_pc = ~op2;
+ break;
+ }
+ }
+ }
+ return ((unsigned long *)new_pc);
+ case 0x1:
+ if ((ins & 0x02000010) == 0x02000010) {
+ // Undefined!
+ return (pc+1);
+ } else {
+ if ((ins & 0x00100000) == 0) {
+ // STR
+ return (pc+1);
+ } else {
+ // LDR
+ if ((ins & 0x0000F000) != 0x0000F000) {
+ // Rd not PC
+ return (pc+1);
+ } else {
+ Rn = (unsigned long)get_register((ins & 0x000F0000) >> 16);
+ if ((ins & 0x000F0000) == 0x000F0000) Rn += 8; // PC prefetch!
+ if (ins & 0x01000000) {
+ // Add/subtract offset before
+ if ((ins & 0x02000000) == 0) {
+ // Immediate offset
+ if (ins & 0x00800000) {
+ // Add offset
+ Rn += (ins & 0x00000FFF);
+ } else {
+ // Subtract offset
+ Rn -= (ins & 0x00000FFF);
+ }
+ } else {
+ // Offset is in a register
+ if (ins & 0x00800000) {
+ // Add offset
+ Rn += RmShifted(ins & 0x00000FFF);
+ } else {
+ // Subtract offset
+ Rn -= RmShifted(ins & 0x00000FFF);
+ }
+ }
+ }
+ return ((unsigned long *)*(unsigned long *)Rn);
+ }
+ }
+ }
+ return (pc+1);
+ case 0x2: // Branch, LDM/STM
+ if ((ins & 0x02000000) == 0) {
+ // LDM/STM
+ if ((ins & 0x00100000) == 0) {
+ // STM
+ return (pc+1);
+ } else {
+ // LDM
+ if ((ins & 0x00008000) == 0) {
+ // PC not in list
+ return (pc+1);
+ } else {
+ Rn = (unsigned long)get_register((ins & 0x000F0000) >> 16);
+ if ((ins & 0x000F0000) == 0x000F0000) Rn += 8; // PC prefetch!
+ offset = ins & 0x0000FFFF;
+ reg_count = 0;
+ for (i = 0; i < 15; i++) {
+ if (offset & (1<<i)) reg_count++;
+ }
+ if (ins & 0x00800000) {
+ // Add offset
+ Rn += reg_count*4;
+ } else {
+ // Subtract offset
+ Rn -= 4;
+ }
+ return ((unsigned long *)*(unsigned long *)Rn);
+ }
+ }
+ } else {
+ // Branch
+ if (ins_will_execute(ins)) {
+ offset = (ins & 0x00FFFFFF) << 2;
+ if (ins & 0x00800000) offset |= 0xFC000000; // sign extend
+ new_pc = (unsigned long)(pc+2) + offset;
+ // If its BLX, make new_pc a thumb address.
+ if ((ins & 0xFE000000) == 0xFA000000) {
+ if ((ins & 0x01000000) == 0x01000000)
+ new_pc |= 2;
+ new_pc = MAKE_THUMB_ADDR(new_pc);
+ }
+ return ((unsigned long *)new_pc);
+ } else {
+ // Falls through
+ return (pc+1);
+ }
+ }
+ case 0x3: // Coprocessor & SWI
+ if (((ins & 0x03000000) == 0x03000000) && ins_will_execute(ins)) {
+ // SWI
+ return (unsigned long *)(CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT * 4);
+ } else {
+ return (pc+1);
+ }
+ default:
+ // Never reached - but fixes compiler warning.
+ return 0;
+ }
+}
+
+// FIXME: target_ins also needs to check for CPSR/THUMB being set and
+// set the thumb bit accordingly.
+
+static unsigned long
+target_thumb_ins(unsigned long pc, unsigned short ins)
+{
+ unsigned long new_pc = MAKE_THUMB_ADDR(pc+2); // default is fall-through
+ // to next thumb instruction
+ unsigned long offset, arm_ins, sp;
+ int i;
+
+ switch ((ins & 0xf000) >> 12) {
+ case 0x4:
+ // Check for BX or BLX
+ if ((ins & 0xff07) == 0x4700)
+ new_pc = (unsigned long)get_register((ins & 0x00078) >> 3);
+ break;
+ case 0xb:
+ // push/pop
+ // Look for "pop {...,pc}"
+ if ((ins & 0xf00) == 0xd00) {
+ // find PC
+ sp = (unsigned long)get_register(SP);
+
+ for (offset = i = 0; i < 8; i++)
+ if (ins & (1 << i))
+ offset += 4;
+
+ new_pc = *(cyg_uint32 *)(sp + offset);
+
+ if (!v5T_semantics())
+ new_pc = MAKE_THUMB_ADDR(new_pc);
+ }
+ break;
+ case 0xd:
+ // Bcc | SWI
+ // Use ARM function to check condition
+ arm_ins = ((unsigned long)(ins & 0x0f00)) << 20;
+ if ((arm_ins & 0xF0000000) == 0xF0000000) {
+ // SWI
+ new_pc = CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT * 4;
+ } else if (ins_will_execute(arm_ins)) {
+ offset = (ins & 0x00FF) << 1;
+ if (ins & 0x0080) offset |= 0xFFFFFE00; // sign extend
+ new_pc = MAKE_THUMB_ADDR((unsigned long)(pc+4) + offset);
+ }
+ break;
+ case 0xe:
+ // check for B
+ if ((ins & 0x0800) == 0) {
+ offset = (ins & 0x07FF) << 1;
+ if (ins & 0x0400) offset |= 0xFFFFF800; // sign extend
+ new_pc = MAKE_THUMB_ADDR((unsigned long)(pc+4) + offset);
+ }
+ break;
+ case 0xf:
+ // BL/BLX (4byte instruction!)
+ // First instruction (bit 11 == 0) holds top-part of offset
+ if ((ins & 0x0800) == 0) {
+ offset = (ins & 0x07FF) << 12;
+ if (ins & 0x0400) offset |= 0xFF800000; // sign extend
+ // Get second instruction
+ // Second instruction (bit 11 == 1) holds bottom-part of offset
+ ins = *(unsigned short*)(pc+2);
+ // Check for BL/BLX
+ if ((ins & 0xE800) == 0xE800) {
+ offset |= (ins & 0x07ff) << 1;
+ new_pc = (unsigned long)(pc+4) + offset;
+ // If its BLX, force a full word alignment
+ // Otherwise, its a thumb address.
+ if (!(ins & 0x1000))
+ new_pc &= ~3;
+ else
+ new_pc = MAKE_THUMB_ADDR(new_pc);
+ }
+ }
+ break;
+ }
+
+ return new_pc;
+}
+
+void __single_step (void)
+{
+ unsigned long pc = get_register(PC);
+ unsigned long cpsr = get_register(PS);
+
+ // Calculate address of next instruction to be executed
+ if (cpsr & CPSR_THUMB_ENABLE) {
+ // thumb
+ ss_saved_pc = target_thumb_ins(pc, *(unsigned short*)pc);
+ } else {
+ // ARM
+ unsigned long curins = *(unsigned long*)pc;
+ if (ins_will_execute(curins)) {
+ // Decode instruction to decide what the next PC will be
+ ss_saved_pc = (unsigned long) target_ins((unsigned long*)pc,
+ curins);
+ } else {
+ // The current instruction will not execute (the conditions
+ // don't hold)
+ ss_saved_pc = pc+4;
+ }
+ }
+
+ // Set breakpoint according to type
+ if (IS_THUMB_ADDR(ss_saved_pc)) {
+ // Thumb instruction
+ unsigned long t_pc = UNMAKE_THUMB_ADDR(ss_saved_pc);
+ ss_saved_thumb_instr = *(unsigned short*)t_pc;
+ *(unsigned short*)t_pc = HAL_BREAKINST_THUMB;
+ } else {
+ // ARM instruction
+ ss_saved_instr = *(unsigned long*)ss_saved_pc;
+ *(unsigned long*)ss_saved_pc = HAL_BREAKINST_ARM;
+ }
+}
+
+ ****************************************************************************/
+
+
+/* _dbg_next_instruction_addr
+ * Determine the address of the next instruction to execute.
+ * On exit:
+ * R1: Instruction Address (31 bits, b0 = THUMB flag)
+ *
+ * Here we make use of the Debugger Stack which contains the address of the aborted instruction that will be reexecuted
+ * when we resume the program.
+ *
+ * If it is a Manual Breakpoint inserted into the code, then we will need to update the aborted instruction
+ * address to skip the current aborted instruction and resume execution at the next instruction address,
+ * and the next instruction address to be returned to the calling routine is the following instruction
+ * address instead.
+ *
+ * We need to check the aborted instruction type, to see if it is a branch instruction, before we can determine
+ * the next instruction address (for inserting a Breakpoint).
+ */
+_dbg_next_instruction_addr:
+/* We assume that any BKPT instructions in the code will be Manual Breakpoints,
+ * i.e., the Debugger does not leave stray Single Step / Auto / Normal breakpoints in memory
+ */
+
+ mov r2, #DBGSTACK_USERCPSR_INDEX /* Retrieve User CPSR */
+ _getdbgregisterfromindex r2, r0 /* Retrieve Register contents into R0 */
+ and r4, r0, #CPSR_THUMB /* store Thumb Mode status in R4 */
+ mov r5, r0, lsr #28 /* store CPSR condition flags in R5[3:0] */
+
+ _dbg_getabortedinstr_addr r2 /* Retrieve aborted instruction address */
+1: teq r4, #0 /* Check if it is ARM or Thumb instruction */
+ ldrneh r0, [r2]
+ ldrne r1, =(BKPT16_INSTR | BKPT16_MANUAL_BKPT) /* check for Thumb Manual Breakpoint Instruction */
+ ldreq r0, [r2]
+ ldreq r1, =(BKPT32_INSTR | BKPT32_MANUAL_BKPT) /* check for ARM Manual Breakpoint Instruction */
+ teq r0, r1
+ bne 2f /* Not Manual breakpoint */
+ teq r4, #0 /* Check if it is ARM or Thumb instruction */
+ addne r2, r2, #2 /* Is Manual Breakpoint, Skip to next Thumb instruction */
+ addeq r2, r2, #4 /* Is Manual Breakpoint, Skip to next ARM instruction */
+ _dbg_setabortedinstr_addr r2 /* Update aborted instruction address */
+ b 1b /* To protect against a sequence of Manual Breakpoint Instructions */
+
+/* Here, r0 contains the instruction which will be reexecuted when program resumes. We need to dissect it to see if
+ * it is a branch instruction.
+ * For ARM instructions, we also need to evaluate the current (breakpointed) instruction to see if it'll execute.
+ * If not, then the next instruction is the instruction following the current instruction.
+ */
+2:
+ /* Use R6 to store candidate next instruction address */
+ teq r4, #0 /* Check if it is ARM or Thumb instruction */
+ beq _next_instr_is_arm
+_next_instr_is_thumb:
+ add r6, r2, #2 /* set next Thumb instruction address */
+ /*_is_thumb_branch_instr r0 */ /* check if the current instruction is a branch instruction */
+_next_instr_is_arm:
+ add r6, r2, #4 /* Is ARM, set next ARM instruction address */
+@@@@@@@@@
+ bx lr
+
+/* __dbg__resume_execution
+ * cleanup, resume execution of program.
+ * Restore User Mode Regsiters from Debugger Stack, and resume execution from aborted instruction
+ */
+__dbg__resume_execution:
+@@@@@@
+ bl _dbg__flush_icache
+ b __dbg__resume_execution
+
+/****************************************************************************
+ *
+ * Instruction Decode Routines
+ *
+ ****************************************************************************/
+
+/* _dbg_check_arm_condcode
+ * Check ARM conditional execution code
+ * On entry:
+ * R0: instruction to be executed
+ * R5[3:0]: CPSR condition codes
+ * On exit:
+ * R0: will_execute (boolean)
+ */
+
+_dbg_check_arm_condcode:
+ stmfd sp!, {r6,lr} /* Use R6 as temporary will_execute variable */
+ mov r6, #TRUE
+ mov r0, r0, lsr #28 /* convert condition code to index (0-F) */
+ ldr r2, =debug_armCondCodeTable
+ ldrb r1, [r2, r0] /* Get condition code mask */
+/*
+ * The following check is unnecessary as it is covered by the set/clear checking algorithm
+ teq r1, #0
+ beq _dbg_check_arm_condcode_exit
+*/
+ teq r1, #0xFF
+ bne _dbg_check_bits_set
+
+
+/*
+ * Complex Checks:
+ *
+ * will_execute = TRUE [default condition]
+ * If (N == V) bit set
+ * will_execute = (N == V)
+ * else
+ * will_execute = (N != V)
+ *
+ * If (ANDOR bit) set
+ * z_cond = ((Z XOR Z set) == 0)
+ * If (AND bit set)
+ * will_execute = will_execute && z_cond
+ * else
+ * will_execute = will_execute || z_cond
+ */
+_dbg_cond_complex_check:
+ sub r1, r0, #COMPLEX_CONDCODE_START /* Convert complex condition code to new index (0-3) */
+ ldr r2, =debug_armComplexCCTable
+ ldrb r1, [r2, r1] /* Get complex condition code bitmap */
+
+ /* Use r2 to store N, r3 to store V */
+ tst r5, #COMPLEX_CONDCODE_NFLAG
+ moveq r2, #FALSE
+ movne r2, #TRUE /* r2 = N flag */
+ tst r5, #COMPLEX_CONDCODE_VFLAG
+ moveq r3, #FALSE
+ movne r3, #TRUE /* r3 = V flag */
+ eor r2, r2, r3 /* r2 = (N xor V): 0 if equal, 0xFF if not equal */
+ tst r1, #COMPLEX_CONDCODE_NEQV_MASK
+ mvnne r6, r1 /* If (N == V) bit set, will_execute (r6) = TRUE if (N == V) [r2 == 0] -> invert r2 */
+ moveq r6, r1 /* else (N == V) bit clr, will_execute (r6) = TRUE if (N != V) [r2 == 0xFF] */
+
+ tst r1, #COMPLEX_CONDCODE_ANDOR_MASK
+ beq _dbg_check_arm_condcode_exit /* No additional checks needed, exit */
+
+ /* Use r2 to store Z, r3 to store Z set */
+ and r2, r5, #COMPLEX_CONDCODE_ZFLAG /* r2 = Z flag */
+ and r3, r1, #COMPLEX_CONDCODE_ZSET_MASK /* r3 = Z set */
+ eors r2, r2, r3 /* r2 = (Z xor Z set): 0 if matched, non-zero if not matched */
+ moveq r2, #TRUE
+ movne r2, #FALSE /* r2 (z_cond): TRUE if matched, FALSE if not matched */
+
+ tst r1, #COMPLEX_CONDCODE_AND_MASK
+ andne r6, r6, r2 /* If AND bit set, will_execute = will_execute && z_cond */
+ orreq r6, r6, r2 /* else, will_execute = will_execute || z_cond */
+ b _dbg_check_arm_condcode_exit
+
+
+/*
+ * Simple Checks:
+ *
+ * will_execute = TRUE [default condition, equivalent to 0x00 (AL) ]
+ * If (SetBitMask is Non-Zero)
+ * will_execute = ((cond_code & SetBitMask) == SetBitMask)
+ * If will_execute && (ClearBitMask is Non-Zero)
+ * will_execute = will_execute && ((cond_code | ~ClearBitMask) == ~ClearBitMask)
+ */
+
+_dbg_check_bits_set:
+ movs r0, r1, lsr #4 /* R0: bits set */
+ beq _dbg_check_bits_clear
+ and r2, r5, r0 /* Check bits set IF bitmask non-zero */
+ teq r2, r0 /* ((cond_code & SetBitMask) == SetBitMask)? */
+ movne r6, #FALSE /* No, so will_execute = FALSE */
+ bne _dbg_check_arm_condcode_exit
+
+_dbg_check_bits_clear:
+ ands r1, r1, #NIBBLE0 /* R1: bits clear */
+ beq _dbg_check_arm_condcode_exit
+ mvn r1, r1 /* Invert Bitmask */
+ orr r2, r5, r1 /* Check bits clear IF bitmask non-zero */
+ teq r2, r1 /* ((cond_code | ~ClearBitMask) == ~ClearBitMask)? */
+ movne r6, #FALSE /* No, so will_execute = FALSE */
+ bne _dbg_check_arm_condcode_exit
+
+
+_dbg_check_arm_condcode_exit:
+ mov r0, r6 /* Update return value */
+ ldmfd sp!, {r6, pc}
+
+
+_arm_data_instr_handler: /* Data Processing instr with Rd = R15 */
+_arm_bx_blx_handler: /* BX or BLX */
+_arm_ldr_pc_handler: /* LDR with Rd = PC */
+_arm_ldm_pc_handler: /* LDM {pc} */
+_arm_b_bl_handler: /* B or BL. Note v4t does not have BLX instr */
+_arm_coproc_swi_handler: /* Coprocessor instr or SWI */
+ bx lr
+
+_thumb_bx_blx_handler: /* BX or BLX. Note: b7 (H1) is not matched in the mask */
+_thumb_poppc_handler: /* PUSH/POP, specifically POP {Rlist,PC} */
+_thumb_bcond_swi_handler: /* B<cond> or SWI */
+_thumb_b_handler: /* B */
+_thumb_long_b_handler: /* Long BL or BLX (4 bytes) Note: b11 (H) indicates 1st or 2nd instr */
+ bx lr
+
+
+/****************************************************************************
+ *
+ * Breakpoint Manipulation Routines
+ *
+ ****************************************************************************/
+/* _dbg_find_breakpoint_slot
+ * Find the matching Breakpoint Slot.
+ * This is both used to find empty slots (pass R0=0x0000) or
+ * occupied slots (pass R0=<brkpt addr>)
+ *
+ * On Entry:
+ * R0: Breakpoint Address
+ * On Exit:
+ * R0: Matching Index (-1: not found)
+ *
+ * NOTE: This routine performs exact match, i.e., breakpoint address MUST be configured
+ * for ARM or Thumb (bit 0 clear/set) as appropriate
+ */
+
+_dbg_find_breakpoint_slot:
+ stmfd sp!, {r1,r2,r3, lr}
+ mov r1, #1 /* Only consider Breakpoints 1-7 */
+ ldr r3, =__breakpoints_num__
+1:
+ _index2bkptindex_addr r1, r2 /* Calculate Breakpoint Entry Address */
+ ldr r2, [r2] /* Get actual breakpoint entry (instruction address) */
+ cmp r0, r2
+ beq _found_breakpoint_slot
+ add r1, r1, #1 /* no match, check next */
+ cmp r1, r3
+ blo 1b /* continue checking only if we don't exceed __breakpoints_num__ */
+
+_notfound_breakpoint_slot:
+ mov r1, #CMD_BKPT_NOTFOUND
+_found_breakpoint_slot:
+ mov r0, r1 /* Return value in R0 */
+ ldmfd sp!, {r1,r2,r3, pc}
+
+/* _dbg__clear_singlestep
+ * Clear the Single Step Breakpoint
+ */
+_dbg__clear_singlestep:
+ ldr r0, =__breakpoints_start__ /* Single Step Breakpoint is at the beginning of the Breakpoint State Struct */
+/* b _dbg__clear_one_breakpoint */
+
+/* _dbg__clear_one_breakpoint
+ * On entry, R0 contains the Breakpoint State slot address to be cleared
+ *
+ */
+_dbg__clear_one_breakpoint:
+ mov r1, #0
+ mov r2, #0
+ stmea r0!, {r1, r2} /* clear Breakpoint state */
+ bx lr
+
+/* _dbg__clear_breakpoints
+ * Routine iterates through the array of breakpoints (incl single step breakpoint) and clears the breakpoint
+ */
+_dbg__clear_breakpoints:
+ stmfd sp!, {lr}
+ ldr r0, =__breakpoints_start__ /* Single Step Breakpoint is at the beginning of the Breakpoint State Struct */
+ ldr r3, =__breakpoints_end__ /* start from top of the table */
+3: bl _dbg__clear_one_breakpoint
+ cmp r0, r3
+ blo 3b
+ ldmfd sp!, {pc}
+
+/* _dbg__install_singlestep
+ * Install the Single Step Breakpoint
+ * On entry:
+ * R1: Instruction Address (31 bits, b0 = THUMB flag)
+ */
+_dbg__install_singlestep:
+ mov r0, #0
+/* b _dbg__install_one_breakpoint */
+
+/* _dbg__install_one_breakpoint
+ * Install breakpoint entry into Breakpoint State Table
+ * On entry:
+ * R0: Breakpoint index (assumed valid)
+ * R1: Instruction Address (31 bits, b0 = THUMB flag)
+ *
+ * On exit:
+ * R2: Breakpoint Instruction
+ * R3: Breakpoint Entry address
+ */
+_dbg__install_one_breakpoint:
+/* Check for Thumb bit */
+ tst r1, #BKPT_STATE_THUMB_FLAG /* 1: Thumb instruction */
+/* Assume that the address entry is valid, otherwise we should sanitize it (mask out b1) */
+ ldreq r2, [r1] /* if 0: load ARM instruction from address location */
+ ldrneh r2, [r1] /* else load Thumb instruction */
+ _index2bkptindex_addr r0, r3 /* Calculate Breakpoint Entry Address */
+ stm r3, {r1, r2}
+ bx lr
+
+
+/* _dbg__restore_singlestep
+ * Restores the contents of the single step breakpoint to memory
+ */
+_dbg__restore_singlestep:
+ mov r0, #0 /* single step breakpoint index */
+ _index2bkptindex_addr r0, r1 /* Calculate Single Step Breakpoint Entry Address */
+ ldm r1, {r1, r2} /* r1: Breakpoint Address, r2: Breakpoint Instruction */
+ teq r1, #0
+ bxeq lr /* Exit if not active */
+/* b _dbg__restore_one_breakpoint */
+
+/* _dbg__restore_one_breakpoint
+ * Restores the contents to memory for one breakpoint
+ * On entry:
+ * R0: Breakpoint index (assumed valid) [not used -- can be used for validating BKPT]
+ * R1: Breakpoint Address (assumed valid)
+ * R2: Breakpoint Instruction (assumed valid)
+ */
+_dbg__restore_one_breakpoint:
+/* Check for Thumb bit */
+ tst r1, #BKPT_STATE_THUMB_FLAG /* 1: Thumb instruction */
+/* Assume that the address entry is valid, otherwise we should sanitize it (mask out b1) */
+ streq r2, [r1] /* if 0: restore ARM instruction to address location */
+ bicne r1, #BKPT_STATE_THUMB_FLAG /* else, clear Thumb Flag */
+ strneh r2, [r1] /* store Thumb instruction */
+ bx lr
+
+/* _dbg__restore_breakpoints
+ * Routine iterates through the array of breakpoints (incl single step breakpoint) and restores the contents to memory
+ * Only Active breakpoints (i.e., Non-zero Address) are processed.
+ */
+_dbg__restore_breakpoints:
+ stmfd sp!, {lr}
+ ldr r5, =_dbg__restore_one_breakpoint
+ b __dbg__iterate_breakpoint_array
+
+/* _dbg__activate_singlestep
+ * Activate the single step breakpoint to memory
+ */
+_dbg__activate_singlestep:
+ mov r0, #0 /* single step breakpoint index */
+ _index2bkptindex_addr r0, r1 /* Calculate Single Step Breakpoint Entry Address */
+ ldm r1, {r1, r2} /* r1: Breakpoint Address, r2: Breakpoint Instruction */
+ teq r1, #0
+ bxeq lr /* Exit if not active */
+/* b _dbg__activate_one_breakpoint */
+
+/* _dbg__activate_one_breakpoint
+ * Activate one breakpoint to memory
+ * On entry:
+ * R0: Breakpoint index (assumed valid)
+ * R1: Breakpoint Address (assumed valid)
+ * R2: Breakpoint Instruction (assumed valid)
+ */
+_dbg__activate_one_breakpoint:
+/* Check for Thumb bit */
+ tst r1, #BKPT_STATE_THUMB_FLAG /* 1: Thumb instruction */
+ bne _nx_is_thumb_bp
+_nx_is_arm_bp:
+/* Assume that the address entry is valid, otherwise we should sanitize it (mask out b1) */
+ ldr r3, [r1] /* if 0: load ARM instruction from address location */
+ teq r2, r3 /* check that the two instructions are identical */
+ bne _dbg__breakpoint_invalid_arm
+ ldr r2, =BKPT32_INSTR /* ARM BKPT instruction */
+ and r2, r2, r0 /* Merge Breakpoint index */
+ str r2, [r1] /* Store it into memory location */
+_dbg__breakpoint_invalid_arm:
+ bx lr
+_nx_is_thumb_bp:
+ bic r1, #BKPT_STATE_THUMB_FLAG /* else, clear Thumb Flag */
+ ldrh r3, [r1] /* load Thumb instruction from address location */
+ teq r2, r3 /* check that the two instructions are identical */
+ bne _dbg__breakpoint_invalid_thumb
+ ldr r2, =BKPT16_INSTR /* Thumb BKPT instruction */
+ and r2, r2, r0 /* Merge Breakpoint index */
+ strh r2, [r1] /* Store it into memory location */
+_dbg__breakpoint_invalid_thumb:
+ bx lr
+
+/* _dbg__activate_breakpoints
+ * Routine iterates through the array of breakpoints (incl single step breakpoint) and activates them
+ * Only Active breakpoints (i.e., Non-zero Address) are processed.
+ */
+_dbg__activate_breakpoints:
+ stmfd sp!, {lr}
+ ldr r5, =_dbg__activate_one_breakpoint
+ b __dbg__iterate_breakpoint_array
+
+
+/* __dbg__iterate_breakpoint_array
+ * Common routine iterates through the array of breakpoints (incl single step breakpoint)
+ * and executes routine given in R5, passing:
+ * R0: Breakpoint index
+ * R1: Breakpoint Address
+ * R2: Breakpoint Instruction
+ *
+ * On Entry:
+ * Assumes that lr has been push to stack (routine can't be called directly)
+ *
+ * Only Active breakpoints (i.e., Non-zero Address entries) are processed.
+ */
+__dbg__iterate_breakpoint_array:
+ ldr r4, =__breakpoints_end__ /* start from top of the table (Assume __breakpoints_end__ > __breakpoints_start__) */
+ ldr r3, =__breakpoints_start__ /* end address check */
+ ldr r0, =__breakpoints_num__ /* Number of Breakpoints (incl Single Step) (Assume Non-Zero) */
+4: sub r0, r0, #1 /* Decrement breakpoint index in r0 */
+ ldmea r4!, {r1, r2} /* r1: Breakpoint Address, r2: Breakpoint Instruction */
+ teq r1, #0 /* Is it active? */
+ movne lr, pc
+ bxne r5 /* active entry */
+ cmp r4, r3
+ bhi 4b /* if (pointer > start of Breakpoint Table address), get next slot */
+ ldmfd sp!, {pc}
+
+/* _dbg__activate_autobreakpoint
+ * Activate all other breakpoints except current breakpoint, activate auto breakpoint in next instr slot
+ * On entry:
+ * R0: Current Breakpoint index (assumed valid)
+ * R1: Next Instruction address (for AUTO Breakpoint) [Not used, assume Single Step Breakpoint already has correct info]
+ */
+_dbg__activate_autobreakpoint:
+ stmfd sp!, {lr}
+ mov r5, r0 /* Keep Current Breakpoint Index in r5 */
+ ldr r4, =__breakpoints_end__ /* start from top of the table */
+ ldr r0, =__breakpoints_num__ /* Number of Breakpoints (incl Single Step) (Assume Non-Zero) */
+4: subs r0, r0, #1 /* Decrement breakpoint index in r0 */
+ ldmea r4!, {r1, r2} /* r1: Breakpoint Address, r2: Breakpoint Instruction */
+ bls 5f /* Flag set by subs instruction previously. Reached Single Step, go activate AUTO Breakpoint */
+ teq r0, r5 /* Is it the Current Breakpoint? */
+ beq 4b /* Yes, so skip */
+ teq r1, #0 /* Is it active? */
+ blne _dbg__activate_one_breakpoint /* active entry */
+ b 4b /* Next iteration */
+5:
+/* Here, r1: Breakpoint Address, r2: Breakpoint Instruction */
+ tst r1, #BKPT_STATE_THUMB_FLAG /* Check for Thumb bit -- 1: Thumb instruction */
+ orreq r0, r5, #BKPT32_AUTO_BKPT /* Is ARM Instruction, merge AUTO flag with Current Breakpoint Index */
+ orrne r0, r5, #BKPT16_AUTO_BKPT /* Is Thumb Instruction, merge AUTO flag with Current Breakpoint Index */
+ bl _dbg__activate_one_breakpoint /* Activate AUTO Breakpoint */
+ ldmfd sp!, {pc}
+
diff --git a/AT91SAM7S256/armdebug/Debugger/debug_stub.h b/AT91SAM7S256/armdebug/Debugger/debug_stub.h
new file mode 100644
index 0000000..1c47050
--- /dev/null
+++ b/AT91SAM7S256/armdebug/Debugger/debug_stub.h
@@ -0,0 +1,299 @@
+/** @file debug_stub.h
+ * @brief Shared C/ASM header file for debugger stub
+ *
+ */
+
+/* Copyright (C) 2007-2010 the NxOS developers
+ *
+ * Module Developed by: TC Wan <tcwan@cs.usm.my>
+ *
+ * See AUTHORS for a full list of the developers.
+ *
+ * See COPYING for redistribution license
+ *
+ */
+
+#ifndef __DEBUG_STUB_H__
+#define __DEBUG_STUB_H__
+
+#include "_c_arm_macros.h"
+
+
+/** @addtogroup debugger */
+/*@{*/
+
+
+/* Declarations go here. */
+/** @name Debug Message Constants.
+ *
+ * Debug Message Values
+ */
+/*@{*/
+
+/*
+ * USB Buffer Sizes: Ctrl Intr Iso Bulk
+ * Full Speed Device 64 64 1023 64
+ * High Speed Device 64 1024 1024 512
+ */
+
+#define USB_BUFSIZE 64 /* USB Buffer size for AT91SAM7S */
+
+#define USB_NXT_TELEGRAMTYPE_OFFSET 0 /* NXT Direct Command/Response Header */
+#define USB_NXT_SEGNUM_OFFSET 1
+#define USB_NXT_TELEGRAMSIZE_OFFSET 2
+
+#define USB_NXT_TELEGRAMTYPE 0x8d /* GDB debugger specific, no Response required */
+
+#define USB_GDBMSG_START 3 /* Offset into USB Telegram buffer */
+
+#define MSG_NUMSEGMENTS 3 /* For packet transfers */
+#define MSG_SEGMENTSIZE (USB_BUFSIZE - USB_GDBMSG_START) /* 61 bytes per segment */
+#define MSGBUF_SIZE (MSG_SEGMENTSIZE*MSG_NUMSEGMENTS) /* Debug Message Buffer Size, 61 x 3 = 183 chars = ~80 bytes of actual data */
+#define MSGBUF_CHKSUMOFFSET 3 /* to be subtracted from message length */
+
+#define MSGBUF_CTRLC 0x03 /* For Out of Band Signaling: not implemented yet */
+#define MSGBUF_STARTCHAR '$'
+#define MSGBUF_ACKCHAR '+'
+#define MSGBUF_NAKCHAR '-'
+#define MSGBUF_ERRCHAR 'E'
+#define MSGBUF_SIGCHAR 'S'
+#define MSGBUF_CPSRREG '!'
+#define MSGBUF_SETCHAR '='
+#define MSGBUF_CHKSUMCHAR '#'
+#define MSGBUF_SEPCHAR ','
+#define MSGBUF_MSGERROR -1
+/*@}*/
+
+/** @name Debug Command Lookup Constants.
+ *
+ * Debug Command Lookup
+ */
+/*@{*/
+
+#define CMDINDEX_OUTOFRANGE -1
+/*@}*/
+
+/** @name Debug Register Command Constants.
+ *
+ * Debug Register Command
+ */
+/*@{*/
+#define CMD_REG_NUMREGS 17
+#define CMD_REG_GETONE_PARAMLEN 1
+#define CMD_REG_GETALL_PARAMLEN 0
+#define CMD_REG_SETONE_PARAMLEN 6
+#define CMD_REG_SETALL_PARAMLEN (CMD_REG_NUMREGS*4)
+
+
+/*@}*/
+
+/** @name Debug Breakpoint Command Constants.
+ *
+ * Debug Breakpoint Command
+ */
+/*@{*/
+
+#define CMD_BKPT_INSERT_PARAMLEN 12
+#define CMD_BKPT_REMOVE_PARAMLEN 12
+
+
+#define CMD_BKPT_TYPE_BREAK_MEMORY 0
+#define CMD_BKPT_TYPE_BREAK_HARD 1 /* Not supported */
+#define CMD_BKPT_TYPE_WATCH_WRITE 2 /* Not supported (yet) */
+#define CMD_BKPT_TYPE_WATCH_READ 3 /* Not supported (yet) */
+#define CMD_BKPT_TYPE_WATCH_ACCESS 4 /* Not supported (yet) */
+
+#define CMD_BKPT_KIND_THUMB 2
+#define CMD_BKPT_KIND_THUMB2 3 /* Not supported */
+#define CMD_BKPT_KIND_ARM 4
+
+#define CMD_BKPT_NOTFOUND -1
+
+/*@}*/
+
+/** @name Debug Stack Constants.
+ *
+ * Debug Stack Manipulation Values
+ */
+/*@{*/
+#define DBGSTACK_USERCPSR_OFFSET (DBGSTACK_USERCPSR_INDEX-DBGSTACK_USERREG_INDEX) /* = -1, offset for calculating Debug Stack index */
+#define DBGSTACK_USERCPSR_INDEX 1 /* User CPSR (SPSR_UNDEF) is at index 1 from bottom of Debug Stack */
+#define DBGSTACK_USERREG_INDEX 2 /* R0 starts at index 2 from bottom of Debug Stack */
+/*@}*/
+
+/** @name Bitmask Definitions.
+ *
+ * Various Bitmasks used for data manipulation.
+ */
+/*@{*/
+#define BKPT_STATE_THUMB_FLAG 0x01 /* Flag Thumb Breakpoint */
+#define ASCII_LOWER2UPPER_MASK 0x20 /* ASCII Conversion bitmask */
+#define NIBBLE0 0x0000000F /* Nibble 0 word(3:0) */
+#define NIBBLE1 0x000000F0 /* Nibble 1 word(7:4) */
+#define NIBBLE2 0x00000F00 /* Nibble 2 word(11:8) */
+#define NIBBLE3 0x0000F000 /* Nibble 3 word(15:12) */
+#define NIBBLE4 0x000F0000 /* Nibble 4 word(19:16) */
+#define NIBBLE5 0x00F00000 /* Nibble 5 word(23:20) */
+#define NIBBLE6 0x0F000000 /* Nibble 6 word(27:24) */
+#define NIBBLE7 0xF0000000 /* Nibble 7 word(31:28) */
+#define BYTE0 0x000000FF /* Byte 0 word(7:0) */
+#define BYTE1 0x0000FF00 /* Byte 1 word(15:8) */
+#define BYTE2 0x00FF0000 /* Byte 2 word(23:16) */
+#define BYTE3 0xFF000000 /* Byte 3 word(31:24) */
+#define HLFWRD0 0x0000FFFF /* Halfword 0 word(15:0) */
+#define HLFWRD1 0xFFFF0000 /* Halfword 0 word(31:16) */
+/*@}*/
+
+/** @name CPSR Bit Definitions.
+ *
+ * Various Bit definitions for accessing the CPSR register.
+ */
+/*@{*/
+#define CPSR_THUMB 0x00000020
+#define CPSR_FIQ 0x00000040
+#define CPSR_IRQ 0x00000080
+#define CPSR_MODE 0x0000001F
+
+/*@}*/
+
+/** @name BKPT suppport constants
+ *
+ * ARM and Thumb Breakpoint Instructions.
+ */
+/*@{*/
+
+#define __ARM6OR7__
+
+#ifdef __ARM6OR7__
+#define BKPT32_INSTR 0xE7200070 /* ARM6 and ARM7 does not trap unused opcodes (BKPT overlap with control instructions), \
+ CPU has unpredictable behavior. Ref: Steve Furber, ARM SoC Architecture 2nd Ed, pg. 143 */
+#else
+#define BKPT32_INSTR 0xE1200070 /* ARM BKPT instruction, will work in ARMv5T and above */
+#endif
+
+#define BKPT32_ENUM_MASK 0x000FFF0F /* ARM BKPT Enum Mask */
+#define BKPT32_AUTO_BKPT 0x00080000 /* ARM BKPT Auto-Step Flag (for CONT support) */
+#define BKPT32_MANUAL_BKPT 0x0007FF0F /* Manually inserted ARM Breakpoint */
+
+#define BKPT16_INSTR 0xBE00 /* Thumb BKPT instruction */
+#define BKPT16_ENUM_MASK 0x00FF /* Thumb BKPT Enum Mask */
+#define BKPT16_AUTO_BKPT 0x0080 /* Thumb BKPT Auto-Step Flag (for CONT support) */
+#define BKPT16_MANUAL_BKPT 0x007F /* Manually inserted Thumb Breakpoint */
+/*@}*/
+
+/** Debugger State Enums
+ *
+ * Debugger State.
+ * The enums must be consecutive, starting from 0
+ */
+ENUM_BEGIN
+ENUM_VALASSIGN(DBG_RESET, 0) /**< Initial State. */
+ENUM_VAL(DBG_INIT) /**< Debugger Initialized. */
+ENUM_VAL(DBG_MANUAL_BKPT_ARM) /**< Manual ARM Breakpoint. */
+ENUM_VAL(DBG_NORMAL_BKPT_ARM) /**< Normal ARM Breakpoint (Single Step, Normal). */
+ENUM_VAL(DBG_MANUAL_BKPT_THUMB) /**< Manual Thumb Breakpoint. */
+ENUM_VAL(DBG_NORMAL_BKPT_THUMB) /**< Normal Thumb Breakpoint (Single Step, Normal). */
+ENUM_END(dbg_state_t)
+
+/** Debugger Message Error Enums
+ *
+ * Debugger Error Message Enums.
+ * The enums must be consecutive, starting from 1
+ */
+ENUM_BEGIN
+ENUM_VALASSIGN(MSG_ERRIMPL, 0) /**< Stub (not implemented) Error. */
+ENUM_VAL(MSG_ERRCHKSUM) /**< Checksum Error. */
+ENUM_VAL(MSG_ERRFORMAT) /**< Message Format Error. */
+ENUM_VAL(MSG_UNKNOWNCMD) /**< Unrecognized Command Error. */
+ENUM_VAL(MSG_UNKNOWNPARAM) /**< Unrecognized Parameter Error. */
+ENUM_VAL(MSG_UNKNOWNBRKPT) /**< Unrecognized Breakpoint Error. */
+ENUM_END(dbg_msg_errno)
+
+
+#ifndef __ASSEMBLY__
+
+/* Define C stuff */
+/** @defgroup debug_public */
+/*@{*/
+
+
+/** Initialize Debugger.
+ * Equivalent to GDB set_debug_traps() routine
+ */
+FUNCDEF void dbg__bkpt_init(void);
+
+#ifndef __NXOS__
+/** Switch Mode to Debugger.
+ * Used by NXT Firmware only
+ */
+FUNCDEF UWORD cCommHandleDebug(UBYTE *pInBuf, UBYTE CmdBit, UWORD MsgLength);
+#endif
+
+/** Debugger Handler Routine (called by Exception Handler Trap).
+ * Equivalent to GDB handle_exception() routine
+ */
+FUNCDEF void dbg__bkpt_handler(void);
+
+/** dbg_breakpoint_arm.
+ * Equivalent to GDB breakpoint() routine for ARM code
+ */
+/* FUNCDEF void dbg_breakpoint_arm(void); */
+static inline void dbg_breakpoint_arm(void)
+{
+ asm volatile (".word %a0"
+ : /* Output (empty) */
+ : "X" (BKPT32_INSTR | BKPT32_MANUAL_BKPT)
+ );
+}
+
+#if 0 /* Old asm definitions, in case gas does not recognize %a0 operand */
+
+#ifdef __ARM6OR7__
+static inline void dbg_breakpoint_arm(void) { asm volatile (".word 0xE727FF7F" /* (BKPT32_INSTR | BKPT32_MANUAL_BKPT) */ ); }
+#else
+static inline void dbg_breakpoint_arm(void) { asm volatile (".word 0xE127FF7F" /* (BKPT32_INSTR | BKPT32_MANUAL_BKPT) */ ); }
+#endif
+
+#endif
+
+/** dbg_breakpoint_thumb.
+ * Equivalent to GDB breakpoint() routine for Thumb code
+ */
+/* FUNCDEF void dbg_breakpoint_thumb(void); */
+static inline void dbg_breakpoint_thumb(void)
+{
+ asm volatile (".hword %a0"
+ : /* Output (empty) */
+ : "X" (BKPT16_INSTR | BKPT16_MANUAL_BKPT)
+ );
+}
+
+#if 0 /* Old asm definitions, in case gas does not recognize %a0 operand */
+
+static inline void dbg_breakpoint_thumb(void) { asm volatile (".hword 0xBE7F" /* (BKPT16_INSTR | BKPT16_MANUAL_BKPT) */); }
+
+#endif
+
+/*@}*/
+
+#else
+/* Define Assembly stuff */
+
+/* dbg__bkpt_arm
+ * GDB breakpoint() for ARM mode
+ */
+ .macro dbg__bkpt_arm
+ .word (BKPT32_INSTR | BKPT32_MANUAL_BKPT)
+ .endm
+
+/* dbg__bkpt_arm
+ * GDB breakpoint() for Thumb mode
+ */
+ .macro dbg__bkpt_thumb
+ .hword (BKPT16_INSTR | BKPT16_MANUAL_BKPT)
+ .endm
+
+#endif
+ /*@}*/
+
+#endif /* __DEBUG_STUB_H__ */
diff --git a/AT91SAM7S256/armdebug/Debugger/debug_test.S b/AT91SAM7S256/armdebug/Debugger/debug_test.S
new file mode 100644
index 0000000..91e19d2
--- /dev/null
+++ b/AT91SAM7S256/armdebug/Debugger/debug_test.S
@@ -0,0 +1,53 @@
+/** @file debug_test.S
+ * @brief Test Routines to trigger ARM and Thumb Manual Breakpoints
+ *
+ */
+
+/* Copyright (C) 2007-2011 the NxOS developers
+ *
+ * Module Developed by: TC Wan <tcwan@cs.usm.my>
+ *
+ * See AUTHORS for a full list of the developers.
+ *
+ * See COPYING for redistribution license
+ *
+ */
+#define __ASSEMBLY__
+#include "debug_stub.h"
+
+.text
+.align 4
+.code 32
+
+/**********************************************
+ * dbg__test_arm_bkpt Test Routine
+ *
+ */
+ .global dbg__test_arm_bkpt
+dbg__test_arm_bkpt:
+ stmfd sp!,{lr}
+ dbg__bkpt_arm /* Trigger ARM Manual Breakpoint */
+ ldmfd sp!,{pc}
+
+/**********************************************
+ * dbg__test_thumb_bkpt Test Routine
+ *
+ */
+ .global dbg__test_thumb_bkpt
+dbg__test_thumb_bkpt:
+ stmfd sp!,{lr}
+/* ldr r0, =_thumb_entry
+ orr r0, r0, #1 @ Set Thumb mode
+ mov lr, pc
+ bx r0
+*/
+ bl _thumb_entry
+ ldmfd sp!,{pc}
+
+.code 16
+.thumb_func
+_thumb_entry:
+ dbg__bkpt_thumb
+ bx lr
+
+.end
diff --git a/AT91SAM7S256/armdebug/Debugger/debug_test.h b/AT91SAM7S256/armdebug/Debugger/debug_test.h
new file mode 100644
index 0000000..6680f58
--- /dev/null
+++ b/AT91SAM7S256/armdebug/Debugger/debug_test.h
@@ -0,0 +1,35 @@
+/** @file debug_test.h
+ * @brief C header file for debugger test routines
+ *
+ */
+
+/* Copyright (C) 2007-2010 the NxOS developers
+ *
+ * Module Developed by: TC Wan <tcwan@cs.usm.my>
+ *
+ * See AUTHORS for a full list of the developers.
+ *
+ * See COPYING for redistribution license
+ *
+ */
+
+#ifndef __DEBUG_TEST_H__
+#define __DEBUG_TEST_H__
+
+#include "_c_arm_macros.h"
+
+#ifndef __ASSEMBLY__
+
+/* Define C stuff */
+/** @defgroup debug_public */
+/*@{*/
+
+FUNCDEF void dbg__test_arm_bkpt(void);
+FUNCDEF void dbg__test_thumb_bkpt(void);
+
+ /*@}*/
+
+#endif
+
+
+#endif /* __DEBUG_TEST_H__ */
diff --git a/AT91SAM7S256/armdebug/Debugger/undef_handler.S b/AT91SAM7S256/armdebug/Debugger/undef_handler.S
new file mode 100644
index 0000000..6923d4d
--- /dev/null
+++ b/AT91SAM7S256/armdebug/Debugger/undef_handler.S
@@ -0,0 +1,111 @@
+
+/* Copyright (C) 2007-2010 the NxOS developers
+ *
+ * Module Developed by: TC Wan <tcwan@cs.usm.my>
+ *
+ * See AUTHORS for a full list of the developers.
+ *
+ * Redistribution of this file is permitted under
+ * the terms of the GNU Public License (GPL) version 2.
+ */
+#define __ASSEMBLY__
+#include "debug_stub.h"
+
+#define MODE_USR 0x10 /* User mode */
+#define MODE_FIQ 0x11 /* FIQ mode */
+#define MODE_IRQ 0x12 /* IRQ mode */
+#define MODE_SVC 0x13 /* Supervisor mode */
+#define MODE_ABT 0x17 /* Abort mode */
+#define MODE_UND 0x1B /* Undefined mode */
+#define MODE_SYS 0x1F /* System mode */
+
+.text
+.code 32
+.align 0
+
+ .extern dbg__thumb_bkpt_handler
+ .extern dbg__arm_bkpt_handler
+ .extern default_undef_handler
+
+ .global undef_handler
+
+undef_handler:
+/* Remote GDB Debugger relies on BKPT instruction being trapped here
+ * In ARMv4t, it is an Illegal (Undefined) Instruction.
+ * On triggering, lr (R14) contains the previous mode's pc (R15).
+ * Based on example in Hohl, "ARM Assembly Language: Fundamentals and Techniques"
+ * Chapter 11, Example 11.1.
+ * Note: The handler is not AAPCS compliant (8 byte-alignment and stack, etc.)
+ */
+ /* We assume that the UNDEF stack holds only one stack frame and we will overwrite it.
+ * On entry, LR_undef points to one instruction past the UNDEF instruction.
+ *
+ * For the purpose of Debugging, the stack frame should present the PC (R15) as the address
+ * of the instruction that triggered the Breakpoint. Hence we need to adjust R15
+ * to point to the address of the UNDEF instruction. This is what the JTAG debugger
+ * does. (In the ARM hardware, the PC would point to UNDEF+2 instruction address
+ * since it has a three stage pipeline).
+ *
+ * We will also store UNDEF LR (next instruction pointer) and UNDEF SPSR to the stack.
+ *
+ * For the handler, once the user registers have been stored in the debug stack, the
+ * registers will be used as follows:
+ *
+ * R0: UNDEF LR, then UNDEF instruction address, finally UNDEF instruction word / BKPT index
+ * R1: SPSR
+ * R2: Mode
+ * R3: Debug Stack Pointer (for Banked R13-R14 update)
+ */
+ ldr sp, =__debugger_stack__
+ stmfd sp, {r0-r15}^ /* Save workspace, previous mode's pc via 'S' flag, R13-R15: placeholders */
+ mov r3, sp /* Use R3 to write Banked R13-R14, and actual PC of UNDEF instruction */
+ sub sp, sp, #(4*16) /* Need to manually update SP(undef) */
+
+ mov r0, lr /* Keep Next Instruction address after UNDEF instruction in R0 */
+ mrs r1, spsr /* Copy SPSR to r1 */
+ stmfd sp!, {r0,r1} /* Save User's Next Instr Pointer (in UNDEF LR) and previous mode's CPSR to stack */
+
+ tst r1, #CPSR_THUMB /* Check for Thumb Mode */
+ subne r0, r0, #2 /* Is Thumb instruction, adjust PC for UNDEF instruction address */
+ subeq r0, r0, #4 /* Is ARM instruction, adjust PC for UNDEF instruction address */
+ str r0, [r3, #-4]! /* Save PC to stack (R15 slot) */
+
+ and r2, r1, #CPSR_MODE /* Get previous mode */
+ teq r2, #MODE_USR
+ beq _skip_banked_registers /* Can't switch back if we're in User mode! */
+
+_store_prev_mode_banked_regs:
+ /* FIXME: We don't handle FIQ properly! */
+
+ orr r2, #(CPSR_FIQ | CPSR_IRQ) /* Disable Interrupts */
+ msr cpsr_c, r2 /* Switch to previous mode */
+ stmfd r3!, {sp, lr} /* Store Previous Mode's LR (R14), SP (R13) via R3 */
+ msr cpsr_c, #(MODE_UND | CPSR_FIQ | CPSR_IRQ) /* Revert to Undef Mode */
+
+_skip_banked_registers:
+ tst r1, #CPSR_THUMB /* Check for Thumb Mode */
+ beq _is_arm /* Clear, so it's ARM mode */
+_is_thumb:
+ ldrh r0, [r0] /* load UNDEF instruction into r0 */
+ ldr r1, =BKPT16_ENUM_MASK /* Thumb BKPT enum mask */
+ bic r2, r0, r1 /* leave only opcode */
+ ldr r1, =BKPT16_INSTR /* check for Thumb Breakpoint Instruction */
+ teq r2, r1
+ bne default_undef_handler
+ ldr r1, =BKPT16_ENUM_MASK /* get Thumb BKPT Enum Mask */
+ b _exit_undef_handler
+_is_arm:
+ ldr r0, [r0] /* load UNDEF instruction into r0 */
+ ldr r1, =BKPT32_ENUM_MASK /* ARM BKPT enum mask */
+ bic r2, r0, r1 /* leave only opcode */
+ ldr r1, =BKPT32_INSTR /* check for ARM Breakpoint Instruction */
+ teq r2, r1
+ bne default_undef_handler
+ ldr r1, =BKPT32_ENUM_MASK /* get ARM BKPT Enum Mask */
+_exit_undef_handler:
+ and r0, r1, r0 /* Keep index value */
+ msr cpsr_c, #(MODE_ABT) /* Configure Abort Mode */
+ ldr lr, =dbg__arm_bkpt_handler /* handle BKPT, BKPT index in r0 */
+ mov pc, lr /* Invoke Debugger State (Supervisor Mode) */
+
+