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authorNicolas Schodet2010-06-13 17:49:42 +0200
committerNicolas Schodet2010-08-19 23:24:12 +0200
commit495cc1df494505378977995eeb76b05f20f0b235 (patch)
treef7c52ae59cad0e96f1aff1736d31cb8624676812 /AT91SAM7S256/SAM7S256
parentba78bd9ba834260d035a9830726afc34fdad2a15 (diff)
import firmware from LEGO v1.29lego-1.29lego
Diffstat (limited to 'AT91SAM7S256/SAM7S256')
-rw-r--r--AT91SAM7S256/SAM7S256/Include/AT91SAM7S64.h1920
-rw-r--r--AT91SAM7S256/SAM7S256/Include/AT91SAM7S64_inc.h1710
-rw-r--r--AT91SAM7S256/SAM7S256/Include/Board.h89
-rw-r--r--AT91SAM7S256/SAM7S256/Include/DLib_Defaults.h685
-rw-r--r--AT91SAM7S256/SAM7S256/Include/Dlib_Product.h8
-rw-r--r--AT91SAM7S256/SAM7S256/Include/ctype.h169
-rw-r--r--AT91SAM7S256/SAM7S256/Include/ioat91sam7s64.h3307
-rw-r--r--AT91SAM7S256/SAM7S256/Include/lib_at91sam7s64.h3664
-rw-r--r--AT91SAM7S256/SAM7S256/Include/math.h647
-rw-r--r--AT91SAM7S256/SAM7S256/Include/sam7s256.c6
-rw-r--r--AT91SAM7S256/SAM7S256/Include/sam7s256.h21
-rw-r--r--AT91SAM7S256/SAM7S256/Include/stdbool.h28
-rw-r--r--AT91SAM7S256/SAM7S256/Include/stdio.h240
-rw-r--r--AT91SAM7S256/SAM7S256/Include/stdlib.h337
-rw-r--r--AT91SAM7S256/SAM7S256/Include/string.h409
-rw-r--r--AT91SAM7S256/SAM7S256/Include/time.h90
-rw-r--r--AT91SAM7S256/SAM7S256/Include/wchar.h339
-rw-r--r--AT91SAM7S256/SAM7S256/Include/xencoding_limits.h55
-rw-r--r--AT91SAM7S256/SAM7S256/Include/xlocale.h130
-rw-r--r--AT91SAM7S256/SAM7S256/Include/xlocale_c.h107
-rw-r--r--AT91SAM7S256/SAM7S256/Include/xlocaleuse.h180
-rw-r--r--AT91SAM7S256/SAM7S256/Include/xmtx.h41
-rw-r--r--AT91SAM7S256/SAM7S256/Include/xtinfo.h68
-rw-r--r--AT91SAM7S256/SAM7S256/Include/xtls.h188
-rw-r--r--AT91SAM7S256/SAM7S256/Include/ymath.h91
-rw-r--r--AT91SAM7S256/SAM7S256/Include/ysizet.h37
-rw-r--r--AT91SAM7S256/SAM7S256/Include/yvals.h549
-rw-r--r--AT91SAM7S256/SAM7S256/Lib/dl4tptinl8n.h9
-rw-r--r--AT91SAM7S256/SAM7S256/Lib/dl4tptinl8n.r79bin0 -> 1149147 bytes
-rw-r--r--AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.d79bin0 -> 46113 bytes
-rw-r--r--AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.mac143
-rw-r--r--AT91SAM7S256/SAM7S256/Tools/LMS_V02.dep3943
-rw-r--r--AT91SAM7S256/SAM7S256/Tools/LMS_V02.ewd1354
-rw-r--r--AT91SAM7S256/SAM7S256/Tools/LMS_V02.ewp2531
-rw-r--r--AT91SAM7S256/SAM7S256/Tools/LMS_V02.eww10
-rw-r--r--AT91SAM7S256/SAM7S256/Tools/at91SAM7S256_64KRAM.xcl136
-rw-r--r--AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.dbgdt96
-rw-r--r--AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.dni33
-rw-r--r--AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.wsdt49
39 files changed, 23413 insertions, 6 deletions
diff --git a/AT91SAM7S256/SAM7S256/Include/AT91SAM7S64.h b/AT91SAM7S256/SAM7S256/Include/AT91SAM7S64.h
new file mode 100644
index 0000000..45db24d
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/AT91SAM7S64.h
@@ -0,0 +1,1920 @@
+// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name : AT91SAM7S64.h
+// Object : AT91SAM7S64 definitions
+// Generated : AT91 SW Application Group 02/23/2005 (17:06:07)
+//
+// CVS Reference : /AT91SAM7S64.pl/1.18/Wed Feb 9 15:26:02 2005//
+// CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005//
+// CVS Reference : /MC_SAM7S.pl/1.2/Tue Feb 1 17:01:00 2005//
+// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005//
+// CVS Reference : /RSTC_SAM7S.pl/1.1/Tue Feb 1 16:16:35 2005//
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
+// CVS Reference : /UDP_6083C.pl/1.1/Mon Jan 31 13:01:46 2005//
+// CVS Reference : /AIC_6075A.pl/1.1/Fri Jun 28 10:36:48 2002//
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference : /SPI_6088D.pl/1.2/Mon Feb 14 07:24:18 2005//
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference : /TC_6082A.pl/1.6/Fri Feb 18 13:53:30 2005//
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference : /PWM_6044D.pl/1.1/Tue Apr 27 14:53:52 2004//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7S64_H
+#define AT91SAM7S64_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved2[45]; //
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved3[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved4[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved5[54]; //
+ AT91_REG PIOA_PER; // PIO Enable Register
+ AT91_REG PIOA_PDR; // PIO Disable Register
+ AT91_REG PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved6[1]; //
+ AT91_REG PIOA_OER; // Output Enable Register
+ AT91_REG PIOA_ODR; // Output Disable Registerr
+ AT91_REG PIOA_OSR; // Output Status Register
+ AT91_REG Reserved7[1]; //
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved8[1]; //
+ AT91_REG PIOA_SODR; // Set Output Data Register
+ AT91_REG PIOA_CODR; // Clear Output Data Register
+ AT91_REG PIOA_ODSR; // Output Data Status Register
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
+ AT91_REG PIOA_IER; // Interrupt Enable Register
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
+ AT91_REG PIOA_ISR; // Interrupt Status Register
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved9[1]; //
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved10[1]; //
+ AT91_REG PIOA_ASR; // Select A Register
+ AT91_REG PIOA_BSR; // Select B Register
+ AT91_REG PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved11[9]; //
+ AT91_REG PIOA_OWER; // Output Write Enable Register
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
+ AT91_REG PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved12[469]; //
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved16[3]; //
+ AT91_REG PMC_PCKR[3]; // Programmable Clock Register
+ AT91_REG Reserved17[5]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved18[36]; //
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved19[5]; //
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+ AT91_REG Reserved20[5]; //
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG CKGR_PLLR; // PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved3[3]; //
+ AT91_REG PMC_PCKR[3]; // Programmable Clock Register
+ AT91_REG Reserved4[5]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+ AT91_REG MC_RCR; // MC Remap Control Register
+ AT91_REG MC_ASR; // MC Abort Status Register
+ AT91_REG MC_AASR; // MC Abort Address Status Register
+ AT91_REG Reserved0[21]; //
+ AT91_REG MC_FMR; // MC Flash Mode Register
+ AT91_REG MC_FCR; // MC Flash Command Register
+ AT91_REG MC_FSR; // MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+ AT91_REG ADC_CR; // ADC Control Register
+ AT91_REG ADC_MR; // ADC Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
+ AT91_REG ADC_SR; // ADC Status Register
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
+ AT91_REG Reserved1[44]; //
+ AT91_REG ADC_RPR; // Receive Pointer Register
+ AT91_REG ADC_RCR; // Receive Counter Register
+ AT91_REG ADC_TPR; // Transmit Pointer Register
+ AT91_REG ADC_TCR; // Transmit Counter Register
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+ AT91_REG SSC_CR; // Control Register
+ AT91_REG SSC_CMR; // Clock Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
+ AT91_REG SSC_RHR; // Receive Holding Register
+ AT91_REG SSC_THR; // Transmit Holding Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG SSC_SR; // Status Register
+ AT91_REG SSC_IER; // Interrupt Enable Register
+ AT91_REG SSC_IDR; // Interrupt Disable Register
+ AT91_REG SSC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved3[44]; //
+ AT91_REG SSC_RPR; // Receive Pointer Register
+ AT91_REG SSC_RCR; // Receive Counter Register
+ AT91_REG SSC_TPR; // Transmit Pointer Register
+ AT91_REG SSC_TCR; // Transmit Counter Register
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+ AT91_REG TWI_CR; // Control Register
+ AT91_REG TWI_MMR; // Master Mode Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG TWI_IADR; // Internal Address Register
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
+ AT91_REG Reserved1[3]; //
+ AT91_REG TWI_SR; // Status Register
+ AT91_REG TWI_IER; // Interrupt Enable Register
+ AT91_REG TWI_IDR; // Interrupt Disable Register
+ AT91_REG TWI_IMR; // Interrupt Mask Register
+ AT91_REG TWI_RHR; // Receive Holding Register
+ AT91_REG TWI_THR; // Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+ AT91_REG PWMC_CMR; // Channel Mode Register
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
+ AT91_REG PWMC_CPRDR; // Channel Period Register
+ AT91_REG PWMC_CCNTR; // Channel Counter Register
+ AT91_REG PWMC_CUPDR; // Channel Update Register
+ AT91_REG PWMC_Reserved[3]; // Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+ AT91_REG PWMC_MR; // PWMC Mode Register
+ AT91_REG PWMC_ENA; // PWMC Enable Register
+ AT91_REG PWMC_DIS; // PWMC Disable Register
+ AT91_REG PWMC_SR; // PWMC Status Register
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
+ AT91_REG Reserved0[55]; //
+ AT91_REG PWMC_VR; // PWMC Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
+#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4
+#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5
+#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6
+#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register
+ AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG UDP_TXVC; // Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt
+#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
+#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6
+#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ==========
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI peripheral ==========
+#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
+#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
+#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
+#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
+#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
+#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
+#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
+#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
+#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
+#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
+// ========== Register definition for SPI peripheral ==========
+#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
+#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register
+#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
+#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register
+#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
+#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
+#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
+#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
+#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
+
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0
+#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1
+#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data
+#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
+#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave
+#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave
+#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock
+#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync
+#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock
+#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data
+#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data
+#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock
+#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync
+#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data
+#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data
+#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock
+#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send
+#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send
+#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect
+#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready
+#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready
+#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator
+#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data
+#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1
+#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
+#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock
+#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data
+#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data
+#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send
+#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send
+#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data
+#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
+
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller
+#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved
+#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter
+#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved
+#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved
+#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved
+#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
+#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
+
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte)
+
+#endif
diff --git a/AT91SAM7S256/SAM7S256/Include/AT91SAM7S64_inc.h b/AT91SAM7S256/SAM7S256/Include/AT91SAM7S64_inc.h
new file mode 100644
index 0000000..0a34c87
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/AT91SAM7S64_inc.h
@@ -0,0 +1,1710 @@
+// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name : AT91SAM7S64.h
+// Object : AT91SAM7S64 definitions
+// Generated : AT91 SW Application Group 02/23/2005 (17:06:08)
+//
+// CVS Reference : /AT91SAM7S64.pl/1.18/Wed Feb 9 15:26:02 2005//
+// CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005//
+// CVS Reference : /MC_SAM7S.pl/1.2/Tue Feb 1 17:01:00 2005//
+// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005//
+// CVS Reference : /RSTC_SAM7S.pl/1.1/Tue Feb 1 16:16:35 2005//
+// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
+// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
+// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
+// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
+// CVS Reference : /UDP_6083C.pl/1.1/Mon Jan 31 13:01:46 2005//
+// CVS Reference : /AIC_6075A.pl/1.1/Fri Jun 28 10:36:48 2002//
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference : /SPI_6088D.pl/1.2/Mon Feb 14 07:24:18 2005//
+// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference : /TC_6082A.pl/1.6/Fri Feb 18 13:53:30 2005//
+// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
+// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference : /PWM_6044D.pl/1.1/Tue Apr 27 14:53:52 2004//
+// ----------------------------------------------------------------------------
+
+// Hardware register definition
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+// *** Register offset in AT91S_AIC structure ***
+#define AIC_SMR ( 0) // Source Mode Register
+#define AIC_SVR (128) // Source Vector Register
+#define AIC_IVR (256) // IRQ Vector Register
+#define AIC_FVR (260) // FIQ Vector Register
+#define AIC_ISR (264) // Interrupt Status Register
+#define AIC_IPR (268) // Interrupt Pending Register
+#define AIC_IMR (272) // Interrupt Mask Register
+#define AIC_CISR (276) // Core Interrupt Status Register
+#define AIC_IECR (288) // Interrupt Enable Command Register
+#define AIC_IDCR (292) // Interrupt Disable Command Register
+#define AIC_ICCR (296) // Interrupt Clear Command Register
+#define AIC_ISCR (300) // Interrupt Set Command Register
+#define AIC_EOICR (304) // End of Interrupt Command Register
+#define AIC_SPU (308) // Spurious Vector Register
+#define AIC_DCR (312) // Debug Control Register (Protect)
+#define AIC_FFER (320) // Fast Forcing Enable Register
+#define AIC_FFDR (324) // Fast Forcing Disable Register
+#define AIC_FFSR (328) // Fast Forcing Status Register
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+// *** Register offset in AT91S_PDC structure ***
+#define PDC_RPR ( 0) // Receive Pointer Register
+#define PDC_RCR ( 4) // Receive Counter Register
+#define PDC_TPR ( 8) // Transmit Pointer Register
+#define PDC_TCR (12) // Transmit Counter Register
+#define PDC_RNPR (16) // Receive Next Pointer Register
+#define PDC_RNCR (20) // Receive Next Counter Register
+#define PDC_TNPR (24) // Transmit Next Pointer Register
+#define PDC_TNCR (28) // Transmit Next Counter Register
+#define PDC_PTCR (32) // PDC Transfer Control Register
+#define PDC_PTSR (36) // PDC Transfer Status Register
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+// *** Register offset in AT91S_DBGU structure ***
+#define DBGU_CR ( 0) // Control Register
+#define DBGU_MR ( 4) // Mode Register
+#define DBGU_IER ( 8) // Interrupt Enable Register
+#define DBGU_IDR (12) // Interrupt Disable Register
+#define DBGU_IMR (16) // Interrupt Mask Register
+#define DBGU_CSR (20) // Channel Status Register
+#define DBGU_RHR (24) // Receiver Holding Register
+#define DBGU_THR (28) // Transmitter Holding Register
+#define DBGU_BRGR (32) // Baud Rate Generator Register
+#define DBGU_CIDR (64) // Chip ID Register
+#define DBGU_EXID (68) // Chip ID Extension Register
+#define DBGU_FNTR (72) // Force NTRST Register
+#define DBGU_RPR (256) // Receive Pointer Register
+#define DBGU_RCR (260) // Receive Counter Register
+#define DBGU_TPR (264) // Transmit Pointer Register
+#define DBGU_TCR (268) // Transmit Counter Register
+#define DBGU_RNPR (272) // Receive Next Pointer Register
+#define DBGU_RNCR (276) // Receive Next Counter Register
+#define DBGU_TNPR (280) // Transmit Next Pointer Register
+#define DBGU_TNCR (284) // Transmit Next Counter Register
+#define DBGU_PTCR (288) // PDC Transfer Control Register
+#define DBGU_PTSR (292) // PDC Transfer Status Register
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PIO structure ***
+#define PIO_PER ( 0) // PIO Enable Register
+#define PIO_PDR ( 4) // PIO Disable Register
+#define PIO_PSR ( 8) // PIO Status Register
+#define PIO_OER (16) // Output Enable Register
+#define PIO_ODR (20) // Output Disable Registerr
+#define PIO_OSR (24) // Output Status Register
+#define PIO_IFER (32) // Input Filter Enable Register
+#define PIO_IFDR (36) // Input Filter Disable Register
+#define PIO_IFSR (40) // Input Filter Status Register
+#define PIO_SODR (48) // Set Output Data Register
+#define PIO_CODR (52) // Clear Output Data Register
+#define PIO_ODSR (56) // Output Data Status Register
+#define PIO_PDSR (60) // Pin Data Status Register
+#define PIO_IER (64) // Interrupt Enable Register
+#define PIO_IDR (68) // Interrupt Disable Register
+#define PIO_IMR (72) // Interrupt Mask Register
+#define PIO_ISR (76) // Interrupt Status Register
+#define PIO_MDER (80) // Multi-driver Enable Register
+#define PIO_MDDR (84) // Multi-driver Disable Register
+#define PIO_MDSR (88) // Multi-driver Status Register
+#define PIO_PPUDR (96) // Pull-up Disable Register
+#define PIO_PPUER (100) // Pull-up Enable Register
+#define PIO_PPUSR (104) // Pull-up Status Register
+#define PIO_ASR (112) // Select A Register
+#define PIO_BSR (116) // Select B Register
+#define PIO_ABSR (120) // AB Select Status Register
+#define PIO_OWER (160) // Output Write Enable Register
+#define PIO_OWDR (164) // Output Write Disable Register
+#define PIO_OWSR (168) // Output Write Status Register
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+// *** Register offset in AT91S_CKGR structure ***
+#define CKGR_MOR ( 0) // Main Oscillator Register
+#define CKGR_MCFR ( 4) // Main Clock Frequency Register
+#define CKGR_PLLR (12) // PLL Register
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PMC structure ***
+#define PMC_SCER ( 0) // System Clock Enable Register
+#define PMC_SCDR ( 4) // System Clock Disable Register
+#define PMC_SCSR ( 8) // System Clock Status Register
+#define PMC_PCER (16) // Peripheral Clock Enable Register
+#define PMC_PCDR (20) // Peripheral Clock Disable Register
+#define PMC_PCSR (24) // Peripheral Clock Status Register
+#define PMC_MOR (32) // Main Oscillator Register
+#define PMC_MCFR (36) // Main Clock Frequency Register
+#define PMC_PLLR (44) // PLL Register
+#define PMC_MCKR (48) // Master Clock Register
+#define PMC_PCKR (64) // Programmable Clock Register
+#define PMC_IER (96) // Interrupt Enable Register
+#define PMC_IDR (100) // Interrupt Disable Register
+#define PMC_SR (104) // Status Register
+#define PMC_IMR (108) // Interrupt Mask Register
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RSTC structure ***
+#define RSTC_RCR ( 0) // Reset Control Register
+#define RSTC_RSR ( 4) // Reset Status Register
+#define RSTC_RMR ( 8) // Reset Mode Register
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RTTC structure ***
+#define RTTC_RTMR ( 0) // Real-time Mode Register
+#define RTTC_RTAR ( 4) // Real-time Alarm Register
+#define RTTC_RTVR ( 8) // Real-time Value Register
+#define RTTC_RTSR (12) // Real-time Status Register
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PITC structure ***
+#define PITC_PIMR ( 0) // Period Interval Mode Register
+#define PITC_PISR ( 4) // Period Interval Status Register
+#define PITC_PIVR ( 8) // Period Interval Value Register
+#define PITC_PIIR (12) // Period Interval Image Register
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_WDTC structure ***
+#define WDTC_WDCR ( 0) // Watchdog Control Register
+#define WDTC_WDMR ( 4) // Watchdog Mode Register
+#define WDTC_WDSR ( 8) // Watchdog Status Register
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_VREG structure ***
+#define VREG_MR ( 0) // Voltage Regulator Mode Register
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_MC structure ***
+#define MC_RCR ( 0) // MC Remap Control Register
+#define MC_ASR ( 4) // MC Abort Status Register
+#define MC_AASR ( 8) // MC Abort Address Status Register
+#define MC_FMR (96) // MC Flash Mode Register
+#define MC_FCR (100) // MC Flash Command Register
+#define MC_FSR (104) // MC Flash Status Register
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SPI structure ***
+#define SPI_CR ( 0) // Control Register
+#define SPI_MR ( 4) // Mode Register
+#define SPI_RDR ( 8) // Receive Data Register
+#define SPI_TDR (12) // Transmit Data Register
+#define SPI_SR (16) // Status Register
+#define SPI_IER (20) // Interrupt Enable Register
+#define SPI_IDR (24) // Interrupt Disable Register
+#define SPI_IMR (28) // Interrupt Mask Register
+#define SPI_CSR (48) // Chip Select Register
+#define SPI_RPR (256) // Receive Pointer Register
+#define SPI_RCR (260) // Receive Counter Register
+#define SPI_TPR (264) // Transmit Pointer Register
+#define SPI_TCR (268) // Transmit Counter Register
+#define SPI_RNPR (272) // Receive Next Pointer Register
+#define SPI_RNCR (276) // Receive Next Counter Register
+#define SPI_TNPR (280) // Transmit Next Pointer Register
+#define SPI_TNCR (284) // Transmit Next Counter Register
+#define SPI_PTCR (288) // PDC Transfer Control Register
+#define SPI_PTSR (292) // PDC Transfer Status Register
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+// *** Register offset in AT91S_ADC structure ***
+#define ADC_CR ( 0) // ADC Control Register
+#define ADC_MR ( 4) // ADC Mode Register
+#define ADC_CHER (16) // ADC Channel Enable Register
+#define ADC_CHDR (20) // ADC Channel Disable Register
+#define ADC_CHSR (24) // ADC Channel Status Register
+#define ADC_SR (28) // ADC Status Register
+#define ADC_LCDR (32) // ADC Last Converted Data Register
+#define ADC_IER (36) // ADC Interrupt Enable Register
+#define ADC_IDR (40) // ADC Interrupt Disable Register
+#define ADC_IMR (44) // ADC Interrupt Mask Register
+#define ADC_CDR0 (48) // ADC Channel Data Register 0
+#define ADC_CDR1 (52) // ADC Channel Data Register 1
+#define ADC_CDR2 (56) // ADC Channel Data Register 2
+#define ADC_CDR3 (60) // ADC Channel Data Register 3
+#define ADC_CDR4 (64) // ADC Channel Data Register 4
+#define ADC_CDR5 (68) // ADC Channel Data Register 5
+#define ADC_CDR6 (72) // ADC Channel Data Register 6
+#define ADC_CDR7 (76) // ADC Channel Data Register 7
+#define ADC_RPR (256) // Receive Pointer Register
+#define ADC_RCR (260) // Receive Counter Register
+#define ADC_TPR (264) // Transmit Pointer Register
+#define ADC_TCR (268) // Transmit Counter Register
+#define ADC_RNPR (272) // Receive Next Pointer Register
+#define ADC_RNCR (276) // Receive Next Counter Register
+#define ADC_TNPR (280) // Transmit Next Pointer Register
+#define ADC_TNCR (284) // Transmit Next Counter Register
+#define ADC_PTCR (288) // PDC Transfer Control Register
+#define ADC_PTSR (292) // PDC Transfer Status Register
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SSC structure ***
+#define SSC_CR ( 0) // Control Register
+#define SSC_CMR ( 4) // Clock Mode Register
+#define SSC_RCMR (16) // Receive Clock ModeRegister
+#define SSC_RFMR (20) // Receive Frame Mode Register
+#define SSC_TCMR (24) // Transmit Clock Mode Register
+#define SSC_TFMR (28) // Transmit Frame Mode Register
+#define SSC_RHR (32) // Receive Holding Register
+#define SSC_THR (36) // Transmit Holding Register
+#define SSC_RSHR (48) // Receive Sync Holding Register
+#define SSC_TSHR (52) // Transmit Sync Holding Register
+#define SSC_SR (64) // Status Register
+#define SSC_IER (68) // Interrupt Enable Register
+#define SSC_IDR (72) // Interrupt Disable Register
+#define SSC_IMR (76) // Interrupt Mask Register
+#define SSC_RPR (256) // Receive Pointer Register
+#define SSC_RCR (260) // Receive Counter Register
+#define SSC_TPR (264) // Transmit Pointer Register
+#define SSC_TCR (268) // Transmit Counter Register
+#define SSC_RNPR (272) // Receive Next Pointer Register
+#define SSC_RNCR (276) // Receive Next Counter Register
+#define SSC_TNPR (280) // Transmit Next Pointer Register
+#define SSC_TNCR (284) // Transmit Next Counter Register
+#define SSC_PTCR (288) // PDC Transfer Control Register
+#define SSC_PTSR (292) // PDC Transfer Status Register
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+// *** Register offset in AT91S_USART structure ***
+#define US_CR ( 0) // Control Register
+#define US_MR ( 4) // Mode Register
+#define US_IER ( 8) // Interrupt Enable Register
+#define US_IDR (12) // Interrupt Disable Register
+#define US_IMR (16) // Interrupt Mask Register
+#define US_CSR (20) // Channel Status Register
+#define US_RHR (24) // Receiver Holding Register
+#define US_THR (28) // Transmitter Holding Register
+#define US_BRGR (32) // Baud Rate Generator Register
+#define US_RTOR (36) // Receiver Time-out Register
+#define US_TTGR (40) // Transmitter Time-guard Register
+#define US_FIDI (64) // FI_DI_Ratio Register
+#define US_NER (68) // Nb Errors Register
+#define US_IF (76) // IRDA_FILTER Register
+#define US_RPR (256) // Receive Pointer Register
+#define US_RCR (260) // Receive Counter Register
+#define US_TPR (264) // Transmit Pointer Register
+#define US_TCR (268) // Transmit Counter Register
+#define US_RNPR (272) // Receive Next Pointer Register
+#define US_RNCR (276) // Receive Next Counter Register
+#define US_TNPR (280) // Transmit Next Pointer Register
+#define US_TNCR (284) // Transmit Next Counter Register
+#define US_PTCR (288) // PDC Transfer Control Register
+#define US_PTSR (292) // PDC Transfer Status Register
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TWI structure ***
+#define TWI_CR ( 0) // Control Register
+#define TWI_MMR ( 4) // Master Mode Register
+#define TWI_IADR (12) // Internal Address Register
+#define TWI_CWGR (16) // Clock Waveform Generator Register
+#define TWI_SR (32) // Status Register
+#define TWI_IER (36) // Interrupt Enable Register
+#define TWI_IDR (40) // Interrupt Disable Register
+#define TWI_IMR (44) // Interrupt Mask Register
+#define TWI_RHR (48) // Receive Holding Register
+#define TWI_THR (52) // Transmit Holding Register
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TC structure ***
+#define TC_CCR ( 0) // Channel Control Register
+#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV (16) // Counter Value
+#define TC_RA (20) // Register A
+#define TC_RB (24) // Register B
+#define TC_RC (28) // Register C
+#define TC_SR (32) // Status Register
+#define TC_IER (36) // Interrupt Enable Register
+#define TC_IDR (40) // Interrupt Disable Register
+#define TC_IMR (44) // Interrupt Mask Register
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE (0x1 << 15) // (TC)
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TCB structure ***
+#define TCB_TC0 ( 0) // TC Channel 0
+#define TCB_TC1 (64) // TC Channel 1
+#define TCB_TC2 (128) // TC Channel 2
+#define TCB_BCR (192) // TC Block Control Register
+#define TCB_BMR (196) // TC Block Mode Register
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC_CH structure ***
+#define PWMC_CMR ( 0) // Channel Mode Register
+#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register
+#define PWMC_CPRDR ( 8) // Channel Period Register
+#define PWMC_CCNTR (12) // Channel Counter Register
+#define PWMC_CUPDR (16) // Channel Update Register
+#define PWMC_Reserved (20) // Reserved
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC structure ***
+#define PWMC_MR ( 0) // PWMC Mode Register
+#define PWMC_ENA ( 4) // PWMC Enable Register
+#define PWMC_DIS ( 8) // PWMC Disable Register
+#define PWMC_SR (12) // PWMC Status Register
+#define PWMC_IER (16) // PWMC Interrupt Enable Register
+#define PWMC_IDR (20) // PWMC Interrupt Disable Register
+#define PWMC_IMR (24) // PWMC Interrupt Mask Register
+#define PWMC_ISR (28) // PWMC Interrupt Status Register
+#define PWMC_VR (252) // PWMC Version Register
+#define PWMC_CH (512) // PWMC Channel 0
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
+#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4
+#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5
+#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6
+#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+// *** Register offset in AT91S_UDP structure ***
+#define UDP_NUM ( 0) // Frame Number Register
+#define UDP_GLBSTATE ( 4) // Global State Register
+#define UDP_FADDR ( 8) // Function Address Register
+#define UDP_IER (16) // Interrupt Enable Register
+#define UDP_IDR (20) // Interrupt Disable Register
+#define UDP_IMR (24) // Interrupt Mask Register
+#define UDP_ISR (28) // Interrupt Status Register
+#define UDP_ICR (32) // Interrupt Clear Register
+#define UDP_RSTEP (40) // Reset Endpoint Register
+#define UDP_CSR (48) // Endpoint Control and Status Register
+#define UDP_FDR (80) // Endpoint FIFO Data Register
+#define UDP_TXVC (116) // Transceiver Control Register
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt
+#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
+#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6
+#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ==========
+#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI peripheral ==========
+#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
+#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
+#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register
+#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register
+#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
+#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
+#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register
+#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
+#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
+#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
+// ========== Register definition for SPI peripheral ==========
+#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register
+#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register
+#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register
+#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register
+#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register
+#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register
+#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register
+#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register
+#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register
+
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0
+#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1
+#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data
+#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
+#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave
+#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave
+#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock
+#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync
+#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock
+#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data
+#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data
+#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock
+#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2
+#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync
+#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data
+#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data
+#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock
+#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send
+#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send
+#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect
+#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready
+#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready
+#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator
+#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data
+#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1
+#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
+#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock
+#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data
+#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data
+#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send
+#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send
+#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data
+#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
+
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ( 1) // System Peripheral
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller
+#define AT91C_ID_3_Reserved ( 3) // Reserved
+#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter
+#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface
+#define AT91C_ID_US0 ( 6) // USART 0
+#define AT91C_ID_US1 ( 7) // USART 1
+#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ( 9) // Two-Wire Interface
+#define AT91C_ID_PWMC (10) // PWM Controller
+#define AT91C_ID_UDP (11) // USB Device Port
+#define AT91C_ID_TC0 (12) // Timer Counter 0
+#define AT91C_ID_TC1 (13) // Timer Counter 1
+#define AT91C_ID_TC2 (14) // Timer Counter 2
+#define AT91C_ID_15_Reserved (15) // Reserved
+#define AT91C_ID_16_Reserved (16) // Reserved
+#define AT91C_ID_17_Reserved (17) // Reserved
+#define AT91C_ID_18_Reserved (18) // Reserved
+#define AT91C_ID_19_Reserved (19) // Reserved
+#define AT91C_ID_20_Reserved (20) // Reserved
+#define AT91C_ID_21_Reserved (21) // Reserved
+#define AT91C_ID_22_Reserved (22) // Reserved
+#define AT91C_ID_23_Reserved (23) // Reserved
+#define AT91C_ID_24_Reserved (24) // Reserved
+#define AT91C_ID_25_Reserved (25) // Reserved
+#define AT91C_ID_26_Reserved (26) // Reserved
+#define AT91C_ID_27_Reserved (27) // Reserved
+#define AT91C_ID_28_Reserved (28) // Reserved
+#define AT91C_ID_29_Reserved (29) // Reserved
+#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address
+#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address
+
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte)
+#define AT91C_IFLASH (0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE (0x00010000) // Internal ROM size in byte (64 Kbyte)
+
+
diff --git a/AT91SAM7S256/SAM7S256/Include/Board.h b/AT91SAM7S256/SAM7S256/Include/Board.h
new file mode 100644
index 0000000..95e15e0
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/Board.h
@@ -0,0 +1,89 @@
+/*----------------------------------------------------------------------------
+* ATMEL Microcontroller Software Support - ROUSSET -
+*----------------------------------------------------------------------------
+* The software is delivered "AS IS" without warranty or condition of any
+* kind, either express, implied or statutory. This includes without
+* limitation any warranty or condition with respect to merchantability or
+* fitness for any particular purpose, or against the infringements of
+* intellectual property rights of others.
+*----------------------------------------------------------------------------
+* File Name : Board.h
+* Object : AT91SAM7S Evaluation Board Features Definition File.
+*
+* Creation : JPP 16/Jun/2004
+*----------------------------------------------------------------------------
+*/
+#ifndef Board_h
+#define Board_h
+
+#include "include/AT91SAM7S64.h"
+#define __inline inline
+#include "include/lib_AT91SAM7S64.h"
+
+#define true -1
+#define false 0
+
+/*-------------------------------*/
+/* SAM7Board Memories Definition */
+/*-------------------------------*/
+// The AT91SAM7S64 embeds a 16-Kbyte SRAM bank, and 64 K-Byte Flash
+
+#define INT_SARM 0x00200000
+#define INT_SARM_REMAP 0x00000000
+
+#define INT_FLASH 0x00000000
+#define INT_FLASH_REMAP 0x01000000
+
+#define FLASH_PAGE_NB 512
+#define FLASH_PAGE_SIZE 128
+
+/*-----------------*/
+/* Leds Definition */
+/*-----------------*/
+/* PIO Flash PA PB PIN */
+#define LED1 (1<<0) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */
+#define LED2 (1<<1) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */
+#define LED3 (1<<2) /* PA2 & PWM2 SCK0 44 */
+#define LED4 (1<<3) /* PA3 & TWD NPCS3 43 */
+#define NB_LEB 4
+
+#define LED_MASK (LED1|LED2|LED3|LED4)
+
+/*-------------------------*/
+/* Push Buttons Definition */
+/*-------------------------*/
+/* PIO Flash PA PB PIN */
+#define SW1_MASK (1<<19) /* PA19 / PGMD7 & RK FIQ 13 */
+#define SW2_MASK (1<<20) /* PA20 / PGMD8 & RF IRQ0 16 */
+#define SW3_MASK (1<<15) /* PA15 / PGM3 & TF TIOA1 20 */
+#define SW4_MASK (1<<14) /* PA14 / PGMD2 & SPCK PWM3 21 */
+#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
+
+
+#define SW1 (1<<19) // PA19
+#define SW2 (1<<20) // PA20
+#define SW3 (1<<15) // PA15
+#define SW4 (1<<14) // PA14
+
+/*------------------*/
+/* USART Definition */
+/*------------------*/
+/* SUB-D 9 points J3 DBGU*/
+#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */
+#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */
+#define AT91C_DBGU_BAUD 115200 // Baud rate
+
+#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */
+#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */
+#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */
+#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */
+
+/*--------------*/
+/* Master Clock */
+/*--------------*/
+
+#define EXT_OC 18432000 // Exetrnal ocilator MAINCK
+#define MCK 47923200 // MCK (PLLRC div by 2)
+#define MCKKHz (MCK/1000) //
+
+#endif /* Board_h */
diff --git a/AT91SAM7S256/SAM7S256/Include/DLib_Defaults.h b/AT91SAM7S256/SAM7S256/Include/DLib_Defaults.h
new file mode 100644
index 0000000..d3f2d27
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/DLib_Defaults.h
@@ -0,0 +1,685 @@
+
+/***************************************************
+ *
+ * DLib_Defaults.h is the library configuration manager.
+ *
+ * Copyright (C) 2003 IAR Systems. All rights reserved.
+ *
+ * $Revision: 1 $
+ *
+ * This configuration header file performs the following tasks:
+ *
+ * 1. Includes the configuration header file, defined by _DLIB_CONFIG_FILE,
+ * that sets up a particular runtime environment.
+ *
+ * 2. Includes the product configuration header file, DLib_Product.h, that
+ * specifies default values for the product and makes sure that the
+ * configuration is valid.
+ *
+ * 3. Sets up default values for all remaining configuration symbols.
+ *
+ * This configuration header file, the one defined by _DLIB_CONFIG_FILE, and
+ * DLib_Product.h configures how the runtime environment should behave. This
+ * includes all system headers and the library itself, i.e. all system headers
+ * includes this configuration header file, and the library has been built
+ * using this configuration header file.
+ *
+ ***************************************************
+ *
+ * DO NOT MODIFY THIS FILE!
+ *
+ ***************************************************/
+
+#ifndef _DLIB_DEFAULTS_H
+#define _DLIB_DEFAULTS_H
+
+#pragma system_include
+
+/* Include the main configuration header file. */
+#if defined(_DLIB_CONFIG_FILE_HEADER_NAME)
+ #include _DLIB_CONFIG_FILE_HEADER_NAME
+ /* _DLIB_CONFIG_FILE_STRING is the quoted variant of above */
+#elif defined(_DLIB_CONFIG_FILE)
+ #include _STRINGIFY(_DLIB_CONFIG_FILE)
+#else
+ #pragma message("Library configuration file is not specified. Use\
+ --dlib_config, please see the compiler reference guide for details.")
+#endif
+
+/* Include the product specific header file. */
+#ifndef __NO_DLIB_PRODUCT_FILE
+ #include <DLib_Product.h>
+#endif
+
+
+/*
+ * The remainder of the file sets up defaults for a number of
+ * configuration symbols, each corresponds to a feature in the
+ * libary.
+ *
+ * The value of the symbols should either be 1, if the feature should
+ * be supported, or 0 if it shouldn't. (Except where otherwise
+ * noted.)
+ */
+
+
+
+
+/*
+ * File handling
+ *
+ * Determines whether FILE descriptors and related functions exists or not.
+ * When this feature is selected, i.e. set to 1, then FILE descriptors and
+ * related functions (e.g. fprintf, fopen) exist. All files, even stdin,
+ * stdout, and stderr will then be handled with a file system mechanism that
+ * buffers files before accessing the lowlevel I/O interface (__open, __read,
+ * __write, etc).
+ *
+ * If not selected, i.e. set to 0, then FILE descriptors and related functions
+ * (e.g. fprintf, fopen) does not exist. All functions that normally uses
+ * stderr will use stdout instead. Functions that uses stdout and stdin (like
+ * printf and scanf) will access the lowlevel I/O interface directly (__open,
+ * __read, __write, etc), i.e. there will not be any buffering.
+ *
+ * The default is not to have support for FILE descriptors.
+ */
+
+#ifndef _DLIB_FILE_DESCRIPTOR
+#define _DLIB_FILE_DESCRIPTOR 0
+#endif
+
+/*
+ * Use static buffers for stdout
+ *
+ * This setting controls whether the stream stdout uses a static 80 bytes
+ * buffer or uses a one byte buffer allocated in the file descriptor. This
+ * setting is only applicable if the FILE descriptors are enabled above.
+ *
+ * Default is to use a static 80 byte buffer.
+ */
+
+#ifndef _DLIB_STDOUT_USES_STATIC_BUFFER
+#define _DLIB_STDOUT_USES_STATIC_BUFFER 1
+#endif
+
+/*
+ * Support of locale interface
+ *
+ * "Locale" is the system in C that support language- and
+ * contry-specific settings for a number of areas, including currency
+ * symbols, date and time, and multibyte encodings.
+ *
+ * This setting determines whether the locale interface exist or not.
+ * When this feature is selected, i.e. set to 1, the locale interface exist
+ * (setlocale, etc). A number of preselected locales can be activated during
+ * runtime. The preselected locales and encodings is choosen by defining any
+ * number of _LOCALE_USE_xxx and _ENCODING_USE_xxx symbols. The application
+ * will start with the "C" locale choosen. (Single byte encoding is always
+ * supported in this mode.)
+ *
+ *
+ * If not selected, i.e. set to 0, the locale interface (setlocale, etc) does
+ * not exist. One preselected locale and one preselected encoding is then used
+ * directly. That locale can not be changed during runtime. The preselected
+ * locale and encoding is choosen by defining at most one of _LOCALE_USE_xxx
+ * and at most one of _ENCODING_USE_xxx. The default is to use the "C" locale
+ * and the single byte encoding, respectively.
+ *
+ * The default is not to have support for the locale interface with the "C"
+ * locale and the single byte encoding.
+ *
+ * Supported locales
+ * -----------------
+ * _LOCALE_USE_C C standard locale (the default)
+ * _LOCALE_USE_POSIX ISO-8859-1 Posix locale
+ * _LOCALE_USE_CS_CZ ISO-8859-2 Czech language locale for Czech Republic
+ * _LOCALE_USE_DA_DK ISO-8859-1 Danish language locale for Denmark
+ * _LOCALE_USE_DA_EU ISO-8859-15 Danish language locale for Europe
+ * _LOCALE_USE_DE_AT ISO-8859-1 German language locale for Austria
+ * _LOCALE_USE_DE_BE ISO-8859-1 German language locale for Belgium
+ * _LOCALE_USE_DE_CH ISO-8859-1 German language locale for Switzerland
+ * _LOCALE_USE_DE_DE ISO-8859-1 German language locale for Germany
+ * _LOCALE_USE_DE_EU ISO-8859-15 German language locale for Europe
+ * _LOCALE_USE_DE_LU ISO-8859-1 German language locale for Luxemburg
+ * _LOCALE_USE_EL_EU ISO-8859-7x Greek language locale for Europe
+ * (Euro symbol added)
+ * _LOCALE_USE_EL_GR ISO-8859-7 Greek language locale for Greece
+ * _LOCALE_USE_EN_AU ISO-8859-1 English language locale for Australia
+ * _LOCALE_USE_EN_CA ISO-8859-1 English language locale for Canada
+ * _LOCALE_USE_EN_DK ISO_8859-1 English language locale for Denmark
+ * _LOCALE_USE_EN_EU ISO-8859-15 English language locale for Europe
+ * _LOCALE_USE_EN_GB ISO-8859-1 English language locale for United Kingdom
+ * _LOCALE_USE_EN_IE ISO-8859-1 English language locale for Ireland
+ * _LOCALE_USE_EN_NZ ISO-8859-1 English language locale for New Zealand
+ * _LOCALE_USE_EN_US ISO-8859-1 English language locale for USA
+ * _LOCALE_USE_ES_AR ISO-8859-1 Spanish language locale for Argentina
+ * _LOCALE_USE_ES_BO ISO-8859-1 Spanish language locale for Bolivia
+ * _LOCALE_USE_ES_CL ISO-8859-1 Spanish language locale for Chile
+ * _LOCALE_USE_ES_CO ISO-8859-1 Spanish language locale for Colombia
+ * _LOCALE_USE_ES_DO ISO-8859-1 Spanish language locale for Dominican Republic
+ * _LOCALE_USE_ES_EC ISO-8859-1 Spanish language locale for Equador
+ * _LOCALE_USE_ES_ES ISO-8859-1 Spanish language locale for Spain
+ * _LOCALE_USE_ES_EU ISO-8859-15 Spanish language locale for Europe
+ * _LOCALE_USE_ES_GT ISO-8859-1 Spanish language locale for Guatemala
+ * _LOCALE_USE_ES_HN ISO-8859-1 Spanish language locale for Honduras
+ * _LOCALE_USE_ES_MX ISO-8859-1 Spanish language locale for Mexico
+ * _LOCALE_USE_ES_PA ISO-8859-1 Spanish language locale for Panama
+ * _LOCALE_USE_ES_PE ISO-8859-1 Spanish language locale for Peru
+ * _LOCALE_USE_ES_PY ISO-8859-1 Spanish language locale for Paraguay
+ * _LOCALE_USE_ES_SV ISO-8859-1 Spanish language locale for Salvador
+ * _LOCALE_USE_ES_US ISO-8859-1 Spanish language locale for USA
+ * _LOCALE_USE_ES_UY ISO-8859-1 Spanish language locale for Uruguay
+ * _LOCALE_USE_ES_VE ISO-8859-1 Spanish language locale for Venezuela
+ * _LOCALE_USE_ET_EE ISO-8859-1 Estonian language for Estonia
+ * _LOCALE_USE_EU_ES ISO-8859-1 Basque language locale for Spain
+ * _LOCALE_USE_FI_EU ISO-8859-15 Finnish language locale for Europe
+ * _LOCALE_USE_FI_FI ISO-8859-1 Finnish language locale for Finland
+ * _LOCALE_USE_FO_FO ISO-8859-1 Faroese language locale for Faroe Islands
+ * _LOCALE_USE_FR_BE ISO-8859-1 French language locale for Belgium
+ * _LOCALE_USE_FR_CA ISO-8859-1 French language locale for Canada
+ * _LOCALE_USE_FR_CH ISO-8859-1 French language locale for Switzerland
+ * _LOCALE_USE_FR_EU ISO-8859-15 French language locale for Europe
+ * _LOCALE_USE_FR_FR ISO-8859-1 French language locale for France
+ * _LOCALE_USE_FR_LU ISO-8859-1 French language locale for Luxemburg
+ * _LOCALE_USE_GA_EU ISO-8859-15 Irish language locale for Europe
+ * _LOCALE_USE_GA_IE ISO-8859-1 Irish language locale for Ireland
+ * _LOCALE_USE_GL_ES ISO-8859-1 Galician language locale for Spain
+ * _LOCALE_USE_HR_HR ISO-8859-2 Croatian language locale for Croatia
+ * _LOCALE_USE_HU_HU ISO-8859-2 Hungarian language locale for Hungary
+ * _LOCALE_USE_ID_ID ISO-8859-1 Indonesian language locale for Indonesia
+ * _LOCALE_USE_IS_EU ISO-8859-15 Icelandic language locale for Europe
+ * _LOCALE_USE_IS_IS ISO-8859-1 Icelandic language locale for Iceland
+ * _LOCALE_USE_IT_EU ISO-8859-15 Italian language locale for Europe
+ * _LOCALE_USE_IT_IT ISO-8859-1 Italian language locale for Italy
+ * _LOCALE_USE_IW_IL ISO-8859-8 Hebrew language locale for Israel
+ * _LOCALE_USE_KL_GL ISO-8859-1 Greenlandic language locale for Greenland
+ * _LOCALE_USE_LT_LT BALTIC Lithuanian languagelocale for Lithuania
+ * _LOCALE_USE_LV_LV BALTIC Latvian languagelocale for Latvia
+ * _LOCALE_USE_NL_BE ISO-8859-1 Dutch language locale for Belgium
+ * _LOCALE_USE_NL_EU ISO-8859-15 Dutch language locale for Europe
+ * _LOCALE_USE_NL_NL ISO-8859-9 Dutch language locale for Netherlands
+ * _LOCALE_USE_NO_EU ISO-8859-15 Norwegian language locale for Europe
+ * _LOCALE_USE_NO_NO ISO-8859-1 Norwegian language locale for Norway
+ * _LOCALE_USE_PL_PL ISO-8859-2 Polish language locale for Poland
+ * _LOCALE_USE_PT_BR ISO-8859-1 Portugese language locale for Brazil
+ * _LOCALE_USE_PT_EU ISO-8859-15 Portugese language locale for Europe
+ * _LOCALE_USE_PT_PT ISO-8859-1 Portugese language locale for Portugal
+ * _LOCALE_USE_RO_RO ISO-8859-2 Romanian language locale for Romania
+ * _LOCALE_USE_RU_RU ISO-8859-5 Russian language locale for Russia
+ * _LOCALE_USE_SL_SI ISO-8859-2 Slovenian language locale for Slovenia
+ * _LOCALE_USE_SV_EU ISO-8859-15 Swedish language locale for Europe
+ * _LOCALE_USE_SV_FI ISO-8859-1 Swedish language locale for Finland
+ * _LOCALE_USE_SV_SE ISO-8859-1 Swedish language locale for Sweden
+ * _LOCALE_USE_TR_TR ISO-8859-9 Turkish language locale for Turkey
+ *
+ * Supported encodings
+ * -------------------
+ * n/a Single byte (used if no other is defined).
+ * _ENCODING_USE_UTF8 UTF8 encoding.
+ */
+
+#ifndef _DLIB_FULL_LOCALE_SUPPORT
+#define _DLIB_FULL_LOCALE_SUPPORT 0
+#endif
+
+/* We need to have the "C" locale if we have full locale support. */
+#if _DLIB_FULL_LOCALE_SUPPORT && !defined(_LOCALE_USE_C)
+#define _LOCALE_USE_C
+#endif
+
+
+/*
+ * Support of multibytes in printf- and scanf-like functions
+ *
+ * This is the default value for _DLIB_PRINTF_MULTIBYTE and
+ * _DLIB_SCANF_MULTIBYTE. See them for a description.
+ *
+ * Default is to not have support for multibytes in printf- and scanf-like
+ * functions.
+ */
+
+#ifndef _DLIB_FORMATTED_MULTIBYTE
+#define _DLIB_FORMATTED_MULTIBYTE 0
+#endif
+
+
+/*
+ * Throw handling in the EC++ library
+ *
+ * This setting determines what happens when the EC++ part of the library
+ * fails (where a normal C++ library 'throws').
+ *
+ * The following alternatives exists (setting of the symbol):
+ * 0 - The application does nothing, i.e. continues with the
+ * next statement.
+ * 1 - The application terminates by calling the 'abort'
+ * function directly.
+ * <anything else> - An object of class "exception" is created. This
+ * object contains a string describing the problem.
+ * This string is later emitted on "stderr" before
+ * the application terminates by calling the 'abort'
+ * function directly.
+ *
+ * Default is to do nothing.
+ */
+
+#ifndef _DLIB_THROW_HANDLING
+#define _DLIB_THROW_HANDLING 0
+#endif
+
+
+/*
+ * Handling of floating-point environment
+ *
+ * If selected, i.e. set to 1, then the floating-point environment, defined in
+ * the header file fenv.h, is updated when a floating-point operation produces
+ * an exception (overflow, etc). Note that not all products support this.
+ *
+ * If not selected, i.e. set to 0, then the floating-point environment is not
+ * updated.
+ *
+ * Default is to not update the floating-point environment.
+ */
+
+#ifndef _DLIB_FLOAT_ENVIRONMENT
+#define _DLIB_FLOAT_ENVIRONMENT 0
+#endif
+
+
+/*
+ * Hexadecimal floating-point numbers in strtod
+ *
+ * If selected, i.e. set to 1, strtod supports C99 hexadecimal floating-point
+ * numbers. This also enables hexadecimal floating-points in internal functions
+ * used for converting strings and wide strings to float, double, and long
+ * double.
+ *
+ * If not selected, i.e. set to 0, C99 hexadecimal floating-point numbers
+ * aren't supported.
+ *
+ * Default is not to support hexadecimal floating-point numbers.
+ */
+
+#ifndef _DLIB_STRTOD_HEX_FLOAT
+#define _DLIB_STRTOD_HEX_FLOAT 0
+#endif
+
+
+/*
+ * Printf configuration symbols.
+ *
+ * All the configuration symbols described further on controls the behaviour
+ * of printf, sprintf, and the other printf variants.
+ *
+ * The library proves four formatters for printf: 'tiny', 'small',
+ * 'large', and 'default'. The setup in this file controls all except
+ * 'tiny'. Note that both small' and 'large' explicitly removes
+ * some features.
+ */
+
+/*
+ * Handle multibytes in printf
+ *
+ * This setting controls whether multibytes and wchar_ts are supported in
+ * printf. Set to 1 to support them, otherwise set to 0.
+ *
+ * See _DLIB_FORMATTED_MULTIBYTE for the default setting.
+ */
+
+#ifndef _DLIB_PRINTF_MULTIBYTE
+#define _DLIB_PRINTF_MULTIBYTE _DLIB_FORMATTED_MULTIBYTE
+#endif
+
+/*
+ * Long long formatting in printf
+ *
+ * This setting controls long long support (%lld) in printf. Set to 1 to
+ * support it, otherwise set to 0.
+
+ * Note, if long long should not be supported and 'intmax_t' is larger than
+ * an ordinary 'long', then %jd and %jn will not be supported.
+ *
+ * Default is to support long long formatting.
+ */
+
+#ifndef _DLIB_PRINTF_LONG_LONG
+ #ifdef __LONG_LONG_SIZE__
+ #define _DLIB_PRINTF_LONG_LONG 1
+ #else
+ #define _DLIB_PRINTF_LONG_LONG 0
+ #endif
+#endif
+
+#if _DLIB_PRINTF_LONG_LONG && !defined(__LONG_LONG_SIZE__)
+#error "Long long support turned on for printf, the compiler doesn't support long long though"
+#endif
+
+
+/*
+ * Floating-point formatting in printf
+ *
+ * This setting controls whether printf supports floating-point formatting.
+ * Set to 1 to support them, otherwise set to 0.
+ *
+ * Default is to support floating-point formatting.
+ */
+
+#ifndef _DLIB_PRINTF_SPECIFIER_FLOAT
+#define _DLIB_PRINTF_SPECIFIER_FLOAT 1
+#endif
+
+/*
+ * Hexadecimal floating-point formatting in printf
+ *
+ * This setting controls whether the %a format, i.e. the output of
+ * floating-point numbers in the C99 hexadecimal format. Set to 1 to support
+ * it, otherwise set to 0.
+ *
+ * Default is to support %a in printf.
+ */
+
+#ifndef _DLIB_PRINTF_SPECIFIER_A
+#define _DLIB_PRINTF_SPECIFIER_A 1
+#endif
+
+/*
+ * Output count formatting in printf
+ *
+ * This setting controls whether the output count specifier (%n) is supported
+ * or not in printf. Set to 1 to support it, otherwise set to 0.
+ *
+ * Default is to support %n in printf.
+ */
+
+#ifndef _DLIB_PRINTF_SPECIFIER_N
+#define _DLIB_PRINTF_SPECIFIER_N 1
+#endif
+
+/*
+ * Support of qualifiers in printf
+ *
+ * This setting controls whether qualifiers that enlarges the input value
+ * [hlLjtz] is supported in printf or not. Set to 1 to support them, otherwise
+ * set to 0. See also _DLIB_PRINTF_INT_TYPE_IS_INT and
+ * _DLIB_PRINTF_INT_TYPE_IS_LONG.
+ *
+ * Default is to support [hlLjtz] qualifiers in printf.
+ */
+
+#ifndef _DLIB_PRINTF_QUALIFIERS
+#define _DLIB_PRINTF_QUALIFIERS 1
+#endif
+
+/*
+ * Support of flags in printf
+ *
+ * This setting controls whether flags (-+ #0) is supported in printf or not.
+ * Set to 1 to support them, otherwise set to 0.
+ *
+ * Default is to support flags in printf.
+ */
+
+#ifndef _DLIB_PRINTF_FLAGS
+#define _DLIB_PRINTF_FLAGS 1
+#endif
+
+/*
+ * Support widths and precisions in printf
+ *
+ * This setting controls whether widths and precisions are supported in printf.
+ * Set to 1 to support them, otherwise set to 0.
+ *
+ * Default is to support widths and precisions in printf.
+ */
+
+#ifndef _DLIB_PRINTF_WIDTH_AND_PRECISION
+#define _DLIB_PRINTF_WIDTH_AND_PRECISION 1
+#endif
+
+/*
+ * Support of unsigned integer formatting in printf
+ *
+ * This setting controls whether unsigned integer formatting is supported in
+ * printf. Set to 1 to support it, otherwise set to 0.
+ *
+ * Default is to support unsigned integer formatting in printf.
+ */
+
+#ifndef _DLIB_PRINTF_SPECIFIER_UNSIGNED
+#define _DLIB_PRINTF_SPECIFIER_UNSIGNED 1
+#endif
+
+/*
+ * Support of signed integer formatting in printf
+ *
+ * This setting controls whether signed integer formatting is supported in
+ * printf. Set to 1 to support it, otherwise set to 0.
+ *
+ * Default is to support signed integer formatting in printf.
+ */
+
+#ifndef _DLIB_PRINTF_SPECIFIER_SIGNED
+#define _DLIB_PRINTF_SPECIFIER_SIGNED 1
+#endif
+
+/*
+ * Support of formatting anything larger than int in printf
+ *
+ * This setting controls if 'int' should be used internally in printf, rather
+ * than the largest existing integer type. If 'int' is used, any integer or
+ * pointer type formatting use 'int' as internal type even though the
+ * formatted type is larger. Set to 1 to use 'int' as internal type, otherwise
+ * set to 0.
+ *
+ * See also next configuration.
+ *
+ * Default is to internally use largest existing internally type.
+ */
+
+#ifndef _DLIB_PRINTF_INT_TYPE_IS_INT
+#define _DLIB_PRINTF_INT_TYPE_IS_INT 0
+#endif
+
+/*
+ * Support of formatting anything larger than long in printf
+ *
+ * This setting controls if 'long' should be used internally in printf, rather
+ * than the largest existing integer type. If 'long' is used, any integer or
+ * pointer type formatting use 'long' as internal type even though the
+ * formatted type is larger. Set to 1 to use 'long' as internal type,
+ * otherwise set to 0.
+ *
+ * See also previous configuration.
+ *
+ * Default is to internally use largest existing internally type.
+ */
+
+#ifndef _DLIB_PRINTF_INT_TYPE_IS_LONG
+#define _DLIB_PRINTF_INT_TYPE_IS_LONG 0
+#endif
+
+#if _DLIB_PRINTF_INT_TYPE_IS_INT && _DLIB_PRINTF_INT_TYPE_IS_LONG
+#error "At most one of _DLIB_PRINTF_INT_TYPE_IS_INT and _DLIB_PRINTF_INT_TYPE_IS_LONG can be defined."
+#endif
+
+/*
+ * Emit a char a time in printf
+ *
+ * This setting controls internal output handling. If selected, i.e. set to 1,
+ * then printf emits one character at a time, which requires less code but
+ * can be slightly slower for some types of output.
+ *
+ * If not selected, i.e. set to 0, then printf buffers some outputs.
+ *
+ * Note that it is recommended to either use full file support (see
+ * _DLIB_FILE_DESCRIPTOR) or -- for debug output -- use the linker
+ * option "-e__write_buffered=__write" to enable buffered I/O rather
+ * than deselecting this feature.
+ */
+
+#ifndef _DLIB_PRINTF_CHAR_BY_CHAR
+#define _DLIB_PRINTF_CHAR_BY_CHAR 1
+#endif
+
+
+/*
+ * Scanf configuration symbols.
+ *
+ * All the configuration symbols described here controls the
+ * behaviour of scanf, sscanf, and the other scanf variants.
+ *
+ * The library proves three formatters for scanf: 'small', 'large',
+ * and 'default'. The setup in this file controls all, however both
+ * 'small' and 'large' explicitly removes some features.
+ */
+
+/*
+ * Handle multibytes in scanf
+ *
+ * This setting controls whether multibytes and wchar_t:s are supported in
+ * scanf. Set to 1 to support them, otherwise set to 0.
+ *
+ * See _DLIB_FORMATTED_MULTIBYTE for the default.
+ */
+
+#ifndef _DLIB_SCANF_MULTIBYTE
+#define _DLIB_SCANF_MULTIBYTE _DLIB_FORMATTED_MULTIBYTE
+#endif
+
+/*
+ * Long long formatting in scanf
+ *
+ * This setting controls whether scanf supports long long support (%lld). It
+ * also controls, if 'intmax_t' is larger than an ordinary 'long', i.e. how
+ * the %jd and %jn specifiers behaves. Set to 1 to support them, otherwise set
+ * to 0.
+ *
+ * Default is to support long long formatting in scanf.
+ */
+
+#ifndef _DLIB_SCANF_LONG_LONG
+ #ifdef __LONG_LONG_SIZE__
+ #define _DLIB_SCANF_LONG_LONG 1
+ #else
+ #define _DLIB_SCANF_LONG_LONG 0
+ #endif
+#endif
+
+#if _DLIB_SCANF_LONG_LONG && !defined(__LONG_LONG_SIZE__)
+#error "Long long support turned on for scanf, the compiler doesn't support long long though"
+#endif
+
+/*
+ * Support widths in scanf
+ *
+ * This controls whether scanf supports widths. Set to 1 to support them,
+ * otherwise set to 0.
+ *
+ * Default is to support widths in scanf.
+ */
+
+#ifndef _DLIB_SCANF_WIDTH
+#define _DLIB_SCANF_WIDTH 1
+#endif
+
+/*
+ * Support qualifiers [hjltzL] in scanf
+ *
+ * This setting controls whether scanf supports qualifiers [hjltzL] or not. Set
+ * to 1 to support them, otherwise set to 0.
+ *
+ * Default is to support qualifiers in scanf.
+ */
+
+#ifndef _DLIB_SCANF_QUALIFIERS
+#define _DLIB_SCANF_QUALIFIERS 1
+#endif
+
+/*
+ * Support floating-point formatting in scanf
+ *
+ * This setting controls whether scanf supports floating-point formatting. Set
+ * to 1 to support them, otherwise set to 0.
+ *
+ * Default is to support floating-point formatting in scanf.
+ */
+
+#ifndef _DLIB_SCANF_SPECIFIER_FLOAT
+#define _DLIB_SCANF_SPECIFIER_FLOAT 1
+#endif
+
+/*
+ * Support output count formatting (%n)
+ *
+ * This setting controls whether scanf supports output count formatting (%n).
+ * Set to 1 to support it, otherwise set to 0.
+ *
+ * Default is to support output count formatting in scanf.
+ */
+
+#ifndef _DLIB_SCANF_SPECIFIER_N
+#define _DLIB_SCANF_SPECIFIER_N 1
+#endif
+
+/*
+ * Support scansets ([]) in scanf
+ *
+ * This setting controls whether scanf supports scansets ([]) or not. Set to 1
+ * to support them, otherwise set to 0.
+ *
+ * Default is to support scansets in scanf.
+ */
+
+#ifndef _DLIB_SCANF_SPECIFIER_SCANSET
+#define _DLIB_SCANF_SPECIFIER_SCANSET 1
+#endif
+
+/*
+ * Support signed integer formatting in scanf
+ *
+ * This setting controls whether scanf supports signed integer formatting or
+ * not. Set to 1 to support them, otherwise set to 0.
+ *
+ * Default is to support signed integer formatting in scanf.
+ */
+
+#ifndef _DLIB_SCANF_SPECIFIER_SIGNED
+#define _DLIB_SCANF_SPECIFIER_SIGNED 1
+#endif
+
+/*
+ * Support unsigned integer formatting in scanf
+ *
+ * This setting controls whether scanf supports unsigned integer formatting or
+ * not. Set to 1 to support them, otherwise set to 0.
+ *
+ * Default is to support unsigned integer formatting in scanf.
+ */
+
+#ifndef _DLIB_SCANF_SPECIFIER_UNSIGNED
+#define _DLIB_SCANF_SPECIFIER_UNSIGNED 1
+#endif
+
+/*
+ * Support assignment suppressing [*] in scanf
+ *
+ * This setting controls whether scanf supports assignment suppressing [*] or
+ * not. Set to 1 to support them, otherwise set to 0.
+ *
+ * Default is to support assignment suppressing in scanf.
+ */
+
+#ifndef _DLIB_SCANF_ASSIGNMENT_SUPPRESSING
+#define _DLIB_SCANF_ASSIGNMENT_SUPPRESSING 1
+#endif
+
+/*
+ * Set Buffert size used in qsort
+ *
+ */
+
+#ifndef _DLIB_QSORT_BUF_SIZE
+#define _DLIB_QSORT_BUF_SIZE 256
+#endif
+
+#endif /* _DLIB_DEFAULTS_H */
diff --git a/AT91SAM7S256/SAM7S256/Include/Dlib_Product.h b/AT91SAM7S256/SAM7S256/Include/Dlib_Product.h
new file mode 100644
index 0000000..b56c243
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/Dlib_Product.h
@@ -0,0 +1,8 @@
+#ifndef _DLIB_PRODUCTS_H_
+#define _DLIB_PRODUCTS_H_
+
+/* Nothing needed here */
+
+#endif
+
+
diff --git a/AT91SAM7S256/SAM7S256/Include/ctype.h b/AT91SAM7S256/SAM7S256/Include/ctype.h
new file mode 100644
index 0000000..cd5ca53
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/ctype.h
@@ -0,0 +1,169 @@
+/* ctype.h standard header */
+#ifndef _CTYPE
+#define _CTYPE
+
+#ifndef _SYSTEM_BUILD
+ #pragma system_include
+#endif
+
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+
+#include <xlocale.h>
+
+_C_STD_BEGIN
+
+_C_LIB_DECL
+__INTRINSIC int isalnum(int);
+__INTRINSIC int isalpha(int);
+#if _DLIB_ADD_C99_SYMBOLS
+ __INTRINSIC int isblank(int);
+#endif /* _DLIB__ADD_C99_SYMBOLS */
+__INTRINSIC int iscntrl(int);
+__INTRINSIC int isdigit(int);
+__INTRINSIC int isgraph(int);
+__INTRINSIC int islower(int);
+__INTRINSIC int isprint(int);
+__INTRINSIC int ispunct(int);
+__INTRINSIC int isspace(int);
+__INTRINSIC int isupper(int);
+__INTRINSIC int isxdigit(int);
+__INTRINSIC int tolower(int);
+__INTRINSIC int toupper(int);
+_END_C_LIB_DECL
+
+#if _DLIB_ADD_C99_SYMBOLS
+ #pragma inline
+ int isblank(int _C)
+ {
+ return ( _C == ' '
+ || _C == '\t'
+ || isspace(_C));
+ }
+#endif /* _DLIB__ADD_C99_SYMBOLS */
+
+#pragma inline
+int isdigit(int _C)
+{
+ return _C >= '0' && _C <= '9';
+}
+
+#pragma inline
+int isxdigit(int _C)
+{
+ return ( (_C >= 'a' && _C <= 'f')
+ || (_C >= 'A' && _C <= 'F')
+ || isdigit(_C));
+}
+
+#pragma inline
+int isalnum(int _C)
+{
+ return ( isalpha(_C)
+ || isdigit(_C));
+}
+
+#pragma inline
+int isprint(int _C)
+{
+ return ( (_C >= ' ' && _C <= '\x7e')
+ || isalpha(_C)
+ || ispunct(_C));
+}
+
+#pragma inline
+int isgraph(int _C)
+{
+ return ( _C != ' '
+ && isprint(_C));
+}
+
+
+#if _DLIB_FULL_LOCALE_SUPPORT
+
+ /* In full support locale mode proxy functions are defined in each
+ * source file. */
+
+#else /* _DLIB_FULL_LOCALE_SUPPORT */
+
+ /* In non-full mode we redirect the corresponding locale function. */
+ _EXTERN_C
+ extern int _LOCALE_WITH_USED(toupper)(int);
+ extern int _LOCALE_WITH_USED(tolower)(int);
+ extern int _LOCALE_WITH_USED(isalpha)(int);
+ extern int _LOCALE_WITH_USED(iscntrl)(int);
+ extern int _LOCALE_WITH_USED(islower)(int);
+ extern int _LOCALE_WITH_USED(ispunct)(int);
+ extern int _LOCALE_WITH_USED(isspace)(int);
+ extern int _LOCALE_WITH_USED(isupper)(int);
+ _END_EXTERN_C
+
+ #pragma inline
+ int toupper(int _C)
+ {
+ return _LOCALE_WITH_USED(toupper)(_C);
+ }
+
+ #pragma inline
+ int tolower(int _C)
+ {
+ return _LOCALE_WITH_USED(tolower)(_C);
+ }
+
+ #pragma inline
+ int isalpha(int _C)
+ {
+ return _LOCALE_WITH_USED(isalpha)(_C);
+ }
+
+ #pragma inline
+ int iscntrl(int _C)
+ {
+ return _LOCALE_WITH_USED(iscntrl)(_C);
+ }
+
+ #pragma inline
+ int islower(int _C)
+ {
+ return _LOCALE_WITH_USED(islower)(_C);
+ }
+
+ #pragma inline
+ int ispunct(int _C)
+ {
+ return _LOCALE_WITH_USED(ispunct)(_C);
+ }
+
+ #pragma inline
+ int isspace(int _C)
+ {
+ return _LOCALE_WITH_USED(isspace)(_C);
+ }
+
+ #pragma inline
+ int isupper(int _C)
+ {
+ return _LOCALE_WITH_USED(isupper)(_C);
+ }
+
+#endif /* _DLIB_FULL_LOCALE_SUPPORT */
+
+_C_STD_END
+#endif /* _CTYPE */
+
+#ifdef _STD_USING
+ using _CSTD isalnum; using _CSTD isalpha; using _CSTD iscntrl;
+ using _CSTD isdigit; using _CSTD isgraph; using _CSTD islower;
+ using _CSTD isprint; using _CSTD ispunct; using _CSTD isspace;
+ using _CSTD isupper; using _CSTD isxdigit; using _CSTD tolower;
+ using _CSTD toupper;
+ #if _DLIB_ADD_C99_SYMBOLS
+ uisng _CSTD isblank;
+ #endif /* _DLIB__ADD_C99_SYMBOLS */
+#endif /* _STD_USING */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Include/ioat91sam7s64.h b/AT91SAM7S256/SAM7S256/Include/ioat91sam7s64.h
new file mode 100644
index 0000000..dd23bd2
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/ioat91sam7s64.h
@@ -0,0 +1,3307 @@
+// - ----------------------------------------------------------------------------
+// - ATMEL Microcontroller Software Support - ROUSSET -
+// - ----------------------------------------------------------------------------
+// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// - ----------------------------------------------------------------------------
+// - File Name : AT91SAM7S64.h
+// - Object : AT91SAM7S64 definitions
+// - Generated : AT91 SW Application Group 02/23/2005 (17:06:07)
+// -
+// - CVS Reference : /AT91SAM7S64.pl/1.18/Wed Feb 9 15:26:02 2005//
+// - CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005//
+// - CVS Reference : /MC_SAM7S.pl/1.2/Tue Feb 1 17:01:00 2005//
+// - CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005//
+// - CVS Reference : /RSTC_SAM7S.pl/1.1/Tue Feb 1 16:16:35 2005//
+// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
+// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
+// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
+// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
+// - CVS Reference : /UDP_6083C.pl/1.1/Mon Jan 31 13:01:46 2005//
+// - CVS Reference : /AIC_6075A.pl/1.1/Fri Jun 28 10:36:48 2002//
+// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
+// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// - CVS Reference : /SPI_6088D.pl/1.2/Mon Feb 14 07:24:18 2005//
+// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// - CVS Reference : /TC_6082A.pl/1.6/Fri Feb 18 13:53:30 2005//
+// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
+// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// - CVS Reference : /PWM_6044D.pl/1.1/Tue Apr 27 14:53:52 2004//
+// - ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7S64_H
+#define AT91SAM7S64_H
+
+#ifdef __IAR_SYSTEMS_ICC__
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved2[45]; //
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved3[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved4[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved5[54]; //
+ AT91_REG PIOA_PER; // PIO Enable Register
+ AT91_REG PIOA_PDR; // PIO Disable Register
+ AT91_REG PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved6[1]; //
+ AT91_REG PIOA_OER; // Output Enable Register
+ AT91_REG PIOA_ODR; // Output Disable Registerr
+ AT91_REG PIOA_OSR; // Output Status Register
+ AT91_REG Reserved7[1]; //
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved8[1]; //
+ AT91_REG PIOA_SODR; // Set Output Data Register
+ AT91_REG PIOA_CODR; // Clear Output Data Register
+ AT91_REG PIOA_ODSR; // Output Data Status Register
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
+ AT91_REG PIOA_IER; // Interrupt Enable Register
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
+ AT91_REG PIOA_ISR; // Interrupt Status Register
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved9[1]; //
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved10[1]; //
+ AT91_REG PIOA_ASR; // Select A Register
+ AT91_REG PIOA_BSR; // Select B Register
+ AT91_REG PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved11[9]; //
+ AT91_REG PIOA_OWER; // Output Write Enable Register
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
+ AT91_REG PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved12[469]; //
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved16[3]; //
+ AT91_REG PMC_PCKR[3]; // Programmable Clock Register
+ AT91_REG Reserved17[5]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved18[36]; //
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved19[5]; //
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+ AT91_REG Reserved20[5]; //
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG CKGR_PLLR; // PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PMC_PLLR; // PLL Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved3[3]; //
+ AT91_REG PMC_PCKR[3]; // Programmable Clock Register
+ AT91_REG Reserved4[5]; //
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+ AT91_REG VREG_MR; // Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+ AT91_REG MC_RCR; // MC Remap Control Register
+ AT91_REG MC_ASR; // MC Abort Status Register
+ AT91_REG MC_AASR; // MC Abort Address Status Register
+ AT91_REG Reserved0[21]; //
+ AT91_REG MC_FMR; // MC Flash Mode Register
+ AT91_REG MC_FCR; // MC Flash Command Register
+ AT91_REG MC_FSR; // MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word
+#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error
+#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error
+#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State
+#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
+#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
+#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
+#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command
+#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number
+#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+ AT91_REG ADC_CR; // ADC Control Register
+ AT91_REG ADC_MR; // ADC Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
+ AT91_REG ADC_SR; // ADC Status Register
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
+ AT91_REG Reserved1[44]; //
+ AT91_REG ADC_RPR; // Receive Pointer Register
+ AT91_REG ADC_RCR; // Receive Counter Register
+ AT91_REG ADC_TPR; // Transmit Pointer Register
+ AT91_REG ADC_TCR; // Transmit Counter Register
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
+#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
+#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
+#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
+#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
+#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
+#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+ AT91_REG SSC_CR; // Control Register
+ AT91_REG SSC_CMR; // Clock Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
+ AT91_REG SSC_RHR; // Receive Holding Register
+ AT91_REG SSC_THR; // Transmit Holding Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG SSC_SR; // Status Register
+ AT91_REG SSC_IER; // Interrupt Enable Register
+ AT91_REG SSC_IDR; // Interrupt Disable Register
+ AT91_REG SSC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved3[44]; //
+ AT91_REG SSC_RPR; // Receive Pointer Register
+ AT91_REG SSC_RCR; // Receive Counter Register
+ AT91_REG SSC_TPR; // Transmit Pointer Register
+ AT91_REG SSC_TCR; // Transmit Counter Register
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+ AT91_REG TWI_CR; // Control Register
+ AT91_REG TWI_MMR; // Master Mode Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG TWI_IADR; // Internal Address Register
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
+ AT91_REG Reserved1[3]; //
+ AT91_REG TWI_SR; // Status Register
+ AT91_REG TWI_IER; // Interrupt Enable Register
+ AT91_REG TWI_IDR; // Interrupt Disable Register
+ AT91_REG TWI_IMR; // Interrupt Mask Register
+ AT91_REG TWI_RHR; // Receive Holding Register
+ AT91_REG TWI_THR; // Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
+#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+ AT91_REG PWMC_CMR; // Channel Mode Register
+ AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
+ AT91_REG PWMC_CPRDR; // Channel Period Register
+ AT91_REG PWMC_CCNTR; // Channel Counter Register
+ AT91_REG PWMC_CUPDR; // Channel Update Register
+ AT91_REG PWMC_Reserved[3]; // Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH)
+#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH)
+#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+ AT91_REG PWMC_MR; // PWMC Mode Register
+ AT91_REG PWMC_ENA; // PWMC Enable Register
+ AT91_REG PWMC_DIS; // PWMC Disable Register
+ AT91_REG PWMC_SR; // PWMC Status Register
+ AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
+ AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
+ AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
+ AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
+ AT91_REG Reserved0[55]; //
+ AT91_REG PWMC_VR; // PWMC Version Register
+ AT91_REG Reserved1[64]; //
+ AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A
+#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC)
+#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC)
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3
+#define AT91C_PWMC_CHID4 ((unsigned int) 0x1 << 4) // (PWMC) Channel ID 4
+#define AT91C_PWMC_CHID5 ((unsigned int) 0x1 << 5) // (PWMC) Channel ID 5
+#define AT91C_PWMC_CHID6 ((unsigned int) 0x1 << 6) // (PWMC) Channel ID 6
+#define AT91C_PWMC_CHID7 ((unsigned int) 0x1 << 7) // (PWMC) Channel ID 7
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register
+ AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG UDP_TXVC; // Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt
+#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt
+#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5
+#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6
+#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ==========
+#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI peripheral ==========
+#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
+#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
+#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
+#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
+#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
+#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
+#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
+#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
+#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
+#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
+// ========== Register definition for SPI peripheral ==========
+#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
+#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register
+#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
+#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register
+#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
+#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
+#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
+#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
+#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_SSC peripheral ==========
+#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ==========
+#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for PWMC_CH3 peripheral ==========
+#define AT91C_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ==========
+#define AT91C_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ==========
+#define AT91C_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ==========
+#define AT91C_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ==========
+#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
+
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0
+#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1
+#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data
+#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
+#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0
+#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave
+#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1
+#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave
+#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2
+#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock
+#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3
+#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync
+#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock
+#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data
+#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data
+#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock
+#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input
+#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2
+#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock
+#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync
+#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0
+#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data
+#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1
+#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data
+#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock
+#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0
+#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send
+#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1
+#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send
+#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2
+#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect
+#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready
+#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready
+#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input
+#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator
+#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input
+#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data
+#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1
+#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
+#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock
+#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input
+#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data
+#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data
+#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0
+#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send
+#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3
+#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send
+#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger
+#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data
+#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
+
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral
+#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller
+#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved
+#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter
+#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface
+#define AT91C_ID_US0 ((unsigned int) 6) // USART 0
+#define AT91C_ID_US1 ((unsigned int) 7) // USART 1
+#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface
+#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved
+#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved
+#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved
+#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
+#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
+#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
+
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)
+#define AT91C_IFLASH ((char *) 0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte)
+#endif /* __IAR_SYSTEMS_ICC__ */
+
+#ifdef __IAR_SYSTEMS_ASM__
+
+// - Hardware register definition
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR System Peripherals
+// - *****************************************************************************
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// - *****************************************************************************
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level
+AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level
+AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level
+AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type
+AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label Level Sensitive
+AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Edge triggered
+AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) External Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) External Sources Code Label Positive Edge triggered
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status
+AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode
+AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// - *****************************************************************************
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable
+AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable
+AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable
+AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Debug Unit
+// - *****************************************************************************
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver
+AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter
+AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable
+AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable
+AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable
+AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable
+AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type
+AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity
+AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity
+AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space)
+AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark)
+AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity
+AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode
+AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode
+AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt
+AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt
+AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt
+AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt
+AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt
+AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt
+AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt
+AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt
+AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
+AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
+AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
+AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// - *****************************************************************************
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Clock Generator Controler
+// - *****************************************************************************
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable
+AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass
+AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency
+AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
+AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected
+AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0
+AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed
+AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter
+AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
+AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
+AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
+AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
+AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
+AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Power Management Controler
+// - *****************************************************************************
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock
+AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock
+AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection
+AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected
+AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected
+AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected
+AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler
+AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock
+AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2
+AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4
+AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8
+AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16
+AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32
+AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask
+AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask
+AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Reset Controller Interface
+// - *****************************************************************************
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset
+AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset
+AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset
+AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status
+AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status
+AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software.
+AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low.
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured.
+AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level
+AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable
+AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable
+AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Enable
+AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// - *****************************************************************************
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value
+AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
+AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
+AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status
+AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// - *****************************************************************************
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value
+AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
+AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value
+AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// - *****************************************************************************
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart
+AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
+AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
+AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
+AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
+AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
+AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow
+AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
+// - *****************************************************************************
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
+AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Memory Controller Interface
+// - *****************************************************************************
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status
+AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status
+AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status
+AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte
+AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word
+AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word
+AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status
+AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read
+AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write
+AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch
+AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
+AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
+AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
+AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
+AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready
+AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error
+AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error
+AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming
+AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State
+AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations
+AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations
+AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations
+AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations
+AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
+AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command
+AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
+AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
+AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.
+AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
+AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number
+AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
+AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status
+AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status
+AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status
+AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
+AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
+AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
+AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
+AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
+AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
+AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
+AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
+AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
+AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
+AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
+AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
+AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
+AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
+AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
+AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
+AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
+AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
+AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
+AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// - *****************************************************************************
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable
+AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable
+AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset
+AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode
+AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select
+AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select
+AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select
+AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode
+AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection
+AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection
+AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection
+AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
+AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data
+AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data
+AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full
+AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty
+AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error
+AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status
+AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt
+AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt
+AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt
+AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt
+AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity
+AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase
+AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer
+AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer
+AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer
+AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer
+AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer
+AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer
+AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer
+AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer
+AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer
+AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer
+AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer
+AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate
+AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Serial Clock Baud Rate
+AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// - *****************************************************************************
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset
+AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable
+AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
+AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection
+AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0
+AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1
+AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2
+AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3
+AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4
+AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5
+AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger
+AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution.
+AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution
+AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution
+AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode
+AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode
+AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection
+AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time
+AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time
+// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0
+AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1
+AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2
+AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3
+AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4
+AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5
+AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6
+AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7
+// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion
+AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion
+AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion
+AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion
+AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion
+AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion
+AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion
+AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion
+AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error
+AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready
+AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun
+AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
+AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// - *****************************************************************************
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable
+AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable
+AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable
+AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable
+AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection
+AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock
+AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal
+AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin
+AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
+AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
+AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion
+AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection
+AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start
+AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input
+AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input
+AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input
+AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input
+AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input
+AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input
+AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0
+AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
+AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length
+AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode
+AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First
+AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame
+AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
+AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
+AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value
+AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready
+AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty
+AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission
+AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty
+AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready
+AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun
+AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception
+AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full
+AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync
+AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync
+AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable
+AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Usart
+// - *****************************************************************************
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break
+AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break
+AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out
+AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address
+AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations
+AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
+AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out
+AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
+AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
+AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable
+AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode
+AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal
+AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485
+AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking
+AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
+AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA
+AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking
+AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock
+AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1
+AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM)
+AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK)
+AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits
+AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits
+AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits
+AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits
+AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select
+AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits
+AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit
+AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits
+AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order
+AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length
+AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select
+AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode
+AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
+AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK
+AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions
+AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break
+AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out
+AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
+AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge
+AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
+AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
+AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag
+AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input
+AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input
+AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input
+AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Two-wire Interface
+// - *****************************************************************************
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition
+AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition
+AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled
+AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled
+AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size
+AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address
+AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address
+AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address
+AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address
+AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction
+AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider
+AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider
+AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed
+AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY
+AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY
+AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error
+AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error
+AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// - *****************************************************************************
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command
+AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command
+AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
+AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0
+AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1
+AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2
+AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert
+AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection
+AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal
+AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock
+AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock
+AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock
+AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare
+AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading
+AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare
+AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading
+AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection
+AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None
+AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge
+AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge
+AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge
+AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection
+AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None
+AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge
+AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge
+AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge
+AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection
+AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
+AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
+AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
+AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
+AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
+AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable
+AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection
+AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
+AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
+AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC)
+AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
+AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none
+AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set
+AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear
+AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle
+AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection
+AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None
+AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
+AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none
+AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set
+AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear
+AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle
+AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection
+AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None
+AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
+AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none
+AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set
+AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear
+AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle
+AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
+AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none
+AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set
+AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear
+AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle
+AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
+AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none
+AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set
+AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear
+AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle
+AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
+AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none
+AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set
+AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear
+AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle
+AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
+AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none
+AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set
+AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear
+AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle
+AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
+AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none
+AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set
+AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear
+AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow
+AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun
+AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare
+AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare
+AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare
+AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading
+AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading
+AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger
+AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling
+AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror
+AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Timer Counter Interface
+// - *****************************************************************************
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection
+AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0
+AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0
+AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0
+AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0
+AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection
+AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1
+AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1
+AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1
+AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1
+AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection
+AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2
+AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2
+AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2
+AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR PWMC Channel Interface
+// - *****************************************************************************
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
+AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH)
+AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH)
+AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH)
+AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment
+AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity
+AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
+AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
+AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
+AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
+AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
+// - *****************************************************************************
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
+AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor.
+AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A
+AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC)
+AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
+AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
+AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC)
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
+AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0
+AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1
+AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2
+AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3
+AT91C_PWMC_CHID4 EQU (0x1 << 4) ;- (PWMC) Channel ID 4
+AT91C_PWMC_CHID5 EQU (0x1 << 5) ;- (PWMC) Channel ID 5
+AT91C_PWMC_CHID6 EQU (0x1 << 6) ;- (PWMC) Channel ID 6
+AT91C_PWMC_CHID7 EQU (0x1 << 7) ;- (PWMC) Channel ID 7
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
+
+// - *****************************************************************************
+// - SOFTWARE API DEFINITION FOR USB Device Interface
+// - *****************************************************************************
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
+AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error
+AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable
+AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured
+AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume
+AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host
+AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value
+AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt
+AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt
+AT91C_UDP_EPINT4 EQU (0x1 << 4) ;- (UDP) Endpoint 4 Interrupt
+AT91C_UDP_EPINT5 EQU (0x1 << 5) ;- (UDP) Endpoint 5 Interrupt
+AT91C_UDP_EPINT6 EQU (0x1 << 6) ;- (UDP) Endpoint 6 Interrupt
+AT91C_UDP_EPINT7 EQU (0x1 << 7) ;- (UDP) Endpoint 7 Interrupt
+AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt
+AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt
+AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
+AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
+AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0
+AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1
+AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2
+AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3
+AT91C_UDP_EP4 EQU (0x1 << 4) ;- (UDP) Reset Endpoint 4
+AT91C_UDP_EP5 EQU (0x1 << 5) ;- (UDP) Reset Endpoint 5
+AT91C_UDP_EP6 EQU (0x1 << 6) ;- (UDP) Reset Endpoint 6
+AT91C_UDP_EP7 EQU (0x1 << 7) ;- (UDP) Reset Endpoint 7
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR
+AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0
+AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints)
+AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints)
+AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready
+AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction
+AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type
+AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control
+AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT
+AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT
+AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN
+AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN
+AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN
+AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle
+AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
+AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP)
+AT91C_UDP_PUON EQU (0x1 << 9) ;- (UDP) Pull-up ON
+
+// - *****************************************************************************
+// - REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
+// - *****************************************************************************
+// - ========== Register definition for SYS peripheral ==========
+// - ========== Register definition for AIC peripheral ==========
+AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
+AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register
+AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
+AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
+AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
+AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register
+AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
+AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
+AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
+AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
+AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
+AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
+AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
+AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
+AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
+AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
+AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
+AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
+// - ========== Register definition for PDC_DBGU peripheral ==========
+AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
+AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
+AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
+AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
+AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
+AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
+AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
+AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
+AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
+AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
+// - ========== Register definition for DBGU peripheral ==========
+AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
+AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
+AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
+AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
+AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
+AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register
+AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
+AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register
+AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
+AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
+AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
+AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
+// - ========== Register definition for PIOA peripheral ==========
+AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
+AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
+AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
+AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
+AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
+AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
+AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
+AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
+AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
+AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
+AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
+AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
+AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
+AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
+AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
+AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register
+AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
+AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
+AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
+AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
+AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register
+AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register
+AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
+AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
+AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
+AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
+AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
+AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
+AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
+// - ========== Register definition for CKGR peripheral ==========
+AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
+AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
+AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register
+// - ========== Register definition for PMC peripheral ==========
+AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
+AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
+AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register
+AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
+AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
+AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
+AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
+AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
+AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
+AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
+AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register
+AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
+AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
+AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
+AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register
+// - ========== Register definition for RSTC peripheral ==========
+AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
+AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
+AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
+// - ========== Register definition for RTTC peripheral ==========
+AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
+AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
+AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
+AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
+// - ========== Register definition for PITC peripheral ==========
+AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
+AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
+AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
+AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
+// - ========== Register definition for WDTC peripheral ==========
+AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
+AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
+AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
+// - ========== Register definition for VREG peripheral ==========
+AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
+// - ========== Register definition for MC peripheral ==========
+AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
+AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
+AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
+AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
+AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
+AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
+// - ========== Register definition for PDC_SPI peripheral ==========
+AT91C_SPI_PTCR EQU (0xFFFE0120) ;- (PDC_SPI) PDC Transfer Control Register
+AT91C_SPI_TPR EQU (0xFFFE0108) ;- (PDC_SPI) Transmit Pointer Register
+AT91C_SPI_TCR EQU (0xFFFE010C) ;- (PDC_SPI) Transmit Counter Register
+AT91C_SPI_RCR EQU (0xFFFE0104) ;- (PDC_SPI) Receive Counter Register
+AT91C_SPI_PTSR EQU (0xFFFE0124) ;- (PDC_SPI) PDC Transfer Status Register
+AT91C_SPI_RNPR EQU (0xFFFE0110) ;- (PDC_SPI) Receive Next Pointer Register
+AT91C_SPI_RPR EQU (0xFFFE0100) ;- (PDC_SPI) Receive Pointer Register
+AT91C_SPI_TNCR EQU (0xFFFE011C) ;- (PDC_SPI) Transmit Next Counter Register
+AT91C_SPI_RNCR EQU (0xFFFE0114) ;- (PDC_SPI) Receive Next Counter Register
+AT91C_SPI_TNPR EQU (0xFFFE0118) ;- (PDC_SPI) Transmit Next Pointer Register
+// - ========== Register definition for SPI peripheral ==========
+AT91C_SPI_IER EQU (0xFFFE0014) ;- (SPI) Interrupt Enable Register
+AT91C_SPI_SR EQU (0xFFFE0010) ;- (SPI) Status Register
+AT91C_SPI_IDR EQU (0xFFFE0018) ;- (SPI) Interrupt Disable Register
+AT91C_SPI_CR EQU (0xFFFE0000) ;- (SPI) Control Register
+AT91C_SPI_MR EQU (0xFFFE0004) ;- (SPI) Mode Register
+AT91C_SPI_IMR EQU (0xFFFE001C) ;- (SPI) Interrupt Mask Register
+AT91C_SPI_TDR EQU (0xFFFE000C) ;- (SPI) Transmit Data Register
+AT91C_SPI_RDR EQU (0xFFFE0008) ;- (SPI) Receive Data Register
+AT91C_SPI_CSR EQU (0xFFFE0030) ;- (SPI) Chip Select Register
+// - ========== Register definition for PDC_ADC peripheral ==========
+AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
+AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
+AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
+AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
+AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
+AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
+AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
+AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
+AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
+AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
+// - ========== Register definition for ADC peripheral ==========
+AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
+AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
+AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
+AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
+AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
+AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register
+AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
+AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
+AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
+AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
+AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register
+AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
+AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
+AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
+AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
+AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
+AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
+AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
+// - ========== Register definition for PDC_SSC peripheral ==========
+AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
+AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
+AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
+AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
+AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
+AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
+AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
+AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
+AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
+AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
+// - ========== Register definition for SSC peripheral ==========
+AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
+AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
+AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
+AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
+AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
+AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
+AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
+AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
+AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register
+AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
+AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
+AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register
+AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
+AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
+// - ========== Register definition for PDC_US1 peripheral ==========
+AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
+AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
+AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
+AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
+AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
+AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
+AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
+AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
+AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
+AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
+// - ========== Register definition for US1 peripheral ==========
+AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
+AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register
+AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
+AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register
+AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
+AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
+AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
+AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
+AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
+AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
+AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
+AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
+AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register
+AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register
+// - ========== Register definition for PDC_US0 peripheral ==========
+AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
+AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
+AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
+AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
+AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
+AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
+AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
+AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
+AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
+AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
+// - ========== Register definition for US0 peripheral ==========
+AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
+AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register
+AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register
+AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
+AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
+AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
+AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register
+AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
+AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register
+AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
+AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
+AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
+AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
+AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
+// - ========== Register definition for TWI peripheral ==========
+AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
+AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register
+AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register
+AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
+AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
+AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
+AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register
+AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register
+AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
+AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
+// - ========== Register definition for TC0 peripheral ==========
+AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register
+AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C
+AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B
+AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register
+AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
+AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A
+AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
+AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value
+AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
+// - ========== Register definition for TC1 peripheral ==========
+AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B
+AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register
+AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
+AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
+AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register
+AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A
+AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C
+AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
+AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value
+// - ========== Register definition for TC2 peripheral ==========
+AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register
+AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value
+AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A
+AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B
+AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
+AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
+AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C
+AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
+AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register
+// - ========== Register definition for TCB peripheral ==========
+AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
+AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
+// - ========== Register definition for PWMC_CH3 peripheral ==========
+AT91C_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
+AT91C_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
+AT91C_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
+AT91C_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
+AT91C_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
+AT91C_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
+// - ========== Register definition for PWMC_CH2 peripheral ==========
+AT91C_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
+AT91C_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
+AT91C_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
+AT91C_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
+AT91C_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
+AT91C_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
+// - ========== Register definition for PWMC_CH1 peripheral ==========
+AT91C_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
+AT91C_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
+AT91C_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
+AT91C_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
+AT91C_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
+AT91C_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
+// - ========== Register definition for PWMC_CH0 peripheral ==========
+AT91C_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
+AT91C_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
+AT91C_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
+AT91C_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
+AT91C_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
+AT91C_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
+// - ========== Register definition for PWMC peripheral ==========
+AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
+AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
+AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
+AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
+AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
+AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
+AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
+AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
+AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
+// - ========== Register definition for UDP peripheral ==========
+AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
+AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register
+AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register
+AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
+AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
+AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
+AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
+AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
+AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
+AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
+AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register
+AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
+
+// - *****************************************************************************
+// - PIO DEFINITIONS FOR AT91SAM7S64
+// - *****************************************************************************
+AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0
+AT91C_PA0_PWM0 EQU (AT91C_PIO_PA0) ;- PWM Channel 0
+AT91C_PA0_TIOA0 EQU (AT91C_PIO_PA0) ;- Timer Counter 0 Multipurpose Timer I/O Pin A
+AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1
+AT91C_PA1_PWM1 EQU (AT91C_PIO_PA1) ;- PWM Channel 1
+AT91C_PA1_TIOB0 EQU (AT91C_PIO_PA1) ;- Timer Counter 0 Multipurpose Timer I/O Pin B
+AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10
+AT91C_PA10_DTXD EQU (AT91C_PIO_PA10) ;- DBGU Debug Transmit Data
+AT91C_PA10_NPCS2 EQU (AT91C_PIO_PA10) ;- SPI Peripheral Chip Select 2
+AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11
+AT91C_PA11_NPCS0 EQU (AT91C_PIO_PA11) ;- SPI Peripheral Chip Select 0
+AT91C_PA11_PWM0 EQU (AT91C_PIO_PA11) ;- PWM Channel 0
+AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12
+AT91C_PA12_MISO EQU (AT91C_PIO_PA12) ;- SPI Master In Slave
+AT91C_PA12_PWM1 EQU (AT91C_PIO_PA12) ;- PWM Channel 1
+AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13
+AT91C_PA13_MOSI EQU (AT91C_PIO_PA13) ;- SPI Master Out Slave
+AT91C_PA13_PWM2 EQU (AT91C_PIO_PA13) ;- PWM Channel 2
+AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14
+AT91C_PA14_SPCK EQU (AT91C_PIO_PA14) ;- SPI Serial Clock
+AT91C_PA14_PWM3 EQU (AT91C_PIO_PA14) ;- PWM Channel 3
+AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15
+AT91C_PA15_TF EQU (AT91C_PIO_PA15) ;- SSC Transmit Frame Sync
+AT91C_PA15_TIOA1 EQU (AT91C_PIO_PA15) ;- Timer Counter 1 Multipurpose Timer I/O Pin A
+AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16
+AT91C_PA16_TK EQU (AT91C_PIO_PA16) ;- SSC Transmit Clock
+AT91C_PA16_TIOB1 EQU (AT91C_PIO_PA16) ;- Timer Counter 1 Multipurpose Timer I/O Pin B
+AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17
+AT91C_PA17_TD EQU (AT91C_PIO_PA17) ;- SSC Transmit data
+AT91C_PA17_PCK1 EQU (AT91C_PIO_PA17) ;- PMC Programmable Clock Output 1
+AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18
+AT91C_PA18_RD EQU (AT91C_PIO_PA18) ;- SSC Receive Data
+AT91C_PA18_PCK2 EQU (AT91C_PIO_PA18) ;- PMC Programmable Clock Output 2
+AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19
+AT91C_PA19_RK EQU (AT91C_PIO_PA19) ;- SSC Receive Clock
+AT91C_PA19_FIQ EQU (AT91C_PIO_PA19) ;- AIC Fast Interrupt Input
+AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2
+AT91C_PA2_PWM2 EQU (AT91C_PIO_PA2) ;- PWM Channel 2
+AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock
+AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20
+AT91C_PA20_RF EQU (AT91C_PIO_PA20) ;- SSC Receive Frame Sync
+AT91C_PA20_IRQ0 EQU (AT91C_PIO_PA20) ;- External Interrupt 0
+AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21
+AT91C_PA21_RXD1 EQU (AT91C_PIO_PA21) ;- USART 1 Receive Data
+AT91C_PA21_PCK1 EQU (AT91C_PIO_PA21) ;- PMC Programmable Clock Output 1
+AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22
+AT91C_PA22_TXD1 EQU (AT91C_PIO_PA22) ;- USART 1 Transmit Data
+AT91C_PA22_NPCS3 EQU (AT91C_PIO_PA22) ;- SPI Peripheral Chip Select 3
+AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23
+AT91C_PA23_SCK1 EQU (AT91C_PIO_PA23) ;- USART 1 Serial Clock
+AT91C_PA23_PWM0 EQU (AT91C_PIO_PA23) ;- PWM Channel 0
+AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24
+AT91C_PA24_RTS1 EQU (AT91C_PIO_PA24) ;- USART 1 Ready To Send
+AT91C_PA24_PWM1 EQU (AT91C_PIO_PA24) ;- PWM Channel 1
+AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25
+AT91C_PA25_CTS1 EQU (AT91C_PIO_PA25) ;- USART 1 Clear To Send
+AT91C_PA25_PWM2 EQU (AT91C_PIO_PA25) ;- PWM Channel 2
+AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26
+AT91C_PA26_DCD1 EQU (AT91C_PIO_PA26) ;- USART 1 Data Carrier Detect
+AT91C_PA26_TIOA2 EQU (AT91C_PIO_PA26) ;- Timer Counter 2 Multipurpose Timer I/O Pin A
+AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27
+AT91C_PA27_DTR1 EQU (AT91C_PIO_PA27) ;- USART 1 Data Terminal ready
+AT91C_PA27_TIOB2 EQU (AT91C_PIO_PA27) ;- Timer Counter 2 Multipurpose Timer I/O Pin B
+AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28
+AT91C_PA28_DSR1 EQU (AT91C_PIO_PA28) ;- USART 1 Data Set ready
+AT91C_PA28_TCLK1 EQU (AT91C_PIO_PA28) ;- Timer Counter 1 external clock input
+AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29
+AT91C_PA29_RI1 EQU (AT91C_PIO_PA29) ;- USART 1 Ring Indicator
+AT91C_PA29_TCLK2 EQU (AT91C_PIO_PA29) ;- Timer Counter 2 external clock input
+AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3
+AT91C_PA3_TWD EQU (AT91C_PIO_PA3) ;- TWI Two-wire Serial Data
+AT91C_PA3_NPCS3 EQU (AT91C_PIO_PA3) ;- SPI Peripheral Chip Select 3
+AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30
+AT91C_PA30_IRQ1 EQU (AT91C_PIO_PA30) ;- External Interrupt 1
+AT91C_PA30_NPCS2 EQU (AT91C_PIO_PA30) ;- SPI Peripheral Chip Select 2
+AT91C_PIO_PA31 EQU (1 << 31) ;- Pin Controlled by PA31
+AT91C_PA31_NPCS1 EQU (AT91C_PIO_PA31) ;- SPI Peripheral Chip Select 1
+AT91C_PA31_PCK2 EQU (AT91C_PIO_PA31) ;- PMC Programmable Clock Output 2
+AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4
+AT91C_PA4_TWCK EQU (AT91C_PIO_PA4) ;- TWI Two-wire Serial Clock
+AT91C_PA4_TCLK0 EQU (AT91C_PIO_PA4) ;- Timer Counter 0 external clock input
+AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5
+AT91C_PA5_RXD0 EQU (AT91C_PIO_PA5) ;- USART 0 Receive Data
+AT91C_PA5_NPCS3 EQU (AT91C_PIO_PA5) ;- SPI Peripheral Chip Select 3
+AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6
+AT91C_PA6_TXD0 EQU (AT91C_PIO_PA6) ;- USART 0 Transmit Data
+AT91C_PA6_PCK0 EQU (AT91C_PIO_PA6) ;- PMC Programmable Clock Output 0
+AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7
+AT91C_PA7_RTS0 EQU (AT91C_PIO_PA7) ;- USART 0 Ready To Send
+AT91C_PA7_PWM3 EQU (AT91C_PIO_PA7) ;- PWM Channel 3
+AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8
+AT91C_PA8_CTS0 EQU (AT91C_PIO_PA8) ;- USART 0 Clear To Send
+AT91C_PA8_ADTRG EQU (AT91C_PIO_PA8) ;- ADC External Trigger
+AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9
+AT91C_PA9_DRXD EQU (AT91C_PIO_PA9) ;- DBGU Debug Receive Data
+AT91C_PA9_NPCS1 EQU (AT91C_PIO_PA9) ;- SPI Peripheral Chip Select 1
+
+// - *****************************************************************************
+// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
+// - *****************************************************************************
+AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
+AT91C_ID_SYS EQU ( 1) ;- System Peripheral
+AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller
+AT91C_ID_3_Reserved EQU ( 3) ;- Reserved
+AT91C_ID_ADC EQU ( 4) ;- Analog-to-Digital Converter
+AT91C_ID_SPI EQU ( 5) ;- Serial Peripheral Interface
+AT91C_ID_US0 EQU ( 6) ;- USART 0
+AT91C_ID_US1 EQU ( 7) ;- USART 1
+AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller
+AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface
+AT91C_ID_PWMC EQU (10) ;- PWM Controller
+AT91C_ID_UDP EQU (11) ;- USB Device Port
+AT91C_ID_TC0 EQU (12) ;- Timer Counter 0
+AT91C_ID_TC1 EQU (13) ;- Timer Counter 1
+AT91C_ID_TC2 EQU (14) ;- Timer Counter 2
+AT91C_ID_15_Reserved EQU (15) ;- Reserved
+AT91C_ID_16_Reserved EQU (16) ;- Reserved
+AT91C_ID_17_Reserved EQU (17) ;- Reserved
+AT91C_ID_18_Reserved EQU (18) ;- Reserved
+AT91C_ID_19_Reserved EQU (19) ;- Reserved
+AT91C_ID_20_Reserved EQU (20) ;- Reserved
+AT91C_ID_21_Reserved EQU (21) ;- Reserved
+AT91C_ID_22_Reserved EQU (22) ;- Reserved
+AT91C_ID_23_Reserved EQU (23) ;- Reserved
+AT91C_ID_24_Reserved EQU (24) ;- Reserved
+AT91C_ID_25_Reserved EQU (25) ;- Reserved
+AT91C_ID_26_Reserved EQU (26) ;- Reserved
+AT91C_ID_27_Reserved EQU (27) ;- Reserved
+AT91C_ID_28_Reserved EQU (28) ;- Reserved
+AT91C_ID_29_Reserved EQU (29) ;- Reserved
+AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0)
+AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1)
+
+// - *****************************************************************************
+// - BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
+// - *****************************************************************************
+AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address
+AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address
+AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
+AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address
+AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address
+AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address
+AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address
+AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address
+AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address
+AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address
+AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address
+AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address
+AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address
+AT91C_BASE_PDC_SPI EQU (0xFFFE0100) ;- (PDC_SPI) Base Address
+AT91C_BASE_SPI EQU (0xFFFE0000) ;- (SPI) Base Address
+AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
+AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address
+AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
+AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address
+AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address
+AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address
+AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address
+AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address
+AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address
+AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address
+AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address
+AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address
+AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address
+AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
+AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
+AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
+AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
+AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address
+AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address
+
+// - *****************************************************************************
+// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
+// - *****************************************************************************
+AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address
+AT91C_ISRAM_SIZE EQU (0x00004000) ;- Internal SRAM size in byte (16 Kbyte)
+AT91C_IFLASH EQU (0x00100000) ;- Internal ROM base address
+AT91C_IFLASH_SIZE EQU (0x00010000) ;- Internal ROM size in byte (64 Kbyte)
+#endif /* __IAR_SYSTEMS_ASM__ */
+
+
+#endif /* AT91SAM7S64_H */
diff --git a/AT91SAM7S256/SAM7S256/Include/lib_at91sam7s64.h b/AT91SAM7S256/SAM7S256/Include/lib_at91sam7s64.h
new file mode 100644
index 0000000..85d2e69
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/lib_at91sam7s64.h
@@ -0,0 +1,3664 @@
+//* ----------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name : lib_AT91SAM7S64.h
+//* Object : AT91SAM7S64 inlined functions
+//* Generated : AT91 SW Application Group 02/23/2005 (17:06:08)
+//*
+//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference : /lib_pmc_SAM7S.h/1.1/Tue Feb 1 08:32:10 2005//
+//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005//
+//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004//
+//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004//
+//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004//
+//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 08:46:12 2002//
+//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004//
+//* CVS Reference : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference : /lib_MC_SAM7S.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+#ifndef lib_AT91SAM7S64_H
+#define lib_AT91SAM7S64_H
+
+/* *****************************************************************************
+ SOFTWARE API FOR AIC
+ ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id, // \arg interrupt number to initialize
+ unsigned int priority, // \arg priority to give to the interrupt
+ unsigned int src_type, // \arg activation and sense of activation
+ void (*newHandler) (void) ) // \arg address of the interrupt handler
+{
+ unsigned int oldHandler;
+ unsigned int mask ;
+
+ oldHandler = pAic->AIC_SVR[irq_id];
+
+ mask = 0x1 << irq_id ;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Save the interrupt handler routine pointer and the interrupt priority
+ pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+ //* Store the Source Mode Register
+ pAic->AIC_SMR[irq_id] = src_type | priority ;
+ //* Clear the interrupt on the interrupt controller
+ pAic->AIC_ICCR = mask ;
+
+ return oldHandler;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
+{
+ //* Enable the interrupt on the interrupt controller
+ pAic->AIC_IECR = 0x1 << irq_id ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id ) // \arg interrupt number to initialize
+{
+ unsigned int mask = 0x1 << irq_id;
+ //* Disable the interrupt on the interrupt controller
+ pAic->AIC_IDCR = mask ;
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = mask ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number to initialize
+{
+ //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+ pAic->AIC_ICCR = (0x1 << irq_id);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+ AT91PS_AIC pAic) // \arg pointer to the AIC registers
+{
+ pAic->AIC_EOICR = pAic->AIC_EOICR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_SetExceptionVector (
+ unsigned int *pVector, // \arg pointer to the AIC registers
+ void (*Handler) () ) // \arg Interrupt Handler
+{
+ unsigned int oldVector = *pVector;
+
+ if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+ *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+ else
+ *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
+
+ return oldVector;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Trig (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg interrupt number
+{
+ pAic->AIC_ISCR = (0x1 << irq_id) ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsActive (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
+{
+ return (pAic->AIC_ISR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_IsPending (
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ unsigned int irq_id) // \arg Interrupt Number
+{
+ return (pAic->AIC_IPR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+ AT91PS_AIC pAic, // \arg pointer to the AIC registers
+ void (*IrqHandler) (), // \arg Default IRQ vector exception
+ void (*FiqHandler) (), // \arg Default FIQ vector exception
+ void (*DefaultHandler) (), // \arg Default Handler set in ISR
+ void (*SpuriousHandler) (), // \arg Default Spurious Handler
+ unsigned int protectMode) // \arg Debug Control Register
+{
+ int i;
+
+ // Disable all interrupts and set IVR to the default handler
+ for (i = 0; i < 32; ++i) {
+ AT91F_AIC_DisableIt(pAic, i);
+ AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);
+ }
+
+ // Set the IRQ exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+ // Set the Fast Interrupt exception vector
+ AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
+
+ pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+ pAic->AIC_DCR = protectMode;
+}
+/* *****************************************************************************
+ SOFTWARE API FOR PDC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RNPR = (unsigned int) address;
+ pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TNPR = (unsigned int) address;
+ pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RPR = (unsigned int) address;
+ pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TPR = (unsigned int) address;
+ pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
+{
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
+
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+ //* Enable the RX and TX PDC transfer requests
+ AT91F_PDC_EnableRx(pPDC);
+ AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
+{
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
+
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ if (AT91F_PDC_IsTxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+ AT91PS_PDC pPDC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ if (AT91F_PDC_IsRxEmpty(pPDC)) {
+ //* Buffer and next buffer can be initialized
+ AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+ AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+ return 2;
+ }
+ else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+ //* Only one buffer can be initialized
+ AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+ return 1;
+ }
+ else {
+ //* All buffer are in use...
+ return 0;
+ }
+}
+/* *****************************************************************************
+ SOFTWARE API FOR DBGU
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be enabled
+{
+ pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg dbgu interrupt to be disabled
+{
+ pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+ AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller
+{
+ return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+ AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR PIO
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int periphAEnable, // \arg PERIPH A to enable
+ unsigned int periphBEnable) // \arg PERIPH B to enable
+
+{
+ pPio->PIO_ASR = periphAEnable;
+ pPio->PIO_BSR = periphBEnable;
+ pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pioEnable) // \arg PIO to be enabled
+{
+ pPio->PIO_PER = pioEnable; // Set in PIO mode
+ pPio->PIO_OER = pioEnable; // Configure in Output
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputEnable) // \arg PIO to be enabled
+{
+ // Disable output
+ pPio->PIO_ODR = inputEnable;
+ pPio->PIO_PER = inputEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int multiDrvEnable) // \arg pio to be configured in open drain
+{
+ // Configure the multi-drive option
+ pPio->PIO_MDDR = ~multiDrvEnable;
+ pPio->PIO_MDER = multiDrvEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int pullupEnable) // \arg enable pullup on PIO
+{
+ // Connect or not Pullup
+ pPio->PIO_PPUDR = ~pullupEnable;
+ pPio->PIO_PPUER = pullupEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int directDrive) // \arg PIO to be configured with direct drive
+
+{
+ // Configure the Direct Drive
+ pPio->PIO_OWDR = ~directDrive;
+ pPio->PIO_OWER = directDrive;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int inputFilter) // \arg PIO to be configured with input filter
+
+{
+ // Configure the Direct Drive
+ pPio->PIO_IFDR = ~inputFilter;
+ pPio->PIO_IFER = inputFilter;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_PDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInput(pPio) & flag);
+}
+
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be set
+{
+ pPio->PIO_SODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be cleared
+{
+ pPio->PIO_CODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg output to be forced
+{
+ pPio->PIO_ODSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
+{
+ pPio->PIO_PER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
+{
+ pPio->PIO_PDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_PSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be enabled
+{
+ pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output to be disabled
+{
+ pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be enabled
+{
+ pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio input filter to be disabled
+{
+ pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be enabled
+{
+ pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio interrupt to be disabled
+{
+ pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be enabled
+{
+ pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio to be disabled
+{
+ pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio A register selection
+{
+ pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio B register selection
+{
+ pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be enabled
+{
+ pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg pio output write to be disabled
+{
+ pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
+ AT91PS_PIO pPio) // \arg pointer to a PIO controller
+{
+ return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR PMC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
+{
+ //* Write to the SCER register
+ pPMC->PMC_SCER = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
+{
+ //* Write to the SCDR register
+ pPMC->PMC_SCDR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+ AT91PS_PMC pPMC // pointer to a CAN controller
+ )
+{
+ return pPMC->PMC_SCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
+{
+ pPMC->PMC_PCER = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
+{
+ pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+ return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int mode)
+{
+ pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int startup_time, // \arg main osc startup time in microsecond (us)
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+ pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+ AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+ return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int mode)
+{
+ pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+ AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+ return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+ unsigned int slowClock) // \arg slowClock in Hz
+{
+ unsigned int reg = pPMC->PMC_MCKR;
+ unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+ unsigned int pllDivider, pllMultiplier;
+
+ switch (reg & AT91C_PMC_CSS) {
+ case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+ return slowClock / prescaler;
+ case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+ case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+ reg = pCKGR->CKGR_PLLR;
+ pllDivider = (reg & AT91C_CKGR_DIV);
+ pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;
+ return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+ }
+ return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck, // \arg Peripheral clock identifier 0 .. 7
+ unsigned int mode)
+{
+ pPMC->PMC_PCKR[pck] = mode;
+ pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int pck) // \arg Peripheral clock identifier 0 .. 7
+{
+ pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be enabled
+{
+ //* Write to the IER register
+ pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+ AT91PS_PMC pPMC, // pointer to a PMC controller
+ unsigned int flag) // IT to be disabled
+{
+ //* Write to the IDR register
+ pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+ return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+ AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+ return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+ AT91PS_PMC pPMC, // \arg pointer to a PMC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+ SOFTWARE API FOR RSTC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTSoftReset
+//* \brief Start Software Reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSoftReset(
+ AT91PS_RSTC pRSTC,
+ unsigned int reset)
+{
+ pRSTC->RSTC_RCR = (0xA5000000 | reset);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTSetMode
+//* \brief Set Reset Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSetMode(
+ AT91PS_RSTC pRSTC,
+ unsigned int mode)
+{
+ pRSTC->RSTC_RMR = (0xA5000000 | mode);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTGetMode
+//* \brief Get Reset Mode
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetMode(
+ AT91PS_RSTC pRSTC)
+{
+ return (pRSTC->RSTC_RMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTGetStatus
+//* \brief Get Reset Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetStatus(
+ AT91PS_RSTC pRSTC)
+{
+ return (pRSTC->RSTC_RSR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTIsSoftRstActive
+//* \brief Return !=0 if software reset is still not completed
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTIsSoftRstActive(
+ AT91PS_RSTC pRSTC)
+{
+ return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
+}
+/* *****************************************************************************
+ SOFTWARE API FOR RTTC
+ ***************************************************************************** */
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_SetRTT_TimeBase()
+//* \brief Set the RTT prescaler according to the TimeBase in ms
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetTimeBase(
+ AT91PS_RTTC pRTTC,
+ unsigned int ms)
+{
+ if (ms > 2000)
+ return 1; // AT91C_TIME_OUT_OF_RANGE
+ pRTTC->RTTC_RTMR &= ~0xFFFF;
+ pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);
+ return 0;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTSetPrescaler()
+//* \brief Set the new prescaler value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetPrescaler(
+ AT91PS_RTTC pRTTC,
+ unsigned int rtpres)
+{
+ pRTTC->RTTC_RTMR &= ~0xFFFF;
+ pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);
+ return (pRTTC->RTTC_RTMR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTRestart()
+//* \brief Restart the RTT prescaler
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTRestart(
+ AT91PS_RTTC pRTTC)
+{
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;
+}
+
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetAlarmINT()
+//* \brief Enable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmINT(
+ AT91PS_RTTC pRTTC)
+{
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ClearAlarmINT()
+//* \brief Disable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearAlarmINT(
+ AT91PS_RTTC pRTTC)
+{
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetRttIncINT()
+//* \brief Enable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetRttIncINT(
+ AT91PS_RTTC pRTTC)
+{
+ pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ClearRttIncINT()
+//* \brief Disable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearRttIncINT(
+ AT91PS_RTTC pRTTC)
+{
+ pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_SetAlarmValue()
+//* \brief Set RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmValue(
+ AT91PS_RTTC pRTTC, unsigned int alarm)
+{
+ pRTTC->RTTC_RTAR = alarm;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_GetAlarmValue()
+//* \brief Get RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetAlarmValue(
+ AT91PS_RTTC pRTTC)
+{
+ return(pRTTC->RTTC_RTAR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTTGetStatus()
+//* \brief Read the RTT status
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetStatus(
+ AT91PS_RTTC pRTTC)
+{
+ return(pRTTC->RTTC_RTSR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn AT91F_RTT_ReadValue()
+//* \brief Read the RTT value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTReadValue(
+ AT91PS_RTTC pRTTC)
+{
+ register volatile unsigned int val1,val2;
+ do
+ {
+ val1 = pRTTC->RTTC_RTVR;
+ val2 = pRTTC->RTTC_RTVR;
+ }
+ while(val1 != val2);
+ return(val1);
+}
+/* *****************************************************************************
+ SOFTWARE API FOR PITC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITInit
+//* \brief System timer init : period in µsecond, system clock freq in MHz
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITInit(
+ AT91PS_PITC pPITC,
+ unsigned int period,
+ unsigned int pit_frequency)
+{
+ pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
+ pPITC->PITC_PIMR |= AT91C_PITC_PITEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITSetPIV
+//* \brief Set the PIT Periodic Interval Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITSetPIV(
+ AT91PS_PITC pPITC,
+ unsigned int piv)
+{
+ pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITEnableInt
+//* \brief Enable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITEnableInt(
+ AT91PS_PITC pPITC)
+{
+ pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITDisableInt
+//* \brief Disable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITDisableInt(
+ AT91PS_PITC pPITC)
+{
+ pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetMode
+//* \brief Read PIT mode register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetMode(
+ AT91PS_PITC pPITC)
+{
+ return(pPITC->PITC_PIMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetStatus
+//* \brief Read PIT status register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetStatus(
+ AT91PS_PITC pPITC)
+{
+ return(pPITC->PITC_PISR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetPIIR
+//* \brief Read PIT CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIIR(
+ AT91PS_PITC pPITC)
+{
+ return(pPITC->PITC_PIIR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITGetPIVR
+//* \brief Read System timer CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIVR(
+ AT91PS_PITC pPITC)
+{
+ return(pPITC->PITC_PIVR);
+}
+/* *****************************************************************************
+ SOFTWARE API FOR WDTC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTSetMode
+//* \brief Set Watchdog Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTSetMode(
+ AT91PS_WDTC pWDTC,
+ unsigned int Mode)
+{
+ pWDTC->WDTC_WDMR = Mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTRestart
+//* \brief Restart Watchdog
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTRestart(
+ AT91PS_WDTC pWDTC)
+{
+ pWDTC->WDTC_WDCR = 0xA5000001;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTSGettatus
+//* \brief Get Watchdog Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTSGettatus(
+ AT91PS_WDTC pWDTC)
+{
+ return(pWDTC->WDTC_WDSR & 0x3);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTGetPeriod
+//* \brief Translate ms into Watchdog Compatible value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
+{
+ if ((ms < 4) || (ms > 16000))
+ return 0;
+ return((ms << 8) / 1000);
+}
+/* *****************************************************************************
+ SOFTWARE API FOR VREG
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_Enable_LowPowerMode
+//* \brief Enable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Enable_LowPowerMode(
+ AT91PS_VREG pVREG)
+{
+ pVREG->VREG_MR |= AT91C_VREG_PSTDBY;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_Disable_LowPowerMode
+//* \brief Disable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Disable_LowPowerMode(
+ AT91PS_VREG pVREG)
+{
+ pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
+}/* *****************************************************************************
+ SOFTWARE API FOR MC
+ ***************************************************************************** */
+
+#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void) //
+{
+ AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+
+ pMC->MC_RCR = AT91C_MC_RCB;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+ AT91PS_MC pMC, // pointer to a MC controller
+ unsigned int mode) // mode register
+{
+ // Write to the FMR register
+ pMC->MC_FMR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+ AT91PS_MC pMC) // pointer to a MC controller
+{
+ return pMC->MC_FMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+ int master_clock) // master clock in Hz
+{
+ return (master_clock/1000000 +2);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+ AT91PS_MC pMC, // pointer to a MC controller
+ unsigned int transfer_cmd)
+{
+ pMC->MC_FCR = transfer_cmd;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+ AT91PS_MC pMC) // pointer to a MC controller
+{
+ return pMC->MC_FSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+ AT91PS_MC pMC, // \arg pointer to a MC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+ AT91PS_MC pMC, // \arg pointer to a MC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_MC_EFC_GetStatus(pMC) & flag);
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR SPI
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+ const unsigned int null) // \arg
+{
+ /* NOT DEFINED AT THIS MOMENT */
+ return ( 0 );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ int cs, // SPI cs number (0 to 3)
+ int val) // chip select register
+{
+ //* Write to the CSR register
+ *(pSPI->SPI_CSR + cs) = val;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ unsigned int flag) // IT to be enabled
+{
+ //* Write to the IER register
+ pSPI->SPI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ unsigned int flag) // IT to be disabled
+{
+ //* Write to the IDR register
+ pSPI->SPI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
+{
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
+{
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+ AT91PS_SPI pSPI // pointer to a SPI controller
+ )
+{
+ //* Write to the CR register
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ int mode) // mode register
+{
+ //* Write to the MR register
+ pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+ AT91PS_SPI pSPI, // pointer to a SPI controller
+ char PCS_Device) // PCS of the Device
+{
+ //* Write to the MR register
+ pSPI->SPI_MR &= 0xFFF0FFFF;
+ pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+ AT91PS_SPI pSPI,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pSPI->SPI_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+ AT91PS_SPI pSPI,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pSPI->SPI_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+ AT91PS_SPI pSPI) // \arg pointer to a SPI controller
+{
+ //* Reset all the Chip Select register
+ pSPI->SPI_CSR[0] = 0 ;
+ pSPI->SPI_CSR[1] = 0 ;
+ pSPI->SPI_CSR[2] = 0 ;
+ pSPI->SPI_CSR[3] = 0 ;
+
+ //* Reset the SPI mode
+ pSPI->SPI_MR = 0 ;
+
+ //* Disable all interrupts
+ pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+ //* Abort the Peripheral Data Transfers
+ AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+ //* Disable receiver and transmitter and stop any activity immediately
+ pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+ AT91PS_SPI pSPI,
+ unsigned int character,
+ unsigned int cs_number )
+{
+ unsigned int value_for_cs;
+ value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number
+ pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+ const AT91PS_SPI pSPI)
+{
+ return((pSPI->SPI_RDR) & 0xFFFF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+ AT91PS_SPI pSpi) // \arg pointer to a SPI controller
+{
+ return pSpi->SPI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+ AT91PS_SPI pSpi, // \arg pointer to a SPI controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR ADC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int flag) // IT to be enabled
+{
+ //* Write to the IER register
+ pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int flag) // IT to be disabled
+{
+ //* Write to the IDR register
+ pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+ AT91PS_ADC pADC) // pointer to a ADC controller
+{
+ return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+ AT91PS_ADC pADC) // pointer to a ADC controller
+{
+ return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+ AT91PS_ADC pADC, // \arg pointer to a ADC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int mode) // mode register
+{
+ //* Write to the MR register
+ pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_MR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int mck_clock, // in MHz
+ unsigned int adc_clock, // in MHz
+ unsigned int startup_time, // in us
+ unsigned int sample_and_hold_time) // in ns
+{
+ unsigned int prescal,startup,shtim;
+
+ prescal = mck_clock/(2*adc_clock) - 1;
+ startup = adc_clock*startup_time/8 - 1;
+ shtim = adc_clock*sample_and_hold_time/1000 - 1;
+
+ //* Write to the MR register
+ pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int channel) // mode register
+{
+ //* Write to the CHER register
+ pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+ AT91PS_ADC pADC, // pointer to a ADC controller
+ unsigned int channel) // mode register
+{
+ //* Write to the CHDR register
+ pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CHSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ pADC->ADC_CR = AT91C_ADC_START;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ pADC->ADC_CR = AT91C_ADC_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_LCDR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR1;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR2;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR3;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR5;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR6;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+ AT91PS_ADC pADC // pointer to a ADC controller
+ )
+{
+ return pADC->ADC_CDR7;
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR SSC
+ ***************************************************************************** */
+//* Define the standard I2S mode configuration
+
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ AT91C_SSC_CKS_DIV +\
+ AT91C_SSC_CKO_CONTINOUS +\
+ AT91C_SSC_CKG_NONE +\
+ AT91C_SSC_START_FALL_RF +\
+ AT91C_SSC_STTOUT +\
+ ((1<<16) & AT91C_SSC_STTDLY) +\
+ ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+
+
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ (nb_bit_by_slot-1) +\
+ AT91C_SSC_MSBF +\
+ (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\
+ (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+ AT91C_SSC_FSOS_NEGATIVE)
+
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int speed) // \arg SSC baudrate
+{
+ unsigned int baud_value;
+ //* Define the baud rate divisor register
+ if (speed == 0)
+ baud_value = 0;
+ else
+ {
+ baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+ if ((baud_value % 10) >= 5)
+ baud_value = (baud_value / 10) + 1;
+ else
+ baud_value /= 10;
+ }
+
+ pSSC->SSC_CMR = baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int syst_clock, // \arg System Clock Frequency
+ unsigned int baud_rate, // \arg Expected Baud Rate Frequency
+ unsigned int clock_rx, // \arg Receiver Clock Parameters
+ unsigned int mode_rx, // \arg mode Register to be programmed
+ unsigned int clock_tx, // \arg Transmitter Clock Parameters
+ unsigned int mode_tx) // \arg mode Register to be programmed
+{
+ //* Disable interrupts
+ pSSC->SSC_IDR = (unsigned int) -1;
+
+ //* Reset receiver and transmitter
+ pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
+
+ //* Define the Clock Mode Register
+ AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
+
+ //* Write the Receive Clock Mode Register
+ pSSC->SSC_RCMR = clock_rx;
+
+ //* Write the Transmit Clock Mode Register
+ pSSC->SSC_TCMR = clock_tx;
+
+ //* Write the Receive Frame Mode Register
+ pSSC->SSC_RFMR = mode_rx;
+
+ //* Write the Transmit Frame Mode Register
+ pSSC->SSC_TFMR = mode_tx;
+
+ //* Clear Transmit and Receive Counters
+ AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
+{
+ //* Enable receiver
+ pSSC->SSC_CR = AT91C_SSC_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
+{
+ //* Disable receiver
+ pSSC->SSC_CR = AT91C_SSC_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
+{
+ //* Enable transmitter
+ pSSC->SSC_CR = AT91C_SSC_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+ AT91PS_SSC pSSC) // \arg pointer to a SSC controller
+{
+ //* Disable transmitter
+ pSSC->SSC_CR = AT91C_SSC_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg IT to be enabled
+{
+ //* Write to the IER register
+ pSSC->SSC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+ AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg IT to be disabled
+{
+ //* Write to the IDR register
+ pSSC->SSC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+ AT91PS_SSC pSSC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pSSC->SSC_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+ AT91PS_SSC pSSC,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pSSC->SSC_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+ AT91PS_SSC pSsc) // \arg pointer to a SSC controller
+{
+ return pSsc->SSC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+ AT91PS_SSC pSsc, // \arg pointer to a SSC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR USART
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
+
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_EXT )
+
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+ AT91C_US_USMODE_NORMAL + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
+
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
+
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+ AT91C_US_CLKS_CLOCK +\
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_EVEN + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CKLO +\
+ AT91C_US_OVER)
+
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \
+ AT91C_US_NBSTOP_1_BIT + \
+ AT91C_US_PAR_NONE + \
+ AT91C_US_CHRL_8_BITS + \
+ AT91C_US_CLKS_CLOCK )
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+ const unsigned int main_clock, // \arg peripheral clock
+ const unsigned int baud_rate) // \arg UART baudrate
+{
+ unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+ if ((baud_value % 10) >= 5)
+ baud_value = (baud_value / 10) + 1;
+ else
+ baud_value /= 10;
+ return baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int speed) // \arg UART baudrate
+{
+ //* Define the baud rate divisor register
+ pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int timeguard) // \arg timeguard value
+{
+ //* Write the Timeguard Register
+ pUSART->US_TTGR = timeguard ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int flag) // \arg IT to be enabled
+{
+ //* Write to the IER register
+ pUSART->US_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int flag) // \arg IT to be disabled
+{
+ //* Write to the IER register
+ pUSART->US_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+ AT91PS_USART pUSART, // \arg pointer to a USART controller
+ unsigned int mainClock, // \arg peripheral clock
+ unsigned int mode , // \arg mode Register to be programmed
+ unsigned int baudRate , // \arg baudrate to be programmed
+ unsigned int timeguard ) // \arg timeguard to be programmed
+{
+ //* Disable interrupts
+ pUSART->US_IDR = (unsigned int) -1;
+
+ //* Reset receiver and transmitter
+ pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
+
+ //* Define the baud rate divisor register
+ AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
+
+ //* Write the Timeguard Register
+ AT91F_US_SetTimeguard(pUSART, timeguard);
+
+ //* Clear Transmit and Receive Counters
+ AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
+
+ //* Define the USART mode
+ pUSART->US_MR = mode ;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
+{
+ //* Enable receiver
+ pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
+{
+ //* Enable transmitter
+ pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
+{
+ //* Reset receiver
+ pUSART->US_CR = AT91C_US_RSTRX;
+ //* Re-Enable receiver
+ pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
+{
+ //* Reset transmitter
+ pUSART->US_CR = AT91C_US_RSTTX;
+ //* Enable transmitter
+ pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
+{
+ //* Disable receiver
+ pUSART->US_CR = AT91C_US_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
+{
+ //* Disable transmitter
+ pUSART->US_CR = AT91C_US_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+ AT91PS_USART pUSART) // \arg pointer to a USART controller
+{
+ //* Reset the baud rate divisor register
+ pUSART->US_BRGR = 0 ;
+
+ //* Reset the USART mode
+ pUSART->US_MR = 0 ;
+
+ //* Reset the Timeguard Register
+ pUSART->US_TTGR = 0;
+
+ //* Disable all interrupts
+ pUSART->US_IDR = 0xFFFFFFFF ;
+
+ //* Abort the Peripheral Data Transfers
+ AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
+
+ //* Disable receiver and transmitter and stop any activity immediately
+ pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
+{
+ return (pUSART->US_CSR & AT91C_US_TXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
+{
+ return (pUSART->US_CSR & AT91C_US_RXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+ AT91PS_USART pUSART ) // \arg pointer to a USART controller
+{
+ return (pUSART->US_CSR &
+ (AT91C_US_OVRE | // Overrun error
+ AT91C_US_FRAME | // Framing error
+ AT91C_US_PARE)); // Parity error
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+ AT91PS_USART pUSART,
+ int character )
+{
+ pUSART->US_THR = (character & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+ const AT91PS_USART pUSART)
+{
+ return((pUSART->US_RHR) & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+ AT91PS_USART pUSART,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_SendFrame(
+ (AT91PS_PDC) &(pUSART->US_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+ AT91PS_USART pUSART,
+ char *pBuffer,
+ unsigned int szBuffer,
+ char *pNextBuffer,
+ unsigned int szNextBuffer )
+{
+ return AT91F_PDC_ReceiveFrame(
+ (AT91PS_PDC) &(pUSART->US_RPR),
+ pBuffer,
+ szBuffer,
+ pNextBuffer,
+ szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+ AT91PS_USART pUSART,
+ unsigned char value
+)
+{
+ pUSART->US_IF = value;
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR TWI
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg IT to be enabled
+{
+ //* Write to the IER register
+ pTWI->TWI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+ AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg IT to be disabled
+{
+ //* Write to the IDR register
+ pTWI->TWI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller
+{
+ //* Disable interrupts
+ pTWI->TWI_IDR = (unsigned int) -1;
+
+ //* Reset peripheral
+ pTWI->TWI_CR = AT91C_TWI_SWRST;
+
+ //* Set Master mode
+ pTWI->TWI_CR = AT91C_TWI_MSEN;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+ AT91PS_TWI pTwi) // \arg pointer to a TWI controller
+{
+ return pTwi->TWI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+ AT91PS_TWI pTwi, // \arg pointer to a TWI controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR TC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg TC interrupt to be enabled
+{
+ pTc->TC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg TC interrupt to be disabled
+{
+ pTc->TC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+ AT91PS_TC pTc) // \arg pointer to a TC controller
+{
+ return pTc->TC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+ AT91PS_TC pTc, // \arg pointer to a TC controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR PWMC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+ AT91PS_PWMC pPWM) // pointer to a PWM controller
+{
+ return pPWM->PWMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg PWM interrupt to be enabled
+{
+ pPwm->PWMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+ AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg PWM interrupt to be disabled
+{
+ pPwm->PWMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+ AT91PS_PWMC pPwm) // \arg pointer to a PWM controller
+{
+ return pPwm->PWMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_PWMC_GetStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int channelId, // \arg PWM channel ID
+ unsigned int mode, // \arg PWM mode
+ unsigned int period, // \arg PWM period
+ unsigned int duty) // \arg PWM duty cycle
+{
+ pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+ pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+ pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg Channels IDs to be enabled
+{
+ pPWM->PWMC_ENA = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int flag) // \arg Channels IDs to be enabled
+{
+ pPWM->PWMC_DIS = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+ AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
+ unsigned int channelId, // \arg PWM channel ID
+ unsigned int update) // \arg Channels IDs to be enabled
+{
+ pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR UDP
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg IT to be enabled
+{
+ //* Write to the IER register
+ pUDP->UDP_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg IT to be disabled
+{
+ //* Write to the IDR register
+ pUDP->UDP_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char address) // \arg new UDP address
+{
+ pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
+{
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
+{
+ pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg new UDP address
+{
+ pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+ pUDP->UDP_GLBSTATE |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+ AT91PS_UDP pUDP) // \arg pointer to a UDP controller
+{
+ return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg Endpoints to be reset
+{
+ pUDP->UDP_RSTEP = flag;
+ pUDP->UDP_RSTEP = 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
+{
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned char value) // \arg value to be written in the DPR
+{
+ pUDP->UDP_FDR[endpoint] = value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
+{
+ return pUDP->UDP_FDR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
+{
+ pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned int flag) // \arg flag to be cleared
+{
+ pUDP->UDP_CSR[endpoint] &= ~(flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint, // \arg endpoint number
+ unsigned int flag) // \arg flag to be cleared
+{
+ pUDP->UDP_CSR[endpoint] |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+ AT91PS_UDP pUDP, // \arg pointer to a UDP controller
+ unsigned char endpoint) // \arg endpoint number
+{
+ return pUDP->UDP_CSR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+ AT91PS_UDP pUdp) // \arg pointer to a UDP controller
+{
+ return pUdp->UDP_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+ AT91PS_UDP pUdp, // \arg pointer to a UDP controller
+ unsigned int flag) // \arg flag to be tested
+{
+ return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA9_DRXD ) |
+ ((unsigned int) AT91C_PA10_DTXD ), // Peripheral A
+ 0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA6_PCK0 ) |
+ ((unsigned int) AT91C_PA18_PCK2 ) |
+ ((unsigned int) AT91C_PA31_PCK2 ) |
+ ((unsigned int) AT91C_PA21_PCK1 ) |
+ ((unsigned int) AT91C_PA17_PCK1 )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_VREG_CfgPMC
+//* \brief Enable Peripheral clock in PMC for VREG
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RSTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for RSTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTC_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SSC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA19_RK ) |
+ ((unsigned int) AT91C_PA16_TK ) |
+ ((unsigned int) AT91C_PA15_TF ) |
+ ((unsigned int) AT91C_PA18_RD ) |
+ ((unsigned int) AT91C_PA20_RF ) |
+ ((unsigned int) AT91C_PA17_TD ), // Peripheral A
+ 0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_WDTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for WDTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTC_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_US1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA29_RI1 ) |
+ ((unsigned int) AT91C_PA26_DCD1 ) |
+ ((unsigned int) AT91C_PA28_DSR1 ) |
+ ((unsigned int) AT91C_PA27_DTR1 ) |
+ ((unsigned int) AT91C_PA23_SCK1 ) |
+ ((unsigned int) AT91C_PA24_RTS1 ) |
+ ((unsigned int) AT91C_PA22_TXD1 ) |
+ ((unsigned int) AT91C_PA21_RXD1 ) |
+ ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A
+ 0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_US0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA5_RXD0 ) |
+ ((unsigned int) AT91C_PA8_CTS0 ) |
+ ((unsigned int) AT91C_PA7_RTS0 ) |
+ ((unsigned int) AT91C_PA6_TXD0 ), // Peripheral A
+ ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for SPI
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SPI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_SPI_CfgPIO
+//* \brief Configure PIO controllers to drive SPI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA13_MOSI ) |
+ ((unsigned int) AT91C_PA31_NPCS1 ) |
+ ((unsigned int) AT91C_PA14_SPCK ) |
+ ((unsigned int) AT91C_PA11_NPCS0 ) |
+ ((unsigned int) AT91C_PA12_MISO ), // Peripheral A
+ ((unsigned int) AT91C_PA9_NPCS1 ) |
+ ((unsigned int) AT91C_PA22_NPCS3 ) |
+ ((unsigned int) AT91C_PA3_NPCS3 ) |
+ ((unsigned int) AT91C_PA5_NPCS3 ) |
+ ((unsigned int) AT91C_PA10_NPCS2 ) |
+ ((unsigned int) AT91C_PA30_NPCS2 )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PITC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PITC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITC_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_FIQ) |
+ ((unsigned int) 1 << AT91C_ID_IRQ0) |
+ ((unsigned int) 1 << AT91C_ID_IRQ1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A
+ ((unsigned int) AT91C_PA20_IRQ0 ) |
+ ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TWI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA4_TWCK ) |
+ ((unsigned int) AT91C_PA3_TWD ), // Peripheral A
+ 0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA7_PWM3 ) |
+ ((unsigned int) AT91C_PA14_PWM3 )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A
+ ((unsigned int) AT91C_PA13_PWM2 ) |
+ ((unsigned int) AT91C_PA25_PWM2 )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A
+ ((unsigned int) AT91C_PA24_PWM1 ) |
+ ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A
+ ((unsigned int) AT91C_PA23_PWM0 ) |
+ ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_ADC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_RTTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for RTTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RTTC_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_UDP));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA0_TIOA0 ) |
+ ((unsigned int) AT91C_PA4_TCLK0 ) |
+ ((unsigned int) AT91C_PA1_TIOB0 )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA15_TIOA1 ) |
+ ((unsigned int) AT91C_PA28_TCLK1 ) |
+ ((unsigned int) AT91C_PA16_TIOB1 )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_TC2));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PA27_TIOB2 ) |
+ ((unsigned int) AT91C_PA26_TIOA2 ) |
+ ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PIOA));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_PWMC));
+}
+
+#endif // lib_AT91SAM7S64_H
diff --git a/AT91SAM7S256/SAM7S256/Include/math.h b/AT91SAM7S256/SAM7S256/Include/math.h
new file mode 100644
index 0000000..b7c647f
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/math.h
@@ -0,0 +1,647 @@
+/* math.h standard header */
+#ifndef _MATH
+#define _MATH
+
+#ifndef _SYSTEM_BUILD
+ #pragma system_include
+#endif
+
+#ifndef _YMATH
+ #include <ymath.h>
+#endif
+_C_STD_BEGIN
+
+ /* MACROS */
+#define HUGE_VAL _CSTD _Hugeval._Double
+#if _DLIB_ADD_C99_SYMBOLS
+ #define HUGE_VALF _CSTD _FHugeval._Float
+ #define HUGE_VALL _CSTD _LHugeval._Long_Double
+
+ #define INFINITY (0.Infinity)
+ #define NAN (0.NaN)
+
+ /* typedefs */
+
+ typedef float float_t;
+ typedef double double_t;
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+
+
+
+_C_LIB_DECL
+ /* double declarations */
+__INTRINSIC double acos(double);
+__INTRINSIC double asin(double);
+__INTRINSIC double atan(double);
+__INTRINSIC double atan2(double, double);
+__INTRINSIC double ceil(double);
+__INTRINSIC double exp(double);
+__INTRINSIC double fabs(double);
+__INTRINSIC double floor(double);
+__INTRINSIC double fmod(double, double);
+__INTRINSIC double frexp(double, int *);
+__INTRINSIC double ldexp(double, int);
+__INTRINSIC double modf(double, double *);
+__INTRINSIC double pow(double, double);
+__INTRINSIC double sqrt(double);
+__INTRINSIC double tan(double);
+__INTRINSIC double tanh(double);
+
+__INTRINSIC double cos(double);
+__INTRINSIC double cosh(double);
+__INTRINSIC double log(double);
+__INTRINSIC double log10(double);
+__INTRINSIC double sin(double);
+__INTRINSIC double sinh(double);
+
+#if _DLIB_ADD_C99_SYMBOLS
+
+ /* float declarations */
+ __INTRINSIC float acosf(float);
+ __INTRINSIC float asinf(float);
+ __INTRINSIC float atanf(float);
+ __INTRINSIC float atan2f(float, float);
+ __INTRINSIC float ceilf(float);
+ __INTRINSIC float expf(float);
+ __INTRINSIC float fabsf(float);
+ __INTRINSIC float floorf(float);
+ __INTRINSIC float fmodf(float, float);
+ __INTRINSIC float frexpf(float, int *);
+ __INTRINSIC float ldexpf(float, int);
+ __INTRINSIC float modff(float, float *);
+ __INTRINSIC float powf(float, float);
+ __INTRINSIC float sqrtf(float);
+ __INTRINSIC float tanf(float);
+ __INTRINSIC float tanhf(float);
+
+ __INTRINSIC float cosf(float);
+ __INTRINSIC float coshf(float);
+ __INTRINSIC float logf(float);
+ __INTRINSIC float log10f(float);
+ __INTRINSIC float sinf(float);
+ __INTRINSIC float sinhf(float);
+
+ /* long double declarations */
+ __INTRINSIC long double acosl(long double);
+ __INTRINSIC long double asinl(long double);
+ __INTRINSIC long double atanl(long double);
+ __INTRINSIC long double atan2l(long double, long double);
+ __INTRINSIC long double ceill(long double);
+ __INTRINSIC long double expl(long double);
+ __INTRINSIC long double fabsl(long double);
+ __INTRINSIC long double floorl(long double);
+ __INTRINSIC long double fmodl(long double, long double);
+ __INTRINSIC long double frexpl(long double, int *);
+ __INTRINSIC long double ldexpl(long double, int);
+ __INTRINSIC long double modfl(long double, long double *);
+ __INTRINSIC long double powl(long double, long double);
+ __INTRINSIC long double sqrtl(long double);
+ __INTRINSIC long double tanl(long double);
+ __INTRINSIC long double tanhl(long double);
+
+ __INTRINSIC long double cosl(long double);
+ __INTRINSIC long double coshl(long double);
+ __INTRINSIC long double logl(long double);
+ __INTRINSIC long double log10l(long double);
+ __INTRINSIC long double sinl(long double);
+ __INTRINSIC long double sinhl(long double);
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+
+_END_C_LIB_DECL
+
+#ifndef _NO_DEFINITIONS_IN_HEADER_FILES
+ /* double INLINES, FOR C and C++ */
+ #pragma inline
+ double cos(double _X)
+ { /* return cosine */
+ return (_Sin(_X, 1));
+ }
+
+ #pragma inline
+ double cosh(double _X)
+ { /* return hyperbolic cosine */
+ return (_Cosh(_X, 1));
+ }
+
+ #pragma inline
+ double log(double _X)
+ { /* return natural logarithm */
+ return (_Log(_X, 0));
+ }
+
+ #pragma inline
+ double log10(double _X)
+ { /* return base-10 logarithm */
+ return (_Log(_X, 1));
+ }
+
+ #pragma inline
+ double sin(double _X)
+ { /* return sine */
+ return (_Sin(_X, 0));
+ }
+
+ #pragma inline
+ double sinh(double _X)
+ { /* return hyperbolic sine */
+ return (_Sinh(_X, 1));
+ }
+
+ #ifdef __cplusplus
+ inline double abs(double _X) /* OVERLOADS */
+ { /* return absolute value */
+ return (fabs(_X));
+ }
+
+ inline double pow(double _X, int _Y)
+ { /* raise to integer power */
+ unsigned int _N = _Y;
+ if (_Y < 0)
+ _N = 0 - _N;
+
+ for (double _Z = 1; ; _X *= _X)
+ {
+ if ((_N & 1) != 0)
+ _Z *= _X;
+ if ((_N >>= 1) == 0)
+ return (_Y < 0 ? (double)(1) / _Z : _Z);
+ }
+ }
+ #endif /* __cplusplus */
+
+
+ /* float INLINES, FOR C and C++ */
+ #if _DLIB_ADD_C99_SYMBOLS
+ #pragma inline
+ float cosf(float _X)
+ { /* return cosine */
+ return (_F_FNAME(Sin)(_X, 1));
+ }
+
+ #pragma inline
+ float coshf(float _X)
+ { /* return hyperbolic cosine */
+ return (_F_FNAME(Cosh)(_X, 1));
+ }
+
+ #pragma inline
+ float logf(float _X)
+ { /* return natural logarithm */
+ return (_F_FNAME(Log)(_X, 0));
+ }
+
+ #pragma inline
+ float log10f(float _X)
+ { /* return base-10 logarithm */
+ return (_F_FNAME(Log)(_X, 1));
+ }
+
+ #pragma inline
+ float sinf(float _X)
+ { /* return sine */
+ return (_F_FNAME(Sin)(_X, 0));
+ }
+
+ #pragma inline
+ float sinhf(float _X)
+ { /* return hyperbolic sine */
+ return (_F_FNAME(Sinh)(_X, 1));
+ }
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+
+ #ifdef __cplusplus
+ inline float abs(float _X) /* OVERLOADS */
+ { /* return absolute value */
+ return (_F_FUN(fabs)(_X));
+ }
+
+ inline float acos(float _X)
+ { /* return arccosine */
+ return (_F_FUN(acos)(_F_CAST _X));
+ }
+
+ inline float asin(float _X)
+ { /* return arcsine */
+ return (_F_FUN(asin)(_F_CAST _X));
+ }
+
+ inline float atan(float _X)
+ { /* return arctangent */
+ return (_F_FUN(atan)(_F_CAST _X));
+ }
+
+ inline float atan2(float _Y, float _X)
+ { /* return arctangent */
+ return (_F_FUN(atan2)(_F_CAST _Y,_F_CAST _X));
+ }
+
+ inline float ceil(float _X)
+ { /* return ceiling */
+ return (_F_FUN(ceil)(_F_CAST _X));
+ }
+
+ inline float cos(float _X)
+ { /* return cosine */
+ return (_F_FNAME(Sin)(_X, 1));
+ }
+
+ inline float cosh(float _X)
+ { /* return hyperbolic cosine */
+ return (_F_FNAME(Cosh)(_X, 1));
+ }
+
+ inline float exp(float _X)
+ { /* return exponential */
+ return (_F_FUN(exp)(_F_CAST _X));
+ }
+
+ inline float fabs(float _X)
+ { /* return absolute value */
+ return (_F_FUN(fabs)(_F_CAST _X));
+ }
+
+ inline float floor(float _X)
+ { /* return floor */
+ return (_F_FUN(floor)(_F_CAST _X));
+ }
+
+ inline float fmod(float _X, float _Y)
+ { /* return modulus */
+ return (_F_FUN(fmod)(_F_CAST _X,_F_CAST _Y));
+ }
+
+ inline float frexp(float _X, int *_Y)
+ { /* unpack exponent */
+ return (_F_FUN(frexp)(_F_CAST _X, _Y));
+ }
+
+ inline float ldexp(float _X, int _Y)
+ { /* pack exponent */
+ return (_F_FUN(ldexp)(_F_CAST _X, _Y));
+ }
+
+ inline float log(float _X)
+ { /* return natural logarithm */
+ return (_F_FNAME(Log)(_X, 0));
+ }
+
+ inline float log10(float _X)
+ { /* return base-10 logarithm */
+ return (_F_FNAME(Log)(_X, 1));
+ }
+
+ inline float modf(float _X, float *_Y)
+ { /* unpack fraction */
+ return (_F_FUN(modf)(_F_CAST _X,_F_PTRCAST _Y));
+ }
+
+ inline float pow(float _X, float _Y)
+ { /* raise to power */
+ return (_F_FUN(pow)(_F_CAST _X,_F_CAST _Y));
+ }
+
+ inline float pow(float _X, int _Y)
+ { /* raise to integer power */
+ #ifdef _FLOAT_IS_DOUBLE
+ return (float) pow((double) _X, _Y);
+ #else
+ unsigned int _N = _Y;
+ if (_Y < 0)
+ _N = 0 - _N;
+
+ for (float _Z = 1; ; _X *= _X)
+ {
+ if ((_N & 1) != 0)
+ _Z *= _X;
+ if ((_N >>= 1) == 0)
+ return (_Y < 0 ? (float)(1) / _Z : _Z);
+ }
+ #endif /* _FLOAT_IS_DOUBLE */
+ }
+
+ inline float sin(float _X)
+ { /* return sine */
+ return (_F_FNAME(Sin)(_X, 0));
+ }
+
+ inline float sinh(float _X)
+ { /* return hyperbolic sine */
+ return (_F_FNAME(Sinh)(_X, 1));
+ }
+
+ inline float sqrt(float _X)
+ { /* return square root */
+ return (_F_FUN(sqrt)(_F_CAST _X));
+ }
+
+ inline float tan(float _X)
+ { /* return tangent */
+ return (_F_FUN(tan)(_F_CAST _X));
+ }
+
+ inline float tanh(float _X)
+ { /* return hyperbolic tangent */
+ return (_F_FUN(tanh)(_F_CAST _X));
+ }
+ #endif /* __cplusplus */
+
+ /* long double INLINES, FOR C and C++ */
+ #if _DLIB_ADD_C99_SYMBOLS
+ #pragma inline
+ long double cosl(long double _X)
+ { /* return cosine */
+ return (_L_FNAME(Sin)(_X, 1));
+ }
+
+ #pragma inline
+ long double coshl(long double _X)
+ { /* return hyperbolic cosine */
+ return (_L_FNAME(Cosh)(_X, 1));
+ }
+
+ #pragma inline
+ long double logl(long double _X)
+ { /* return natural logarithm */
+ return (_L_FNAME(Log)(_X, 0));
+ }
+
+ #pragma inline
+ long double log10l(long double _X)
+ { /* return base-10 logarithm */
+ return (_L_FNAME(Log)(_X, 1));
+ }
+
+ #pragma inline
+ long double sinl(long double _X)
+ { /* return sine */
+ return (_L_FNAME(Sin)(_X, 0));
+ }
+
+ #pragma inline
+ long double sinhl(long double _X)
+ { /* return hyperbolic sine */
+ return (_L_FNAME(Sinh)(_X, 1));
+ }
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+
+ #ifdef __cplusplus
+ inline long double abs(long double _X) /* OVERLOADS */
+ { /* return absolute value */
+ return (_L_FUN(fabs)(_L_CAST _X));
+ }
+
+ inline long double acos(long double _X)
+ { /* return arccosine */
+ return (_L_FUN(acos)(_L_CAST _X));
+ }
+
+ inline long double asin(long double _X)
+ { /* return arcsine */
+ return (_L_FUN(asin)(_L_CAST _X));
+ }
+
+ inline long double atan(long double _X)
+ { /* return arctangent */
+ return (_L_FUN(atan)(_L_CAST _X));
+ }
+
+ inline long double atan2(long double _Y, long double _X)
+ { /* return arctangent */
+ return (_L_FUN(atan2)(_L_CAST _Y, _L_CAST _X));
+ }
+
+ inline long double ceil(long double _X)
+ { /* return ceiling */
+ return (_L_FUN(ceil)(_L_CAST _X));
+ }
+
+ inline long double cos(long double _X)
+ { /* return cosine */
+ return (_L_FNAME(Sin)(_X, 1));
+ }
+
+ inline long double cosh(long double _X)
+ { /* return hyperbolic cosine */
+ return (_L_FNAME(Cosh)(_X, 1));
+ }
+
+ inline long double exp(long double _X)
+ { /* return exponential */
+ return (_L_FUN(exp)(_L_CAST _X));
+ }
+
+ inline long double fabs(long double _X)
+ { /* return absolute value */
+ return (_L_FUN(fabs)(_L_CAST _X));
+ }
+
+ inline long double floor(long double _X)
+ { /* return floor */
+ return (_L_FUN(floor)(_L_CAST _X));
+ }
+
+ inline long double fmod(long double _X, long double _Y)
+ { /* return modulus */
+ return (_L_FUN(fmod)(_L_CAST _X,_L_CAST _Y));
+ }
+
+ inline long double frexp(long double _X, int *_Y)
+ { /* unpack exponent */
+ return (_L_FUN(frexp)(_L_CAST _X, _Y));
+ }
+
+ inline long double ldexp(long double _X, int _Y)
+ { /* pack exponent */
+ return (_L_FUN(ldexp)(_L_CAST _X, _Y));
+ }
+
+ inline long double log(long double _X)
+ { /* return natural logarithm */
+ return (_L_FNAME(Log)(_X, 0));
+ }
+
+ inline long double log10(long double _X)
+ { /* return base-10 logarithm */
+ return (_L_FNAME(Log)(_X, 1));
+ }
+
+ inline long double modf(long double _X, long double *_Y)
+ { /* unpack fraction */
+ return (_L_FUN(modf)(_L_CAST _X, _L_PTRCAST _Y));
+ }
+
+ inline long double pow(long double _X, long double _Y)
+ { /* raise to power */
+ return (_L_FUN(pow)(_L_CAST _X, _L_CAST _Y));
+ }
+
+ inline long double pow(long double _X, int _Y)
+ { /* raise to integer power */
+ #ifdef _LONG_DOUBLE_IS_DOUBLE
+ return (long double) pow((double) _X, _Y);
+ #else
+ unsigned int _N = _Y;
+ if (_Y < 0)
+ _N = 0 - _N;
+
+ for (long double _Z = 1; ; _X *= _X)
+ {
+ if ((_N & 1) != 0)
+ _Z *= _X;
+ if ((_N >>= 1) == 0)
+ return (_Y < 0 ? (long double)(1) / _Z : _Z);
+ }
+ #endif /* _LONG_DOUBLE_IS_DOUBLE */
+ }
+
+ inline long double sin(long double _X)
+ { /* return sine */
+ return (_L_FNAME(Sin)(_X, 0));
+ }
+
+ inline long double sinh(long double _X)
+ { /* return hyperbolic sine */
+ return (_L_FNAME(Sinh)(_X, 1));
+ }
+
+ inline long double sqrt(long double _X)
+ { /* return square root */
+ return (_L_FUN(sqrt)(_L_CAST _X));
+ }
+
+ inline long double tan(long double _X)
+ { /* return tangent */
+ return (_L_FUN(tan)(_L_CAST _X));
+ }
+
+ inline long double tanh(long double _X)
+ { /* return hyperbolic tangent */
+ return (_L_FUN(tanh)(_L_CAST _X));
+ }
+ #endif /* __cplusplus */
+#endif /* _NO_DEFINITIONS_IN_HEADER_FILES */
+_C_STD_END
+
+#if _DLIB_ADD_C99_SYMBOLS
+#if 0
+
+/* C99 floating point functionality */
+
+Fyll i
+ #define FP_ILOGB0
+ #define FP_ILOGBNAN
+
+ #define MATH_ERRNO 1
+ #define MATH_ERREXCEPT 2
+ #define math_errhandling MATH_ERRNO
+
+
+ #define FP_INFINITE _INFCODE
+ #define FP_NAN _NANCODE
+ #define FP_NORMAL _FINITE
+ #define FP_SUBNORMAL _DENORM
+ #define FP_ZERO 0
+
+ #if _LONG_DOUBLE_IS_DOUBLE
+ #error "Must add long double handling to the macros below"
+ #endif
+
+ #define fpclassify(x) \
+ (sizeof(x) == __DOUBLE_SIZE__ ? __fpclassifyd(x) : __fpclassifyf(x))
+
+ #pragma inline
+ int __fpclassifyd(double x)
+ {
+ return Dtest(x);
+ }
+
+ #ifndef _FLOAT_IS_DOUBLE
+ #pragma inline
+ int __fpclassifyf(float x)
+ {
+ return _F_FNAME(Dtest)(x);
+ }
+ #endif /* _FLOAT_IS_DOUBLE */
+
+ #define isfinite(x) __isfinite(fpclassify(x))
+
+ #pragma inline
+ int __isfinite(int x)
+ {
+ return x == FP_ZERO || x == FP_NORMAL || x == FP_SUBNORMAL;
+ }
+
+ #define isinf(x) (fpclassify(x) == FP_INFINITE)
+ #define isnan(x) (fpclassify(x) == FP_NAN)
+ #define isnormal(x) (fpclassify(x) == FP_NORMAL)
+
+ #define signbit(x) \
+ (sizeof(x) == __DOUBLE_SIZE__ ? __signbitd(x) : __signbitf(x))
+
+ #include "xxtd.h"
+ #pragma inline
+ int __signbitd(double x)
+ {
+ unsigned short *ps = (unsigned short *)&px;
+
+ return ((ps[_X0] & _XSIGN) == _XSIGN;
+ }
+ #include "xxtdundef.h"
+
+ #ifndef _FLOAT_IS_DOUBLE
+ #include "xxtf.h"
+ #pragma inline
+ int __signbitf(float x)
+ {
+ unsigned short *ps = (unsigned short *)&px;
+
+ return (ps[_X0] & _XSIGN) == _XSIGN;
+ }
+ #include "xxtfundef.h"
+ #endif /* _FLOAT_IS_DOUBLE */
+#endif /* 0 */
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+
+
+
+#if defined(_STD_USING) && defined(__cplusplus)
+ using _CSTD abs;
+
+ using _CSTD acos; using _CSTD asin;
+ using _CSTD atan; using _CSTD atan2; using _CSTD ceil;
+ using _CSTD cos; using _CSTD cosh; using _CSTD exp;
+ using _CSTD fabs; using _CSTD floor; using _CSTD fmod;
+ using _CSTD frexp; using _CSTD ldexp; using _CSTD log;
+ using _CSTD log10; using _CSTD modf; using _CSTD pow;
+ using _CSTD sin; using _CSTD sinh; using _CSTD sqrt;
+ using _CSTD tan; using _CSTD tanh;
+
+ #if _DLIB_ADD_C99_SYMBOLS
+ using _CSTD acosf; using _CSTD asinf;
+ using _CSTD atanf; using _CSTD atan2f; using _CSTD ceilf;
+ using _CSTD cosf; using _CSTD coshf; using _CSTD expf;
+ using _CSTD fabsf; using _CSTD floorf; using _CSTD fmodf;
+ using _CSTD frexpf; using _CSTD ldexpf; using _CSTD logf;
+ using _CSTD log10f; using _CSTD modff; using _CSTD powf;
+ using _CSTD sinf; using _CSTD sinhf; using _CSTD sqrtf;
+ using _CSTD tanf; using _CSTD tanhf;
+
+ using _CSTD acosl; using _CSTD asinl;
+ using _CSTD atanl; using _CSTD atan2l; using _CSTD ceill;
+ using _CSTD cosl; using _CSTD coshl; using _CSTD expl;
+ using _CSTD fabsl; using _CSTD floorl; using _CSTD fmodl;
+ using _CSTD frexpl; using _CSTD ldexpl; using _CSTD logl;
+ using _CSTD log10l; using _CSTD modfl; using _CSTD powl;
+ using _CSTD sinl; using _CSTD sinhl; using _CSTD sqrtl;
+ using _CSTD tanl; using _CSTD tanhl;
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+
+#endif /* defined(_STD_USING) && defined(__cplusplus) */
+
+
+#endif /* _MATH */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Include/sam7s256.c b/AT91SAM7S256/SAM7S256/Include/sam7s256.c
index f3776f6..cc22ca3 100644
--- a/AT91SAM7S256/SAM7S256/Include/sam7s256.c
+++ b/AT91SAM7S256/SAM7S256/Include/sam7s256.c
@@ -1,13 +1,13 @@
//
// Date init 14.12.2004
//
-// Revision date $Date:: 16-05-06 10:08 $
+// Revision date $Date:: 10-12-07 14:29 $
//
// Filename $Workfile:: sam7s256.c $
//
-// Version $Revision:: 2 $
+// Version $Revision:: 3 $
//
-// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Sam7s256/Include/ $
+// Archive $Archive:: /LMS2006/Sys01/Main_V02/Firmware/Sam7s256/Incl $
//
// Platform C
//
diff --git a/AT91SAM7S256/SAM7S256/Include/sam7s256.h b/AT91SAM7S256/SAM7S256/Include/sam7s256.h
index 5a2d07d..332e39d 100644
--- a/AT91SAM7S256/SAM7S256/Include/sam7s256.h
+++ b/AT91SAM7S256/SAM7S256/Include/sam7s256.h
@@ -1,13 +1,13 @@
//
// Date init 14.12.2004
//
-// Revision date $Date:: 16-05-06 10:08 $
+// Revision date $Date:: 24-04-08 14:33 $
//
// Filename $Workfile:: sam7s256.h $
//
-// Version $Revision:: 7 $
+// Version $Revision:: 5 $
//
-// Archive $Archive:: /LMS2006/Sys01/Main/Firmware/Sam7s256/Include/ $
+// Archive $Archive:: /LMS2006/Sys01/Main_V02/Firmware/Sam7s256/Incl $
//
// Platform C
//
@@ -27,6 +27,7 @@
TmpReset = *AT91C_PITC_PIVR;\
TmpReset = TmpReset;/* Suppress warning*/\
*AT91C_PMC_PCER = (1L<<AT91C_ID_PIOA);\
+ ADSetup; /* ADC used in several modules */\
}
@@ -37,6 +38,20 @@
#define OSWatchdogWrite
+#define ADCCLOCK (5000000L) /* 5MHz */
+#define ADCPRESCALER (((OSC + ((ADCCLOCK*2)-1))/(ADCCLOCK*2)) - 1)
+
+#define ADCSTARTUPTIME 20 /* uS */
+#define ADCSTARTUP ((((20 * (ADCCLOCK/1000)) + 7999)/8000L) - 1)
+
+#define SAMPLEHOLDTIME 600 /* nS */
+#define SHTIM ((((SAMPLEHOLDTIME * (ADCCLOCK/1000)) + 999999)/1000000L)-1)
+
+#define ADSetup *AT91C_ADC_MR = (((ULONG)ADCPRESCALER << 8) | \
+ ((ULONG)ADCSTARTUP << 16) | \
+ ((ULONG)SHTIM << 24))
+#define ADStart *AT91C_ADC_CR = AT91C_ADC_START
+
void mSchedReset (void);
void mSchedInit (void);
UBYTE mSchedCtrl (void);
diff --git a/AT91SAM7S256/SAM7S256/Include/stdbool.h b/AT91SAM7S256/SAM7S256/Include/stdbool.h
new file mode 100644
index 0000000..3eabc38
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/stdbool.h
@@ -0,0 +1,28 @@
+/* stdbool.h header */
+/* Copyright (C) 2003 IAR Systems. All rights reserved. */
+
+/* NOTE: IAR Extensions must be enabled in order to use the bool type! */
+
+#ifndef _STDBOOL
+#define _STDBOOL
+
+#ifndef _SYSTEM_BUILD
+#pragma system_include
+#endif
+
+
+#ifndef __C99_BOOL__
+ #error "<stdbool.h> compiled with wrong (version of IAR) compiler"
+#endif
+
+#ifndef __cplusplus
+
+#define bool _Bool
+#define true 1
+#define false 0
+
+#endif /* !__cplusplus */
+
+#define __bool_true_false_are_defined 1
+
+#endif /* !_STDBOOL */
diff --git a/AT91SAM7S256/SAM7S256/Include/stdio.h b/AT91SAM7S256/SAM7S256/Include/stdio.h
new file mode 100644
index 0000000..19f928d
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/stdio.h
@@ -0,0 +1,240 @@
+/* stdio.h standard header */
+#ifndef _STDIO
+#define _STDIO
+
+#ifndef _SYSTEM_BUILD
+ #pragma system_include
+#endif
+
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+#include <ysizet.h>
+_C_STD_BEGIN
+
+ /* Module consistency. */
+#pragma rtmodel="__dlib_file_descriptor",_STRINGIFY(_DLIB_FILE_DESCRIPTOR)
+
+ /* macros */
+#ifndef NULL
+ #define NULL _NULL
+#endif /* NULL */
+
+#define _IOFBF 0
+#define _IOLBF 1
+#define _IONBF 2
+
+#define BUFSIZ 512
+#define EOF (-1)
+#define FILENAME_MAX _FNAMAX
+#define FOPEN_MAX _FOPMAX
+#define L_tmpnam _TNAMAX
+#define TMP_MAX 32
+
+#define SEEK_SET 0
+#define SEEK_CUR 1
+#define SEEK_END 2
+
+#if _DLIB_FILE_DESCRIPTOR
+#define stdin (&_CSTD _Stdin)
+#define stdout (&_CSTD _Stdout)
+#define stderr (&_CSTD _Stderr)
+#endif /* _DLIB_FILE_DESCRIPTOR */
+
+#if _MULTI_THREAD
+ #define _Lockfile(str) _Lockfilelock(str)
+ #define _Unlockfile(str) _Unlockfilelock(str)
+
+#else /* _MULTI_THREAD */
+ #define _Lockfile(x) (void)0
+ #define _Unlockfile(x) (void)0
+#endif /* _MULTI_THREAD */
+
+ /* type definitions */
+typedef _Fpost fpos_t;
+
+ /* printf and scanf pragma support */
+#pragma language=save
+#pragma language=extended
+
+#ifdef _HAS_PRAGMA_PRINTF_ARGS
+ #define __PRINTFPR _Pragma("__printf_args")
+ #define __SCANFPR _Pragma("__scanf_args")
+#else
+ #define __PRINTFPR
+ #define __SCANFPR
+#endif
+
+
+#if _DLIB_FILE_DESCRIPTOR
+ #ifndef _FD_TYPE
+ #define _FD_TYPE signed char
+ #endif /* _FD_TYPE */
+
+ typedef struct _Filet
+ { /* file control information */
+ unsigned short _Mode;
+ unsigned char _Lockno;
+ _FD_TYPE _Handle;
+
+ unsigned char *_Buf, *_Bend, *_Next;
+ unsigned char *_Rend, *_Wend, *_Rback;
+
+ _Wchart *_WRback, _WBack[2];
+ unsigned char *_Rsave, *_WRend, *_WWend;
+
+ struct _Mbstatet _Wstate;
+ char *_Tmpnam;
+ unsigned char _Back[_MBMAX], _Cbuf;
+ } FILE;
+
+ /* declarations */
+ _C_LIB_DECL
+ extern FILE _Stdin, _Stdout, _Stderr;
+
+ __INTRINSIC void clearerr(FILE *);
+ __INTRINSIC int fclose(FILE *);
+ __INTRINSIC int feof(FILE *);
+ __INTRINSIC int ferror(FILE *);
+ __INTRINSIC int fflush(FILE *);
+ __INTRINSIC int fgetc(FILE *);
+ __INTRINSIC int fgetpos(FILE *, fpos_t *);
+ __INTRINSIC char * fgets(char *, int, FILE *);
+ __INTRINSIC FILE * fopen(const char *, const char *);
+ __PRINTFPR __INTRINSIC int fprintf(FILE *, const char *, ...);
+ __INTRINSIC int fputc(int, FILE *);
+ __INTRINSIC int fputs(const char *, FILE *);
+ __INTRINSIC size_t fread(void *, size_t, size_t, FILE *);
+ __INTRINSIC FILE * freopen(const char *, const char *, FILE *);
+ __SCANFPR __INTRINSIC int fscanf(FILE *, const char *, ...);
+ __INTRINSIC int fseek(FILE *, long, int);
+ __INTRINSIC int fsetpos(FILE *, const fpos_t *);
+ __INTRINSIC long ftell(FILE *);
+ __INTRINSIC size_t fwrite(const void *, size_t, size_t, FILE *);
+ __INTRINSIC void rewind(FILE *);
+ __INTRINSIC void setbuf(FILE *, char *);
+ __INTRINSIC int setvbuf(FILE *, char *, int, size_t);
+ __INTRINSIC FILE * tmpfile(void);
+ __INTRINSIC int ungetc(int, FILE *);
+ __PRINTFPR __INTRINSIC int vfprintf(FILE *, const char *, __Va_list);
+ #if _DLIB_ADD_C99_SYMBOLS
+ __SCANFPR __INTRINSIC int vfscanf(FILE *, const char *, __Va_list);
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+
+ #if _DLIB_ADD_EXTRA_SYMBOLS
+ __INTRINSIC FILE * fdopen(_FD_TYPE, const char *);
+ __INTRINSIC _FD_TYPE fileno(FILE *);
+ #endif /* _DLIB_ADD_EXTRA_SYMBOLS */
+
+
+ __INTRINSIC int _Nnl(FILE *, unsigned char *, unsigned char *);
+ __INTRINSIC long _Fgpos(FILE *, fpos_t *);
+ __INTRINSIC int _Flocale(FILE *, const char *, int);
+ __INTRINSIC void _Fsetlocale(FILE *, int);
+ __INTRINSIC int _Fspos(FILE *, const fpos_t *, long, int);
+
+ #if _MULTI_THREAD
+ __INTRINSIC void _Lockfilelock(_Filet *);
+ __INTRINSIC void _Unlockfilelock(_Filet *);
+ #endif /* _MULTI_THREAD */
+
+ extern FILE *_Files[FOPEN_MAX];
+
+ __INTRINSIC int getc(FILE *);
+ __INTRINSIC int putc(int, FILE *);
+ _END_C_LIB_DECL
+#endif /* _DLIB_FILE_DESCRIPTOR */
+
+_C_LIB_DECL
+/* Corresponds to fgets(char *, int, stdin); */
+__INTRINSIC char * __gets(char *, int);
+__INTRINSIC char * gets(char *);
+__INTRINSIC void perror(const char *);
+__PRINTFPR __INTRINSIC int printf(const char *, ...);
+__INTRINSIC int puts(const char *);
+__INTRINSIC int remove(const char *);
+__INTRINSIC int rename(const char *, const char *);
+__SCANFPR __INTRINSIC int scanf(const char *, ...);
+__PRINTFPR __INTRINSIC int sprintf(char *, const char *, ...);
+__SCANFPR __INTRINSIC int sscanf(const char *, const char *, ...);
+__INTRINSIC char * tmpnam(char *);
+/* Corresponds to "ungetc(c, stdout)" */
+__INTRINSIC int __ungetchar(int);
+__PRINTFPR __INTRINSIC int vprintf(const char *, __Va_list);
+#if _DLIB_ADD_C99_SYMBOLS
+ __SCANFPR __INTRINSIC int vscanf(const char *, __Va_list);
+ __SCANFPR __INTRINSIC int vsscanf(const char *, const char *, __Va_list);
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+__PRINTFPR __INTRINSIC int vsprintf(char *, const char *, __Va_list);
+/* Corresponds to fwrite(p, x, y, stdout); */
+__INTRINSIC size_t __write_array(const void *, size_t, size_t);
+#if _DLIB_ADD_C99_SYMBOLS
+ __PRINTFPR __INTRINSIC int snprintf(char *, size_t, const char *, ...);
+ __PRINTFPR __INTRINSIC int vsnprintf(char *, size_t, const char *, __Va_list);
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+
+__INTRINSIC int getchar(void);
+__INTRINSIC int putchar(int);
+
+_END_C_LIB_DECL
+
+#pragma language=restore
+
+#if !(_MULTI_THREAD && _FILE_OP_LOCKS)
+ #ifndef _NO_DEFINITIONS_IN_HEADER_FILES
+ #if _DLIB_FILE_DESCRIPTOR
+ /* inlines, for C and C++ */
+ #pragma inline
+ int (getc)(FILE *_Str)
+ {
+ return fgetc(_Str);
+ }
+
+ #pragma inline
+ int (putc)(int _C, FILE *_Str)
+ {
+ return fputc(_C, _Str);
+ }
+ #endif
+
+ #endif /* _NO_DEFINITIONS_IN_HEADER_FILES */
+#endif /* !(_MULTI_THREAD && _FILE_OP_LOCKS) */
+_C_STD_END
+#endif /* _STDIO */
+
+#if defined(_STD_USING) && defined(__cplusplus)
+ using _CSTD fpos_t;
+ using _CSTD clearerr; using _CSTD fclose; using _CSTD feof;
+ using _CSTD ferror; using _CSTD fflush; using _CSTD fgetc;
+ using _CSTD fgetpos; using _CSTD fgets; using _CSTD fopen;
+ using _CSTD fprintf; using _CSTD fputc; using _CSTD fputs;
+ using _CSTD fread; using _CSTD freopen; using _CSTD fscanf;
+ using _CSTD fseek; using _CSTD fsetpos; using _CSTD ftell;
+ using _CSTD fwrite; using _CSTD getc; using _CSTD getchar;
+ using _CSTD gets; using _CSTD perror;
+ using _CSTD putc; using _CSTD putchar;
+ using _CSTD printf; using _CSTD puts; using _CSTD remove;
+ using _CSTD rename; using _CSTD rewind; using _CSTD scanf;
+ using _CSTD setbuf; using _CSTD setvbuf; using _CSTD sprintf;
+ using _CSTD sscanf; using _CSTD tmpfile; using _CSTD tmpnam;
+ using _CSTD ungetc; using _CSTD vfprintf; using _CSTD vprintf;
+ using _CSTD vsprintf;
+ #if _DLIB_ADD_EXTRA_SYMBOLS
+ using _CSTD fdopen; using _CSTD fileno;
+ #endif /* _DLIB_ADD_EXTRA_SYMBOLS */
+ #if _DLIB_ADD_C99_SYMBOLS
+ using _CSTD snprintf; using _CSTD vsnprintf;
+ using _CSTD vscanf; using _CSTD vsscanf;
+ using _CSTD vfscanf;
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+
+
+ #if _DLIB_FILE_DESCRIPTOR
+ using _CSTD FILE;
+ #endif
+#endif /* defined(_STD_USING) && defined(__cplusplus) */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Include/stdlib.h b/AT91SAM7S256/SAM7S256/Include/stdlib.h
new file mode 100644
index 0000000..eda811d
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/stdlib.h
@@ -0,0 +1,337 @@
+/* stdlib.h standard header */
+#ifndef _STDLIB
+#define _STDLIB
+
+#ifndef _SYSTEM_BUILD
+ #pragma system_include
+#endif
+
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+#include <ysizet.h>
+#include <xencoding_limits.h>
+_C_STD_BEGIN
+
+ /* MACROS */
+#ifndef NULL
+ #define NULL _NULL
+#endif /* NULL */
+
+#define EXIT_FAILURE _EXFAIL
+#define EXIT_SUCCESS 0
+
+#define MB_CUR_MAX _ENCODING_CUR_MAX
+
+#if _ILONG
+ #define RAND_MAX 0x3fffffff
+#else /* _ILONG */
+ #define RAND_MAX 0x7fff
+#endif /* _ILONG */
+
+ /* TYPE DEFINITIONS */
+#ifndef _WCHART
+ #define _WCHART
+ typedef _Wchart wchar_t;
+#endif /* _WCHART */
+
+typedef struct
+{ /* result of int divide */
+ int quot;
+ int rem;
+} div_t;
+
+typedef struct
+{ /* result of long divide */
+ long quot;
+ long rem;
+} ldiv_t;
+
+#if _DLIB_ADD_C99_SYMBOLS
+ #ifdef _LONGLONG
+ typedef struct
+ { /* result of long long divide */
+ _Longlong quot;
+ _Longlong rem;
+ } lldiv_t;
+#endif
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+
+ /* DECLARATIONS */
+_EXTERN_C /* low-level functions */
+__INTRINSIC int atexit(void (*)(void));
+#if _DLIB_ADD_C99_SYMBOLS
+ #pragma object_attribute = __noreturn
+ __INTRINSIC void _Exit(int) _NO_RETURN; /* added with C99 */
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+#pragma object_attribute = __noreturn
+__INTRINSIC void exit(int) _NO_RETURN;
+__INTRINSIC char * getenv(const char *);
+__INTRINSIC int system(const char *);
+_END_EXTERN_C
+
+_C_LIB_DECL
+#pragma object_attribute = __noreturn
+__INTRINSIC void abort(void) _NO_RETURN;
+__INTRINSIC int abs(int);
+__INTRINSIC void * calloc(size_t, size_t);
+__INTRINSIC div_t div(int, int);
+__INTRINSIC void free(void *);
+__INTRINSIC long labs(long);
+__INTRINSIC ldiv_t ldiv(long, long);
+#if _DLIB_ADD_C99_SYMBOLS
+ #ifdef _LONGLONG
+ __INTRINSIC long long llabs(long long);
+ __INTRINSIC lldiv_t lldiv(long long, long long);
+ #endif
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+__INTRINSIC void * malloc(size_t);
+__INTRINSIC int mblen(const char *, size_t);
+__INTRINSIC size_t mbstowcs(wchar_t *, const char *, size_t);
+__INTRINSIC int mbtowc(wchar_t *, const char *, size_t);
+__INTRINSIC int rand(void);
+__INTRINSIC void srand(unsigned int);
+__INTRINSIC void * realloc(void *, size_t);
+__INTRINSIC long strtol(const char *, char **, int);
+__INTRINSIC unsigned long strtoul(const char *, char **, int);
+__INTRINSIC size_t wcstombs(char *, const wchar_t *, size_t);
+__INTRINSIC int wctomb(char *, wchar_t);
+#if _DLIB_ADD_C99_SYMBOLS
+ #ifdef _LONGLONG
+ __INTRINSIC long long strtoll(const char *, char **, int);
+ __INTRINSIC unsigned long long strtoull(const char *, char **, int);
+ #endif
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+
+#pragma language=save
+#pragma language=extended
+
+#define __HEAP_MEM_HELPER1__(M, I) \
+__INTRINSIC void M##_free(void M *); \
+__INTRINSIC void M * M##_malloc(M##_size_t); \
+__INTRINSIC void M * M##_calloc(M##_size_t, M##_size_t); \
+__INTRINSIC void M * M##_realloc(void M *, M##_size_t);
+__HEAP_MEMORY_LIST1__()
+#undef __HEAP_MEM_HELPER1__
+
+#pragma inline
+void free(void * _P)
+{
+ _GLUE(__DEF_PTR_MEM__,_free(_P));
+}
+#pragma inline
+void * malloc(size_t _S)
+{
+ return _GLUE(__DEF_PTR_MEM__,_malloc(_S));
+
+}
+#pragma inline
+void * realloc(void * _P, size_t _S)
+{
+ return _GLUE(__DEF_PTR_MEM__,_realloc(_P, _S));
+}
+#pragma inline
+void * calloc(size_t _N, size_t _S)
+{
+ return _GLUE(__DEF_PTR_MEM__,_calloc(_N, _S));
+}
+
+#pragma language=restore
+
+
+__INTRINSIC unsigned long _Stoul(const char *, char **, int);
+__INTRINSIC float _Stof(const char *, char **, long);
+__INTRINSIC double _Stod(const char *, char **, long);
+__INTRINSIC long double _Stold(const char *, char **, long);
+#ifdef _LONGLONG
+ __INTRINSIC _Longlong _Stoll(const char *, char **, int);
+ __INTRINSIC _ULonglong _Stoull(const char *, char **, int);
+#endif
+
+typedef int _Cmpfun(const void *, const void *);
+__INTRINSIC void * bsearch(const void *, const void *, size_t, size_t,
+ _Cmpfun *);
+__INTRINSIC void qsort(void *, size_t, size_t, _Cmpfun *);
+__INTRINSIC void __qsortbbl(void *, size_t, size_t, _Cmpfun *);
+__INTRINSIC double atof(const char *);
+__INTRINSIC int atoi(const char *);
+__INTRINSIC long atol(const char *);
+#if _DLIB_ADD_C99_SYMBOLS
+ #ifdef _LONGLONG
+ __INTRINSIC long long atoll(const char *);
+ #endif
+ __INTRINSIC float strtof(const char *, char **);
+ __INTRINSIC long double strtold(const char *, char **);
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+__INTRINSIC double strtod(const char *, char **);
+__INTRINSIC size_t _Mbcurmax(void);
+
+_END_C_LIB_DECL
+
+#ifndef _NO_DEFINITIONS_IN_HEADER_FILES
+ _EXTERN_C
+ typedef void _Atexfun(void);
+ _END_EXTERN_C
+ #if _HAS_STRICT_LINKAGE && defined(__cplusplus)
+
+ typedef int _Cmpfun2(const void *, const void *);
+
+ #pragma inline
+ int atexit(void (*_Pfn)(void))
+ { // register a function to call at exit
+ return (atexit((_Atexfun *)_Pfn));
+ }
+
+ #pragma inline
+ void * bsearch(const void *_Key, const void *_Base,
+ size_t _Nelem, size_t _Size, _Cmpfun2 *_Cmp)
+ { // search by binary chop
+ return (bsearch(_Key, _Base, _Nelem, _Size, (_Cmpfun *)_Cmp));
+ }
+
+ #pragma inline
+ void qsort(void *_Base, size_t _Nelem, size_t _Size, _Cmpfun2 *_Cmp)
+ { // sort
+ qsort(_Base, _Nelem, _Size, (_Cmpfun *)_Cmp);
+ }
+ #endif /* _HAS_STRICT_LINKAGE */
+
+ /* INLINES, FOR C and C++ */
+ #pragma inline
+ double atof(const char *_S)
+ { /* convert string to double */
+ return (_Stod(_S, 0, 0));
+ }
+
+ #pragma inline
+ int atoi(const char *_S)
+ { /* convert string to int */
+ return ((int)_Stoul(_S, 0, 10));
+ }
+
+ #pragma inline
+ long atol(const char *_S)
+ { /* convert string to long */
+ return ((long)_Stoul(_S, 0, 10));
+ }
+
+ #if _DLIB_ADD_C99_SYMBOLS
+ #ifdef _LONGLONG
+ #pragma inline
+ long long atoll(const char *_S)
+ { /* convert string to long long */
+ return ((long long)_Stoull(_S, 0, 10));
+ }
+ #endif
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+
+ #pragma inline
+ double strtod(const char *_S, char **_Endptr)
+ { /* convert string to double, with checking */
+ return (_Stod(_S, _Endptr, 0));
+ }
+
+ #if _DLIB_ADD_C99_SYMBOLS
+ #pragma inline
+ float strtof(const char *_S, char **_Endptr)
+ { /* convert string to float, with checking */
+ return (_Stof(_S, _Endptr, 0));
+ }
+
+ #pragma inline
+ long double strtold(const char *_S, char **_Endptr)
+ { /* convert string to long double, with checking */
+ return (_Stold(_S, _Endptr, 0));
+ }
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+
+ #pragma inline
+ unsigned long strtoul(const char *_S, char **_Endptr, int _Base)
+ { /* convert string to unsigned long, with checking */
+ return (_Stoul(_S, _Endptr, _Base));
+ }
+
+ #if _DLIB_ADD_C99_SYMBOLS
+ #ifdef _LONGLONG
+ #pragma inline
+ long long strtoll(const char *_S, char **_Endptr, int _Base)
+ { /* convert string to long long, with checking */
+ return (_Stoll(_S, _Endptr, _Base));
+ }
+
+ #pragma inline
+ unsigned long long strtoull(const char *_S, char **_Endptr, int _Base)
+ { /* convert string to unsigned long long, with checking */
+ return (_Stoull(_S, _Endptr, _Base));
+ }
+ #endif /* _LONGLONG */
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+
+ #pragma inline
+ int abs(int i)
+ { /* compute absolute value of int argument */
+ return (i < 0 ? -i : i);
+ }
+
+ #pragma inline
+ long labs(long i)
+ { /* compute absolute value of long argument */
+ return (i < 0 ? -i : i);
+ }
+
+ #if _DLIB_ADD_C99_SYMBOLS
+ #ifdef _LONGLONG
+ #pragma inline
+ long long llabs(long long i)
+ { /* compute absolute value of long long argument */
+ return (i < 0 ? -i : i);
+ }
+ #endif
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+
+ #ifdef __cplusplus
+ #pragma inline
+ long abs(long _X) /* OVERLOADS */
+ { /* compute abs */
+ return (labs(_X));
+ }
+
+ #pragma inline
+ ldiv_t div(long _X, long _Y)
+ { /* compute quotient and remainder */
+ return (ldiv(_X, _Y));
+ }
+ #endif /* __cplusplus */
+#endif /* _NO_DEFINITIONS_IN_HEADER_FILES */
+
+_C_STD_END
+#endif /* _STDLIB */
+
+#if defined(_STD_USING) && defined(__cplusplus)
+ using _CSTD div_t; using _CSTD ldiv_t;
+
+ using _CSTD abort; using _CSTD abs; using _CSTD atexit;
+ using _CSTD atof; using _CSTD atoi; using _CSTD atol;
+ using _CSTD bsearch; using _CSTD calloc; using _CSTD div;
+ using _CSTD exit; using _CSTD free; using _CSTD getenv;
+ using _CSTD labs; using _CSTD ldiv; using _CSTD malloc;
+ using _CSTD mblen; using _CSTD mbstowcs; using _CSTD mbtowc;
+ using _CSTD qsort; using _CSTD rand; using _CSTD realloc;
+ using _CSTD srand; using _CSTD strtod;
+ using _CSTD strtol; using _CSTD strtoul; using _CSTD system;
+ using _CSTD wcstombs; using _CSTD wctomb;
+ #if _DLIB_ADD_C99_SYMBOLS
+ using _CSTD strtold; using _CSTD strtof;
+ #ifdef _LONGLONG
+ using _CSTD lldiv_t;
+
+ using _CSTD atoll; using _CSTD strtoll; using _CSTD strtoull;
+ using _CSTD llabs; using _CSTD lldiv;
+ #endif
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+#endif /* defined(_STD_USING) && defined(__cplusplus) */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Include/string.h b/AT91SAM7S256/SAM7S256/Include/string.h
new file mode 100644
index 0000000..1fb9d2d
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/string.h
@@ -0,0 +1,409 @@
+/* string.h standard header */
+#ifndef _STRING
+#define _STRING
+
+#ifndef _SYSTEM_BUILD
+#pragma system_include
+#endif
+
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+#include <ysizet.h>
+_C_STD_BEGIN
+
+ /* macros */
+#ifndef NULL
+ #define NULL _NULL
+#endif /* NULL */
+
+ /* declarations */
+_C_LIB_DECL
+__INTRINSIC int memcmp(const void *, const void *, size_t);
+__INTRINSIC void * memcpy(void *, const void *, size_t);
+__INTRINSIC void * memmove(void *, const void *, size_t);
+__INTRINSIC void * memset(void *, int, size_t);
+__INTRINSIC char * strcat(char *, const char *);
+__INTRINSIC int strcmp(const char *, const char *);
+__INTRINSIC int strcoll(const char *, const char *);
+__INTRINSIC char * strcpy(char *, const char *);
+__INTRINSIC size_t strcspn(const char *, const char *);
+__INTRINSIC char * strerror(int);
+__INTRINSIC size_t strlen(const char *);
+__INTRINSIC char * strncat(char *, const char *, size_t);
+__INTRINSIC int strncmp(const char *, const char *, size_t);
+__INTRINSIC char * strncpy(char *, const char *, size_t);
+__INTRINSIC size_t strspn(const char *, const char *);
+__INTRINSIC char * strtok(char *, const char *);
+__INTRINSIC size_t strxfrm(char *, const char *, size_t);
+_END_C_LIB_DECL
+
+ /* The implementations. */
+_C_LIB_DECL
+__INTRINSIC void *_Memchr(const void *, int, size_t);
+__INTRINSIC char *_Strchr(const char *, int);
+__INTRINSIC char *_Strerror(int, char *);
+__INTRINSIC char *_Strpbrk(const char *, const char *);
+__INTRINSIC char *_Strrchr(const char *, int);
+__INTRINSIC char *_Strstr(const char *, const char *);
+_END_C_LIB_DECL
+
+/* IAR, we can't use the stratagem that Dinkum uses for memchr,... */
+#ifdef __cplusplus
+ __INTRINSIC const void *memchr(const void *_S, int _C, size_t _N);
+ __INTRINSIC const char *strchr(const char *_S, int _C);
+ __INTRINSIC const char *strpbrk(const char *_S, const char *_P);
+ __INTRINSIC const char *strrchr(const char *_S, int _C);
+ __INTRINSIC const char *strstr(const char *_S, const char *_P);
+ __INTRINSIC void *memchr(void *_S, int _C, size_t _N);
+ __INTRINSIC char *strchr(char *_S, int _C);
+ __INTRINSIC char *strpbrk(char *_S, const char *_P);
+ __INTRINSIC char *strrchr(char *_S, int _C);
+ __INTRINSIC char *strstr(char *_S, const char *_P);
+#else /* !__cplusplus */
+ __INTRINSIC void *memchr(const void *_S, int _C, size_t _N);
+ __INTRINSIC char *strchr(const char *_S, int _C);
+ __INTRINSIC char *strpbrk(const char *_S, const char *_P);
+ __INTRINSIC char *strrchr(const char *_S, int _C);
+ __INTRINSIC char *strstr(const char *_S, const char *_P);
+#endif /* __cplusplus */
+
+#ifndef _NO_DEFINITIONS_IN_HEADER_FILES
+ /* inlines and overloads, for C and C++ */
+ _STD_BEGIN
+ #ifdef __cplusplus
+ /* First the const overloads for C++. */
+ #pragma inline
+ const void *memchr(const void *_S, int _C, size_t _N)
+ {
+ return (_Memchr(_S, _C, _N));
+ }
+
+ #pragma inline
+ const char *strchr(const char *_S, int _C)
+ {
+ return (_Strchr(_S, _C));
+ }
+
+ #pragma inline
+ const char *strpbrk(const char *_S, const char *_P)
+ {
+ return (_Strpbrk(_S, _P));
+ }
+
+ #pragma inline
+ const char *strrchr(const char *_S, int _C)
+ {
+ return (_Strrchr(_S, _C));
+ }
+
+ #pragma inline
+ const char *strstr(const char *_S, const char *_P)
+ {
+ return (_Strstr(_S, _P));
+ }
+ /* Then the non-const overloads for C++. */
+ #pragma inline
+ void *memchr(void *_S, int _C, size_t _N)
+ {
+ return (_Memchr(_S, _C, _N));
+ }
+
+ #pragma inline
+ char *strchr(char *_S, int _C)
+ {
+ return (_Strchr(_S, _C));
+ }
+
+ #pragma inline
+ char *strpbrk(char *_S, const char *_P)
+ {
+ return (_Strpbrk(_S, _P));
+ }
+
+ #pragma inline
+ char *strrchr(char *_S, int _C)
+ {
+ return (_Strrchr(_S, _C));
+ }
+
+ #pragma inline
+ char *strstr(char *_S, const char *_P)
+ {
+ return (_Strstr(_S, _P));
+ }
+
+ #else /* !__cplusplus */
+ /* Then the overloads for C. */
+ #pragma inline
+ void *memchr(const void *_S, int _C, size_t _N)
+ {
+ return (_Memchr(_S, _C, _N));
+ }
+
+ #pragma inline
+ char *strchr(const char *_S, int _C)
+ {
+ return (_Strchr(_S, _C));
+ }
+
+ #pragma inline
+ char *strpbrk(const char *_S, const char *_P)
+ {
+ return (_Strpbrk(_S, _P));
+ }
+
+ #pragma inline
+ char *strrchr(const char *_S, int _C)
+ {
+ return (_Strrchr(_S, _C));
+ }
+
+ #pragma inline
+ char *strstr(const char *_S, const char *_P)
+ {
+ return (_Strstr(_S, _P));
+ }
+ #endif /* __cplusplus */
+
+ #pragma inline
+ char *strerror(int _Err)
+ {
+ return (_Strerror(_Err, 0));
+ }
+
+ #ifdef _STRING_MORE_INLINES
+ #pragma inline
+ int memcmp(const void *s1, const void *s2, size_t n)
+ /* Copied from memcmp.c */
+ { /* compare unsigned char s1[n], s2[n] */
+ const unsigned char *su1 = (const unsigned char *)s1;
+ const unsigned char *su2 = (const unsigned char *)s2;
+
+ for (; 0 < n; ++su1, ++su2, --n)
+ if (*su1 != *su2)
+ return (*su1 < *su2 ? -1 : +1);
+ return (0);
+ }
+
+ #pragma inline
+ void *memcpy(void *s1, const void *s2, size_t n)
+ /* Copied from memcpy.c */
+ { /* copy char s2[n] to s1[n] in any order */
+ char *su1 = (char *)s1;
+ const char *su2 = (const char *)s2;
+
+ for (; 0 < n; ++su1, ++su2, --n)
+ *su1 = *su2;
+ return (s1);
+ }
+
+ #pragma inline
+ void *memset(void *s, int c, size_t n) /* Copied from memset.c */
+ { /* store c throughout unsigned char s[n] */
+ const unsigned char uc = c;
+ unsigned char *su = (unsigned char *)s;
+
+ for (; 0 < n; ++su, --n)
+ *su = uc;
+ return (s);
+ }
+
+ #pragma inline
+ char *strcat(char *s1, const char *s2) /* Copied from strcat.c */
+ { /* copy char s2[] to end of s1[] */
+ char *s;
+
+ for (s = s1; *s != '\0'; ++s)
+ ; /* find end of s1[] */
+ for (; (*s = *s2) != '\0'; ++s, ++s2)
+ ; /* copy s2[] to end */
+ return (s1);
+ }
+
+ #pragma inline
+ int strcmp(const char *s1, const char *s2) /* Copied from strcmp.c */
+ { /* compare unsigned char s1[], s2[] */
+ for (; *s1 == *s2; ++s1, ++s2)
+ if (*s1 == '\0')
+ return (0);
+ return (*(unsigned char *)s1 < *(unsigned char *)s2
+ ? -1 : +1);
+ }
+
+ #pragma inline
+ char *strcpy(char *s1, const char *s2) /* Copied from strcpy.c */
+ { /* copy char s2[] to s1[] */
+ char *s = s1;
+
+ for (s = s1; (*s++ = *s2++) != '\0'; )
+ ;
+ return (s1);
+ }
+
+ #pragma inline
+ size_t strcspn(const char *s1, const char *s2)
+ /* Copied from strcspn.c */
+ { /* find index of first s1[i] that matches any s2[] */
+ const char *sc1, *sc2;
+
+ for (sc1 = s1; *sc1 != '\0'; ++sc1)
+ for (sc2 = s2; *sc2 != '\0'; ++sc2)
+ if (*sc1 == *sc2)
+ return (sc1 - s1);
+ return (sc1 - s1); /* terminating nulls match */
+ }
+
+ #pragma inline
+ size_t strlen(const char *s) /* Copied from strlen.c */
+ { /* find length of s[] */
+ const char *sc;
+
+ for (sc = s; *sc != '\0'; ++sc)
+ ;
+ return (sc - s);
+ }
+
+ #pragma inline
+ char *strncat(char *s1, const char *s2, size_t n)
+ /* Copied from strncat.c */
+ { /* copy char s2[max n] to end of s1[] */
+ char *s;
+
+ for (s = s1; *s != '\0'; ++s)
+ ; /* find end of s1[] */
+ for (; 0 < n && *s2 != '\0'; --n)
+ *s++ = *s2++; /* copy at most n chars from s2[] */
+ *s = '\0';
+ return (s1);
+ }
+
+ #pragma inline
+ int strncmp(const char *s1, const char *s2, size_t n)
+ /* Copied from strncmp.c */
+ { /* compare unsigned char s1[max n], s2[max n] */
+ for (; 0 < n; ++s1, ++s2, --n)
+ if (*s1 != *s2)
+ return ( *(unsigned char *)s1
+ < *(unsigned char *)s2 ? -1 : +1);
+ else if (*s1 == '\0')
+ return (0);
+ return (0);
+ }
+
+ #pragma inline
+ char *strncpy(char *s1, const char *s2, size_t n)
+ /* Copied from strncpy.c */
+ { /* copy char s2[max n] to s1[n] */
+ char *s;
+
+ for (s = s1; 0 < n && *s2 != '\0'; --n)
+ *s++ = *s2++; /* copy at most n chars from s2[] */
+ for (; 0 < n; --n)
+ *s++ = '\0';
+ return (s1);
+ }
+
+ #pragma inline
+ size_t strspn(const char *s1, const char *s2) /* Copied from strspn.c */
+ { /* find index of first s1[i] that matches no s2[] */
+ const char *sc1, *sc2;
+
+ for (sc1 = s1; *sc1 != '\0'; ++sc1)
+ for (sc2 = s2; ; ++sc2)
+ if (*sc2 == '\0')
+ return (sc1 - s1);
+ else if (*sc1 == *sc2)
+ break;
+ return (sc1 - s1); /* null doesn't match */
+ }
+
+ #pragma inline
+ void *_Memchr(const void *s, int c, size_t n) /* Copied from memchr.c */
+ { /* find first occurrence of c in s[n] */
+ const unsigned char uc = c;
+ const unsigned char *su = (const unsigned char *)s;
+
+ for (; 0 < n; ++su, --n)
+ if (*su == uc)
+ return ((void *)su);
+ return (0);
+ }
+
+ #pragma inline
+ char *_Strchr(const char *s, int c) /* Copied from strchr.c */
+ { /* find first occurrence of c in char s[] */
+ const char ch = c;
+
+ for (; *s != ch; ++s)
+ if (*s == '\0')
+ return (0);
+ return ((char *)s);
+ }
+
+ #pragma inline
+ char *_Strpbrk(const char *s1, const char *s2)
+ /* Copied from strpbrk.c */
+ { /* find index of first s1[i] that matches any s2[] */
+ const char *sc1, *sc2;
+
+ for (sc1 = s1; *sc1 != '\0'; ++sc1)
+ for (sc2 = s2; *sc2 != '\0'; ++sc2)
+ if (*sc1 == *sc2)
+ return ((char *)sc1);
+ return (0); /* terminating nulls match */
+ }
+
+ #pragma inline
+ char *_Strrchr(const char *s, int c) /* Copied from strrchr.c */
+ { /* find last occurrence of c in char s[] */
+ const char ch = c;
+ const char *sc;
+
+ for (sc = 0; ; ++s)
+ { /* check another char */
+ if (*s == ch)
+ sc = s;
+ if (*s == '\0')
+ return ((char *)sc);
+ }
+ }
+
+ #pragma inline
+ char *_Strstr(const char *s1, const char *s2) /* Copied from strstr.c */
+ { /* find first occurrence of s2[] in s1[] */
+ if (*s2 == '\0')
+ return ((char *)s1);
+ for (; (s1 = _Strchr(s1, *s2)) != 0; ++s1)
+ { /* match rest of prefix */
+ const char *sc1, *sc2;
+
+ for (sc1 = s1, sc2 = s2; ; )
+ if (*++sc2 == '\0')
+ return ((char *)s1);
+ else if (*++sc1 != *sc2)
+ break;
+ }
+ return (0);
+ }
+ #endif /* _STRING_MORE_INLINES */
+ _STD_END
+#endif /* _NO_DEFINITIONS_IN_HEADER_FILES */
+
+#endif /* _STRING */
+
+#if defined(_STD_USING) && defined(__cplusplus)
+ using _CSTD memchr; using _CSTD memcmp;
+ using _CSTD memcpy; using _CSTD memmove; using _CSTD memset;
+ using _CSTD strcat; using _CSTD strchr; using _CSTD strcmp;
+ using _CSTD strcoll; using _CSTD strcpy; using _CSTD strcspn;
+ using _CSTD strerror; using _CSTD strlen; using _CSTD strncat;
+ using _CSTD strncmp; using _CSTD strncpy; using _CSTD strpbrk;
+ using _CSTD strrchr; using _CSTD strspn; using _CSTD strstr;
+ using _CSTD strtok; using _CSTD strxfrm;
+#endif /* defined(_STD_USING) && defined(__cplusplus) */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Include/time.h b/AT91SAM7S256/SAM7S256/Include/time.h
new file mode 100644
index 0000000..f2ea765
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/time.h
@@ -0,0 +1,90 @@
+/* time.h standard header */
+#ifndef _TIME
+#define _TIME
+
+#ifndef _SYSTEM_BUILD
+#pragma system_include
+#endif
+
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+#include <ysizet.h>
+_C_STD_BEGIN
+
+ /* macros */
+#ifndef NULL
+ #define NULL _NULL
+#endif /* NULL */
+
+#define CLOCKS_PER_SEC _CPS
+
+ /* type definitions */
+#if !defined(_CLOCK_T) && !defined(__clock_t_defined)
+ #define _CLOCK_T
+ #define __clock_t_defined
+ #define _STD_USING_CLOCK_T
+ typedef long clock_t;
+#endif /* !defined(_CLOCK_T) && !defined(__clock_t_defined) */
+
+#if !defined(_TIME_T) && !defined(__time_t_defined)
+ #define _TIME_T
+ #define __time_t_defined
+ #define _STD_USING_TIME_T
+ typedef long time_t;
+#endif /* !defined(_TIME_T) && !defined(__time_t_defined) */
+
+struct tm
+{ /* date and time components */
+ int tm_sec;
+ int tm_min;
+ int tm_hour;
+ int tm_mday;
+ int tm_mon;
+ int tm_year;
+ int tm_wday;
+ int tm_yday;
+ int tm_isdst;
+};
+
+_EXTERN_C /* low-level functions */
+__INTRINSIC time_t time(time_t *);
+_END_EXTERN_C
+
+_C_LIB_DECL /* declarations */
+__INTRINSIC char * asctime(const struct tm *);
+__INTRINSIC clock_t clock(void);
+__INTRINSIC char * ctime(const time_t *);
+__INTRINSIC double difftime(time_t, time_t);
+__INTRINSIC struct tm * gmtime(const time_t *);
+__INTRINSIC struct tm * localtime(const time_t *);
+__INTRINSIC time_t mktime(struct tm *);
+__INTRINSIC size_t strftime(char *, size_t, const char *,
+ const struct tm *);
+_END_C_LIB_DECL
+_C_STD_END
+#endif /* _TIME */
+
+#if defined(_STD_USING) && defined(__cplusplus)
+ #ifdef _STD_USING_CLOCK_T
+ using _CSTD clock_t;
+ #endif /* _STD_USING_CLOCK_T */
+
+ #ifdef _STD_USING_TIME_T
+ using _CSTD time_t;
+ #endif /* _STD_USING_TIME_T */
+
+ #ifdef _STD_USING_CLOCKID_T
+ using _CSTD clockid_t;
+ #endif /* _STD_USING_CLOCKID_T */
+
+ using _CSTD tm;
+ using _CSTD asctime; using _CSTD clock; using _CSTD ctime;
+ using _CSTD difftime; using _CSTD gmtime; using _CSTD localtime;
+ using _CSTD mktime; using _CSTD strftime; using _CSTD time;
+#endif /* defined(_STD_USING) && defined(__cplusplus) */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Include/wchar.h b/AT91SAM7S256/SAM7S256/Include/wchar.h
new file mode 100644
index 0000000..2fa96aa
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/wchar.h
@@ -0,0 +1,339 @@
+/* wchar.h standard header */
+#ifndef _WCHAR
+#define _WCHAR
+
+#ifndef _SYSTEM_BUILD
+ #pragma system_include
+#endif
+
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+#include <ysizet.h>
+_C_STD_BEGIN
+
+ /* MACROS */
+#ifndef NULL
+ #define NULL _NULL
+#endif /* NULL */
+
+#define WCHAR_MIN _WCMIN
+#define WCHAR_MAX _WCMAX
+#define WEOF ((wint_t)(-1))
+
+#if _WCMAX < __UNSIGNED_SHORT_MAX__
+ #error "<wchart.h> wchar_t is too small."
+#endif
+
+ /* TYPE DEFINITIONS */
+typedef _Mbstatet mbstate_t;
+
+struct tm;
+struct _Filet;
+
+#ifndef _WCHART
+ #define _WCHART
+ typedef _Wchart wchar_t;
+#endif /* _WCHART */
+
+#ifndef _WINTT
+ #define _WINTT
+ typedef _Wintt wint_t;
+#endif /* _WINT */
+
+_C_LIB_DECL
+ /* stdio DECLARATIONS */
+#if _DLIB_FILE_DESCRIPTOR
+ __INTRINSIC wint_t fgetwc(struct _Filet *);
+ __INTRINSIC wchar_t * fgetws(wchar_t *, int, struct _Filet *);
+ __INTRINSIC wint_t fputwc(wchar_t, struct _Filet *);
+ __INTRINSIC int fputws(const wchar_t *, struct _Filet *);
+ __INTRINSIC int fwide(struct _Filet *, int);
+ __INTRINSIC int fwprintf(struct _Filet *,
+ const wchar_t *, ...);
+ __INTRINSIC int fwscanf(struct _Filet *,
+ const wchar_t *, ...);
+ __INTRINSIC wint_t getwc(struct _Filet *);
+ __INTRINSIC wint_t putwc(wchar_t, struct _Filet *);
+ __INTRINSIC wint_t ungetwc(wint_t, struct _Filet *);
+ __INTRINSIC int vfwprintf(struct _Filet *,
+ const wchar_t *, __Va_list);
+ #if _DLIB_ADD_C99_SYMBOLS
+ __INTRINSIC int vfwscanf(struct _Filet *,
+ const wchar_t *, __Va_list);
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+
+#endif /* _DLIB_FILE_DESCRIPTOR */
+
+__INTRINSIC wint_t getwchar(void);
+__INTRINSIC wint_t __ungetwchar(wint_t);
+__INTRINSIC wint_t putwchar(wchar_t);
+__INTRINSIC int swprintf(wchar_t *, size_t,
+ const wchar_t *, ...);
+__INTRINSIC int swscanf(const wchar_t *,
+ const wchar_t *, ...);
+__INTRINSIC int vswprintf(wchar_t *, size_t,
+ const wchar_t *, __Va_list);
+__INTRINSIC int vwprintf(const wchar_t *, __Va_list);
+#if _DLIB_ADD_C99_SYMBOLS
+ __INTRINSIC int vswscanf(const wchar_t *, const wchar_t *, __Va_list);
+ __INTRINSIC int vwscanf(const wchar_t *, __Va_list);
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+__INTRINSIC int wprintf(const wchar_t *, ...);
+__INTRINSIC int wscanf(const wchar_t *, ...);
+
+ /* stdlib DECLARATIONS */
+__INTRINSIC size_t mbrlen(const char *, size_t, mbstate_t *);
+__INTRINSIC size_t mbrtowc(wchar_t *, const char *, size_t,
+ mbstate_t *);
+__INTRINSIC size_t mbsrtowcs(wchar_t *, const char **, size_t,
+ mbstate_t *);
+__INTRINSIC int mbsinit(const mbstate_t *);
+__INTRINSIC size_t wcrtomb(char *, wchar_t, mbstate_t *);
+__INTRINSIC size_t wcsrtombs(char *, const wchar_t **, size_t,
+ mbstate_t *);
+__INTRINSIC long wcstol(const wchar_t *, wchar_t **, int);
+__INTRINSIC unsigned long wcstoul(const wchar_t *, wchar_t **, int);
+
+ /* string DECLARATIONS */
+__INTRINSIC wchar_t * wcscat(wchar_t *, const wchar_t *);
+__INTRINSIC int wcscmp(const wchar_t *, const wchar_t *);
+__INTRINSIC int wcscoll(const wchar_t *, const wchar_t *);
+__INTRINSIC wchar_t * wcscpy(wchar_t *, const wchar_t *);
+__INTRINSIC size_t wcscspn(const wchar_t *, const wchar_t *);
+__INTRINSIC size_t wcslen(const wchar_t *);
+__INTRINSIC wchar_t * wcsncat(wchar_t *,
+ const wchar_t *, size_t);
+__INTRINSIC int wcsncmp(const wchar_t *, const wchar_t *, size_t);
+__INTRINSIC wchar_t * wcsncpy(wchar_t *,
+ const wchar_t *, size_t);
+__INTRINSIC size_t wcsspn(const wchar_t *, const wchar_t *);
+__INTRINSIC wchar_t * wcstok(wchar_t *, const wchar_t *,
+ wchar_t **);
+__INTRINSIC size_t wcsxfrm(wchar_t *,
+ const wchar_t *, size_t);
+__INTRINSIC int wmemcmp(const wchar_t *, const wchar_t *, size_t);
+__INTRINSIC wchar_t * wmemcpy(wchar_t *,
+ const wchar_t *, size_t);
+__INTRINSIC wchar_t * wmemmove(wchar_t *, const wchar_t *, size_t);
+__INTRINSIC wchar_t * wmemset(wchar_t *, wchar_t, size_t);
+
+ /* time DECLARATIONS */
+__INTRINSIC size_t wcsftime(wchar_t *, size_t,
+ const wchar_t *, const struct tm *);
+
+
+__INTRINSIC wint_t btowc(int);
+#if _DLIB_ADD_C99_SYMBOLS
+ __INTRINSIC float wcstof(const wchar_t *, wchar_t **);
+ __INTRINSIC long double wcstold(const wchar_t *, wchar_t **);
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+__INTRINSIC double wcstod(const wchar_t *, wchar_t **);
+__INTRINSIC int wctob(wint_t);
+
+__INTRINSIC wint_t _Btowc(int);
+__INTRINSIC int _Wctob(wint_t);
+__INTRINSIC double _WStod(const wchar_t *, wchar_t **, long);
+__INTRINSIC float _WStof(const wchar_t *, wchar_t **, long);
+__INTRINSIC long double _WStold(const wchar_t *, wchar_t **, long);
+__INTRINSIC unsigned long _WStoul(const wchar_t *, wchar_t **, int);
+
+__INTRINSIC wchar_t * _Wmemchr(const wchar_t *, wchar_t, size_t);
+__INTRINSIC wchar_t * _Wcschr(const wchar_t *, wchar_t);
+__INTRINSIC wchar_t * _Wcspbrk(const wchar_t *, const wchar_t *);
+__INTRINSIC wchar_t * _Wcsrchr(const wchar_t *, wchar_t);
+__INTRINSIC wchar_t * _Wcsstr(const wchar_t *, const wchar_t *);
+_END_C_LIB_DECL
+
+/* IAR, can't use the Dinkum stratagem for wmemchr,... */
+
+#ifdef __cplusplus
+ __INTRINSIC const wchar_t * wmemchr(const wchar_t *, wchar_t, size_t);
+ __INTRINSIC const wchar_t * wcschr(const wchar_t *, wchar_t);
+ __INTRINSIC const wchar_t * wcspbrk(const wchar_t *, const wchar_t *);
+ __INTRINSIC const wchar_t * wcsrchr(const wchar_t *, wchar_t);
+ __INTRINSIC const wchar_t * wcsstr(const wchar_t *, const wchar_t *);
+ __INTRINSIC wchar_t * wmemchr(wchar_t *, wchar_t, size_t);
+ __INTRINSIC wchar_t * wcschr(wchar_t *, wchar_t);
+ __INTRINSIC wchar_t * wcspbrk(wchar_t *, const wchar_t *);
+ __INTRINSIC wchar_t * wcsrchr(wchar_t *, wchar_t);
+ __INTRINSIC wchar_t * wcsstr(wchar_t *, const wchar_t *);
+#else /* !__cplusplus */
+ __INTRINSIC wchar_t * wmemchr(const wchar_t *, wchar_t, size_t);
+ __INTRINSIC wchar_t * wcschr(const wchar_t *, wchar_t);
+ __INTRINSIC wchar_t * wcspbrk(const wchar_t *, const wchar_t *);
+ __INTRINSIC wchar_t * wcsrchr(const wchar_t *, wchar_t);
+ __INTRINSIC wchar_t * wcsstr(const wchar_t *, const wchar_t *);
+#endif /* __cplusplus */
+
+#ifndef _NO_DEFINITIONS_IN_HEADER_FILES
+ #ifdef __cplusplus
+ /* INLINES AND OVERLOADS, FOR C++ */
+
+ inline const wchar_t * wmemchr(const wchar_t *_S, wchar_t _C, size_t _N)
+ {
+ return (_Wmemchr(_S, _C, _N));
+ }
+
+ inline const wchar_t * wcschr(const wchar_t *_S, wchar_t _C)
+ {
+ return (_Wcschr(_S, _C));
+ }
+
+ inline const wchar_t * wcspbrk(const wchar_t *_S, const wchar_t *_P)
+ {
+ return (_Wcspbrk(_S, _P));
+ }
+
+ inline const wchar_t * wcsrchr(const wchar_t *_S, wchar_t _C)
+ {
+ return (_Wcsrchr(_S, _C));
+ }
+
+ inline const wchar_t * wcsstr(const wchar_t *_S, const wchar_t *_P)
+ {
+ return (_Wcsstr(_S, _P));
+ }
+
+ inline wchar_t * wmemchr(wchar_t *_S, wchar_t _C, size_t _N)
+ {
+ return (_Wmemchr(_S, _C, _N));
+ }
+
+ inline wchar_t * wcschr(wchar_t *_S, wchar_t _C)
+ {
+ return (_Wcschr(_S, _C));
+ }
+
+ inline wchar_t * wcspbrk(wchar_t *_S, const wchar_t *_P)
+ {
+ return (_Wcspbrk(_S, _P));
+ }
+
+ inline wchar_t * wcsrchr(wchar_t *_S, wchar_t _C)
+ {
+ return (_Wcsrchr(_S, _C));
+ }
+
+ inline wchar_t * wcsstr(wchar_t *_S, const wchar_t *_P)
+ {
+ return (_Wcsstr(_S, _P));
+ }
+
+ #else /* __cplusplus */
+ #pragma inline
+ wchar_t * wmemchr(const wchar_t *_S, wchar_t _C, size_t _N)
+ {
+ return (_Wmemchr(_S, _C, _N));
+ }
+
+ #pragma inline
+ wchar_t * wcschr(const wchar_t *_S, wchar_t _C)
+ {
+ return (_Wcschr(_S, _C));
+ }
+
+ #pragma inline
+ wchar_t * wcspbrk(const wchar_t *_S, const wchar_t *_P)
+ {
+ return (_Wcspbrk(_S, _P));
+ }
+
+ #pragma inline
+ wchar_t * wcsrchr(const wchar_t *_S, wchar_t _C)
+ {
+ return (_Wcsrchr(_S, _C));
+ }
+
+ #pragma inline
+ wchar_t * wcsstr(const wchar_t *_S, const wchar_t *_P)
+ {
+ return (_Wcsstr(_S, _P));
+ }
+ #endif /* __cplusplus */
+
+ #pragma inline
+ wint_t btowc(int _C)
+ { /* convert single byte to wide character */
+ return (_Btowc(_C));
+ }
+
+ #if _DLIB_ADD_C99_SYMBOLS
+ #pragma inline
+ float wcstof(const wchar_t *_S,
+ wchar_t **_Endptr)
+ { /* convert wide string to double */
+ return (_WStof(_S, _Endptr, 0));
+ }
+
+ #pragma inline
+ long double wcstold(const wchar_t *_S,
+ wchar_t **_Endptr)
+ { /* convert wide string to double */
+ return (_WStold(_S, _Endptr, 0));
+ }
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+
+ #pragma inline
+ double wcstod(const wchar_t *_S,
+ wchar_t **_Endptr)
+ { /* convert wide string to double */
+ return (_WStod(_S, _Endptr, 0));
+ }
+
+
+ #pragma inline
+ unsigned long wcstoul(const wchar_t *_S,
+ wchar_t **_Endptr, int _Base)
+ { /* convert wide string to unsigned long */
+ return (_WStoul(_S, _Endptr, _Base));
+ }
+
+ #pragma inline
+ int wctob(wint_t _Wc)
+ { /* convert wide character to single byte */
+ return (_Wctob(_Wc));
+ }
+
+#endif /* _NO_DEFINITIONS_IN_HEADER_FILES */
+
+#pragma inline
+static wchar_t _WLC(wchar_t _C)
+{ /* Convert wide character to lower case. */
+ return (_C | (L'a' - L'A'));
+}
+
+_C_STD_END
+#endif /* _WCHAR */
+
+#if defined(_STD_USING) && defined(__cplusplus)
+ using _CSTD mbstate_t; using _CSTD tm; using _CSTD wint_t;
+
+ using _CSTD btowc; using _CSTD fgetwc; using _CSTD fgetws; using _CSTD fputwc;
+ using _CSTD fputws; using _CSTD fwide; using _CSTD fwprintf;
+ using _CSTD fwscanf; using _CSTD getwc; using _CSTD getwchar;
+ using _CSTD mbrlen; using _CSTD mbrtowc; using _CSTD mbsrtowcs;
+ using _CSTD mbsinit; using _CSTD putwc; using _CSTD putwchar;
+ using _CSTD swprintf; using _CSTD swscanf; using _CSTD ungetwc;
+ using _CSTD vfwprintf; using _CSTD vswprintf; using _CSTD vwprintf;
+ using _CSTD wcrtomb; using _CSTD wprintf; using _CSTD wscanf;
+ using _CSTD wcsrtombs; using _CSTD wcstol; using _CSTD wcscat;
+ using _CSTD wcschr; using _CSTD wcscmp; using _CSTD wcscoll;
+ using _CSTD wcscpy; using _CSTD wcscspn; using _CSTD wcslen;
+ using _CSTD wcsncat; using _CSTD wcsncmp; using _CSTD wcsncpy;
+ using _CSTD wcspbrk; using _CSTD wcsrchr; using _CSTD wcsspn;
+ using _CSTD wcstod;
+ using _CSTD wcstoul; using _CSTD wcsstr;
+ using _CSTD wcstok; using _CSTD wcsxfrm; using _CSTD wctob;
+ using _CSTD wmemchr; using _CSTD wmemcmp; using _CSTD wmemcpy;
+ using _CSTD wmemmove; using _CSTD wmemset; using _CSTD wcsftime;
+ #if _DLIB_ADD_C99_SYMBOLS
+ using _CSTD vfwscanf; using _CSTD vswscanf; using _CSTD vwscanf;
+ using _CSTD wcstof; using _CSTD wcstold;
+ #endif /* _DLIB_ADD_C99_SYMBOLS */
+#endif /* defined(_STD_USING) && defined(__cplusplus) */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Include/xencoding_limits.h b/AT91SAM7S256/SAM7S256/Include/xencoding_limits.h
new file mode 100644
index 0000000..98d66b2
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/xencoding_limits.h
@@ -0,0 +1,55 @@
+/* xencoding_limits.h internal header file */
+/* Copyright (C) 2003 IAR Systems. All rights reserved. */
+
+#ifndef _XENCODING_LIMITS_H
+#define _XENCODING_LIMITS_H
+
+#ifndef _SYSTEM_BUILD
+ #pragma system_include
+#endif
+
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+
+ /* Multibyte encoding length. */
+#define _EncodingSb_LenMax 1
+
+#if __WCHAR_T_MAX__ <= 0xFF
+ #define _EncodingUtf8_LenMax 1
+#elif __WCHAR_T_MAX__ <= 0xFFFF
+ #define _EncodingUtf8_LenMax 3
+#else
+ #define _EncodingUtf8_LenMax 6
+#endif
+
+
+#if _DLIB_FULL_LOCALE_SUPPORT
+
+ #define _ENCODING_LEN_MAX _EncodingSb_LenMax
+
+ #ifdef _ENCODING_USE_UTF8
+ #if _ENCODING_LEN_MAX < _EncodingUtf8_LenMax
+ #undef _ENCODING_LEN_MAX
+ #define _ENCODING_LEN_MAX _EncodingUtf8_LenMax
+ #endif
+ #endif
+
+ #define _ENCODING_CUR_MAX (_Mbcurmax())
+
+#else /* _DLIB_FULL_LOCALE_SUPPORT */
+
+ /* Utility macro */
+ #ifdef _ENCODING_USE_UTF8
+ #define _ENCODING_WITH_USED(x) _EncodingUtf8_##x
+ #else
+ #define _ENCODING_WITH_USED(x) _EncodingSb_##x
+ #endif
+
+
+ #define _ENCODING_LEN_MAX _ENCODING_WITH_USED(LenMax)
+ #define _ENCODING_CUR_MAX _ENCODING_LEN_MAX
+
+#endif /* _DLIB_FULL_LOCALE_SUPPORT */
+
+#endif /* _XENCODING_LIMITS_H */
diff --git a/AT91SAM7S256/SAM7S256/Include/xlocale.h b/AT91SAM7S256/SAM7S256/Include/xlocale.h
new file mode 100644
index 0000000..bdb2c0d
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/xlocale.h
@@ -0,0 +1,130 @@
+/* xlocale.h internal header file */
+/* Copyright (C) 2003 IAR Systems. All rights reserved. */
+
+#ifndef _XLOCALE_H
+#define _XLOCALE_H
+
+#ifndef _SYSTEM_BUILD
+ #pragma system_include
+#endif
+
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+
+#include <xtls.h>
+
+#if _DLIB_FULL_LOCALE_SUPPORT
+
+#include <wchar.h>
+
+ /*
+ * ======================================================================
+ * Full support, it is possible to define several locales and switch
+ * between them.
+ */
+
+ #ifndef _LOCALE_USE_C
+ #error "_LOCALE_USE_C must be defined for _DLIB_FULL_LOCALE_SUPPORT"
+ #endif
+
+
+ __INTRINSIC int _LocaleForCat(int cat);
+ __INTRINSIC int _LocaleEncoding(void);
+
+
+ /*
+ * _LOCALE_LIST and _LOCALE_LIST1 -- Macros that can be used in
+ * conjunction with _LOCALE_LIST_HELPER and _LOCALE_LIST_HELPER1,
+ * respectively, to iterate over the defined locales.
+ */
+
+ /* Add the "C" locale, then include "localelist" to add the rest. */
+
+ #define _LOCALE_LIST0_0 _LOCALE_LIST_HELPER(C)
+ #define _LOCALE_LIST1_0(a1) _LOCALE_LIST_HELPER1(C,a1)
+
+ #include <xlocalelist.h>
+
+
+ /*
+ * Define unique id:s for each locale.
+ */
+
+ #define _LOCALE_LIST_HELPER(n) _Locale##n##_id,
+
+ enum
+ {
+ _LOCALE_LIST
+ _LocaleCount /* This eats last "," */
+ };
+
+ #undef _LOCALE_LIST_HELPER
+
+
+ /*
+ * The current lconv structure.
+ */
+
+ _TLS_DATA_DECL(struct lconv, _Locale_lconv);
+
+ _EXTERN_C
+ #define _LOCALE_LIST_HELPER1(n,f) \
+ extern int _Locale##n##_##f(int);
+ _LOCALE_LIST1(toupper)
+ _LOCALE_LIST1(tolower)
+ _LOCALE_LIST1(isalpha)
+ _LOCALE_LIST1(iscntrl)
+ _LOCALE_LIST1(islower)
+ _LOCALE_LIST1(ispunct)
+ _LOCALE_LIST1(isspace)
+ _LOCALE_LIST1(isupper)
+ #undef _LOCALE_LIST_HELPER1
+ #define _LOCALE_LIST_HELPER1(n,f) \
+ extern wint_t _Locale##n##_##f(wint_t);
+ _LOCALE_LIST1(towupper)
+ _LOCALE_LIST1(towlower)
+ #undef _LOCALE_LIST_HELPER1
+ #define _LOCALE_LIST_HELPER1(n,f) \
+ extern int _Locale##n##_##f(wint_t);
+ _LOCALE_LIST1(iswalpha)
+ _LOCALE_LIST1(iswcntrl)
+ _LOCALE_LIST1(iswlower)
+ _LOCALE_LIST1(iswpunct)
+ _LOCALE_LIST1(iswspace)
+ _LOCALE_LIST1(iswupper)
+ _LOCALE_LIST1(iswdigit)
+ _LOCALE_LIST1(iswxdigit)
+ #undef _LOCALE_LIST_HELPER1
+ _END_EXTERN_C
+
+
+
+#else /* !_DLIB_FULL_LOCALE_SUPPORT */
+
+ /*
+ * ======================================================================
+ * Reduced support. One locale (possibly "C") is hardwired.
+ */
+
+ /*
+ * This defined the Macro _LOCALE_WITH_USED (i.e. With used
+ * locale). Expands "f" to the corresponding identifier in the
+ * selected locale.
+ */
+
+ #include <xlocaleuse.h>
+
+ #ifdef _LOCALE_USE_C
+ #define _LOCALE_DECIMAL_POINT ('.')
+ #include <xlocale_c.h>
+ #endif
+
+#endif /* _DLIB_FULL_LOCALE_SUPPORT */
+
+
+#ifndef _LOCALE_DECIMAL_POINT
+ #define _LOCALE_DECIMAL_POINT (localeconv()->decimal_point[0])
+#endif
+
+#endif /* _XLOCALE_H */
diff --git a/AT91SAM7S256/SAM7S256/Include/xlocale_c.h b/AT91SAM7S256/SAM7S256/Include/xlocale_c.h
new file mode 100644
index 0000000..ead97fe
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/xlocale_c.h
@@ -0,0 +1,107 @@
+/* locale_c.h Standard "C" locale definitions. */
+#ifndef _LOCALE_C_H
+#define _LOCALE_C_H
+
+#ifndef _SYSTEM_BUILD
+ #pragma system_include
+#endif
+
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+#include <xtinfo.h>
+#include <wchar.h>
+
+_C_STD_BEGIN
+
+
+_C_LIB_DECL
+
+__INTRINSIC int _LocaleC_toupper(int);
+__INTRINSIC int _LocaleC_tolower(int);
+
+__INTRINSIC int _LocaleC_isalpha(int);
+__INTRINSIC int _LocaleC_iscntrl(int);
+__INTRINSIC int _LocaleC_islower(int);
+__INTRINSIC int _LocaleC_ispunct(int);
+__INTRINSIC int _LocaleC_isspace(int);
+__INTRINSIC int _LocaleC_isupper(int);
+
+__INTRINSIC wint_t _LocaleC_towupper(wint_t);
+__INTRINSIC wint_t _LocaleC_towlower(wint_t);
+
+__INTRINSIC int _LocaleC_iswalpha(wint_t);
+__INTRINSIC int _LocaleC_iswcntrl(wint_t);
+__INTRINSIC int _LocaleC_iswlower(wint_t);
+__INTRINSIC int _LocaleC_iswpunct(wint_t);
+__INTRINSIC int _LocaleC_iswspace(wint_t);
+__INTRINSIC int _LocaleC_iswupper(wint_t);
+__INTRINSIC int _LocaleC_iswdigit(wint_t);
+__INTRINSIC int _LocaleC_iswxdigit(wint_t);
+
+_END_C_LIB_DECL
+
+/*
+ * Inline definitions.
+ */
+
+#ifndef _NO_DEFINITIONS_IN_HEADER_FILES
+ /* Note: The first two must precede the functions they are used in. */
+ #pragma inline
+ int _LocaleC_islower(int _C)
+ {
+ return (_C>='a' && _C<='z');
+ }
+
+ #pragma inline
+ int _LocaleC_isupper(int _C)
+ {
+ return (_C>='A' && _C<='Z');
+ }
+
+ #pragma inline
+ int _LocaleC_isalpha(int _C)
+ {
+ return ( _LocaleC_islower(_C)
+ || _LocaleC_isupper(_C));
+ }
+
+ #pragma inline
+ int _LocaleC_iscntrl(int _C)
+ {
+ return ( (_C>='\x00' && _C<='\x1f')
+ || _C=='\x7f');
+ }
+
+ #pragma inline
+ int _LocaleC_ispunct(int _C)
+ {
+ return ( (_C>='\x21' && _C<='\x2f')
+ || (_C>='\x3a' && _C<='\x40')
+ || (_C>='\x5b' && _C<='\x60')
+ || (_C>='\x7b' && _C<='\x7e'));
+ }
+
+ #pragma inline
+ int _LocaleC_isspace(int _C)
+ {
+ return ( (_C>='\x09' && _C<='\x0d')
+ || (_C==' '));
+ }
+
+ #pragma inline
+ int _LocaleC_tolower(int _C)
+ {
+ return (_LocaleC_isupper(_C)?_C-'A'+'a':_C);
+ }
+
+ #pragma inline
+ int _LocaleC_toupper(int _C)
+ {
+ return (_LocaleC_islower(_C)?_C-'a'+'A':_C);
+ }
+
+#endif /* _NO_DEFINITIONS_IN_HEADER_FILES */
+_C_STD_END
+
+#endif /* _LOCALE_C_H */
diff --git a/AT91SAM7S256/SAM7S256/Include/xlocaleuse.h b/AT91SAM7S256/SAM7S256/Include/xlocaleuse.h
new file mode 100644
index 0000000..d7a882d
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/xlocaleuse.h
@@ -0,0 +1,180 @@
+/* localeuse.h - Pick the one locale to use (for non-full locale support).
+ * Copyright (C) 2003 IAR Systems. All rights reserved.
+ *
+ * Do not edit; this file was automatically generated by 'locparse'.
+ */
+
+#ifndef _LOCALEUSE_H
+#define _LOCALEUSE_H
+
+#ifndef _SYSTEM_BUILD
+ #pragma system_include
+#endif
+
+#define _LOCALE_CONCAT0(x,y) x ## y
+#define _LOCALE_CONCAT(x,y) _LOCALE_CONCAT0(x,y)
+
+#if defined(_LOCALE_USE_C)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleC_,f)
+#elif defined(_LOCALE_USE_POSIX)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocalePosix_,f)
+#elif defined(_LOCALE_USE_CS_CZ)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleCsCz_,f)
+#elif defined(_LOCALE_USE_DA_DK)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleDaDk_,f)
+#elif defined(_LOCALE_USE_DA_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleDaEu_,f)
+#elif defined(_LOCALE_USE_DE_AT)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleDeAt_,f)
+#elif defined(_LOCALE_USE_DE_BE)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleDeBe_,f)
+#elif defined(_LOCALE_USE_DE_CH)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleDeCh_,f)
+#elif defined(_LOCALE_USE_DE_DE)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleDeDe_,f)
+#elif defined(_LOCALE_USE_DE_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleDeEu_,f)
+#elif defined(_LOCALE_USE_DE_LU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleDeLu_,f)
+#elif defined(_LOCALE_USE_EL_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleElEu_,f)
+#elif defined(_LOCALE_USE_EL_GR)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleElGr_,f)
+#elif defined(_LOCALE_USE_EN_AU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEnAu_,f)
+#elif defined(_LOCALE_USE_EN_CA)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEnCa_,f)
+#elif defined(_LOCALE_USE_EN_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEnEu_,f)
+#elif defined(_LOCALE_USE_EN_GB)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEnGb_,f)
+#elif defined(_LOCALE_USE_EN_IE)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEnIe_,f)
+#elif defined(_LOCALE_USE_EN_NZ)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEnNz_,f)
+#elif defined(_LOCALE_USE_EN_US)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEnUs_,f)
+#elif defined(_LOCALE_USE_ES_AR)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsAr_,f)
+#elif defined(_LOCALE_USE_ES_BO)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsBo_,f)
+#elif defined(_LOCALE_USE_ES_CL)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsCl_,f)
+#elif defined(_LOCALE_USE_ES_CO)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsCo_,f)
+#elif defined(_LOCALE_USE_ES_DO)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsDo_,f)
+#elif defined(_LOCALE_USE_ES_EC)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsEc_,f)
+#elif defined(_LOCALE_USE_ES_ES)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsEs_,f)
+#elif defined(_LOCALE_USE_ES_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsEu_,f)
+#elif defined(_LOCALE_USE_ES_GT)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsGt_,f)
+#elif defined(_LOCALE_USE_ES_HN)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsHn_,f)
+#elif defined(_LOCALE_USE_ES_MX)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsMx_,f)
+#elif defined(_LOCALE_USE_ES_PA)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsPa_,f)
+#elif defined(_LOCALE_USE_ES_PE)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsPe_,f)
+#elif defined(_LOCALE_USE_ES_PY)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsPy_,f)
+#elif defined(_LOCALE_USE_ES_SV)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsSv_,f)
+#elif defined(_LOCALE_USE_ES_US)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsUs_,f)
+#elif defined(_LOCALE_USE_ES_UY)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsUy_,f)
+#elif defined(_LOCALE_USE_ES_VE)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEsVe_,f)
+#elif defined(_LOCALE_USE_ET_EE)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEtEe_,f)
+#elif defined(_LOCALE_USE_EU_ES)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleEuEs_,f)
+#elif defined(_LOCALE_USE_FI_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleFiEu_,f)
+#elif defined(_LOCALE_USE_FI_FI)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleFiFi_,f)
+#elif defined(_LOCALE_USE_FO_FO)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleFoFo_,f)
+#elif defined(_LOCALE_USE_FR_BE)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleFrBe_,f)
+#elif defined(_LOCALE_USE_FR_CA)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleFrCa_,f)
+#elif defined(_LOCALE_USE_FR_CH)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleFrCh_,f)
+#elif defined(_LOCALE_USE_FR_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleFrEu_,f)
+#elif defined(_LOCALE_USE_FR_FR)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleFrFr_,f)
+#elif defined(_LOCALE_USE_FR_LU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleFrLu_,f)
+#elif defined(_LOCALE_USE_GA_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleGaEu_,f)
+#elif defined(_LOCALE_USE_GA_IE)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleGaIe_,f)
+#elif defined(_LOCALE_USE_GL_ES)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleGlEs_,f)
+#elif defined(_LOCALE_USE_HR_HR)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleHrHr_,f)
+#elif defined(_LOCALE_USE_HU_HU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleHuHu_,f)
+#elif defined(_LOCALE_USE_ID_ID)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleIdId_,f)
+#elif defined(_LOCALE_USE_IS_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleIsEu_,f)
+#elif defined(_LOCALE_USE_IS_IS)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleIsIs_,f)
+#elif defined(_LOCALE_USE_IT_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleItEu_,f)
+#elif defined(_LOCALE_USE_IT_IT)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleItIt_,f)
+#elif defined(_LOCALE_USE_IW_IL)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleIwIl_,f)
+#elif defined(_LOCALE_USE_KL_GL)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleKlGl_,f)
+#elif defined(_LOCALE_USE_LT_LT)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleLtLt_,f)
+#elif defined(_LOCALE_USE_LV_LV)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleLvLv_,f)
+#elif defined(_LOCALE_USE_NL_BE)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleNlBe_,f)
+#elif defined(_LOCALE_USE_NL_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleNlEu_,f)
+#elif defined(_LOCALE_USE_NL_NL)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleNlNl_,f)
+#elif defined(_LOCALE_USE_NO_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleNoEu_,f)
+#elif defined(_LOCALE_USE_NO_NO)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleNoNo_,f)
+#elif defined(_LOCALE_USE_PL_PL)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocalePlPl_,f)
+#elif defined(_LOCALE_USE_PT_BR)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocalePtBr_,f)
+#elif defined(_LOCALE_USE_PT_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocalePtEu_,f)
+#elif defined(_LOCALE_USE_PT_PT)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocalePtPt_,f)
+#elif defined(_LOCALE_USE_RO_RO)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleRoRo_,f)
+#elif defined(_LOCALE_USE_RU_RU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleRuRu_,f)
+#elif defined(_LOCALE_USE_SL_SI)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleSlSi_,f)
+#elif defined(_LOCALE_USE_SV_EU)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleSvEu_,f)
+#elif defined(_LOCALE_USE_SV_FI)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleSvFi_,f)
+#elif defined(_LOCALE_USE_SV_SE)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleSvSe_,f)
+#elif defined(_LOCALE_USE_TR_TR)
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleTrTr_,f)
+#else
+#define _LOCALE_WITH_USED(f) _LOCALE_CONCAT(_LocaleC_,f)
+#define _LOCALE_USE_C
+#endif
+
+#endif /* _LOCALEUSE_H */
diff --git a/AT91SAM7S256/SAM7S256/Include/xmtx.h b/AT91SAM7S256/SAM7S256/Include/xmtx.h
new file mode 100644
index 0000000..1119946
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/xmtx.h
@@ -0,0 +1,41 @@
+/* xmtx.h internal header */
+#ifndef _XMTX
+#define _XMTX
+
+#ifndef _SYSTEM_BUILD
+#pragma system_include
+#endif
+
+#include <stdlib.h>
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+
+_C_LIB_DECL
+typedef void *_Rmtx;
+
+__INTRINSIC void _Mtxinit(_Rmtx *);
+__INTRINSIC void _Mtxdst(_Rmtx *);
+__INTRINSIC void _Mtxlock(_Rmtx *);
+__INTRINSIC void _Mtxunlock(_Rmtx *);
+
+#if !_MULTI_THREAD
+ #define _Mtxinit(mtx)
+ #define _Mtxdst(mtx)
+ #define _Mtxlock(mtx)
+ #define _Mtxunlock(mtx)
+
+ typedef char _Once_t;
+
+ #define _Once(cntrl, func) if (*(cntrl) == 0) (func)(), *(cntrl) = 2
+ #define _ONCE_T_INIT 0
+#else
+ #error "unknown library type"
+#endif /* _MULTI_THREAD */
+_END_C_LIB_DECL
+#endif /* _XMTX */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Include/xtinfo.h b/AT91SAM7S256/SAM7S256/Include/xtinfo.h
new file mode 100644
index 0000000..ff9d667
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/xtinfo.h
@@ -0,0 +1,68 @@
+/* xtinfo.h internal header */
+#ifndef _XTINFO
+#define _XTINFO
+
+#ifndef _SYSTEM_BUILD
+#pragma system_include
+#endif
+
+#include <time.h>
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+
+#include <xlocale.h>
+
+_C_STD_BEGIN
+
+ /* type definitions */
+typedef struct
+{ /* format strings for date and time */
+ const char *_Am_pm;
+ const char *_Days;
+ const char *_Abday;
+ const char *_Day;
+ const char *_Months;
+ const char *_Abmon;
+ const char *_Mon;
+ const char *_Formats;
+ const char *_D_t_fmt;
+ const char *_D_fmt;
+ const char *_T_fmt;
+ const char *_T_fmt_ampm;
+ const char *_Era_Formats;
+ const char *_Era_D_t_fmt;
+ const char *_Era_D_fmt;
+ const char *_Era_T_fmt;
+ const char *_Era_T_fmt_ampm;
+ const char *_Era;
+ const char *_Alt_digits;
+ const char *_Isdst;
+ const char *_Tzone;
+} _Tinfo;
+
+ /* declarations */
+_C_LIB_DECL
+__INTRINSIC size_t _CStrftime(char *, size_t, const char *,
+ const struct tm *, const _Tinfo *);
+__INTRINSIC const _Tinfo *_Getptimes(void);
+__INTRINSIC const _Tinfo *_GetptimesFor(int /* Id */);
+
+#if !_DLIB_FULL_LOCALE_SUPPORT
+
+#pragma inline
+const _Tinfo * _Getptimes(void)
+{
+ extern const _Tinfo _LOCALE_WITH_USED(Tinfo);
+ return &_LOCALE_WITH_USED(Tinfo);
+}
+#endif
+
+_END_C_LIB_DECL
+_C_STD_END
+#endif /* _XTINFO */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Include/xtls.h b/AT91SAM7S256/SAM7S256/Include/xtls.h
new file mode 100644
index 0000000..f85a018
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/xtls.h
@@ -0,0 +1,188 @@
+/* xtls.h internal header */
+#ifndef _XTLS
+#define _XTLS
+
+#ifndef _SYSTEM_BUILD
+#pragma system_include
+#endif
+
+#include <xmtx.h>
+
+/* We need to turn off this warning */
+#pragma diag_suppress = Pe076
+
+_C_LIB_DECL
+typedef void (*_Tlsdtor_t)(void*);
+__INTRINSIC int _Atthreadexit(void (*)(void));
+__INTRINSIC void _Destroytls(void);
+
+#define _IMPLICIT_EXTERN
+
+#if _COMPILER_TLS
+ #define _XTLS_QUAL _TLS_QUAL
+#else /* _COMPILER_TLS */
+ #define _XTLS_QUAL
+#endif /* _COMPILER_TLS */
+
+#if _GLOBAL_LOCALE
+ #define _TLS_LOCK(lock) _Locksyslock(lock)
+ #define _TLS_UNLOCK(lock) _Unlocksyslock(lock)
+#else /* _GLOBAL_LOCALE */
+ #define _TLS_LOCK(lock) (void)0
+ #define _TLS_UNLOCK(lock) (void)0
+#endif /* _GLOBAL_LOCALE */
+
+#define _XTLS_DTOR(name) _Tls_dtor_ ## name
+#define _XTLS_GET(name) _Tls_get_ ## name
+#define _XTLS_INIT(name) _Tls_init_ ## name
+#define _XTLS_KEY(name) _Tls_key_ ## name
+#define _XTLS_ONCE(name) _Tls_once_ ## name
+#define _XTLS_REG(name) _Tls_reg_ ## name
+#define _XTLS_SETUP(name) _Tls_setup_ ## name
+#define _XTLS_SETUPX(name) _Tls_setupx_ ## name
+
+#if _COMPILER_TLS
+ #define _CLEANUP(x) _Atthreadexit(x)
+#else /* _COMPILER_TLS */
+ #define _CLEANUP(x) _Atexit(x)
+#endif /* _COMPILER_TLS */
+
+#if !_MULTI_THREAD || _GLOBAL_LOCALE || _COMPILER_TLS
+
+ #define _TLS_DATA_DECL(type, name) \
+ extern int (*_XTLS_SETUP(name))(void); \
+ extern type name
+
+ #define _TLS_DEFINE_INIT(scope, type, name) \
+ scope _XTLS_QUAL type name
+
+ #define _TLS_DEFINE_NO_INIT(scope, type, name) \
+ scope int (* _XTLS_SETUP(name))(void) = 0
+
+ #define _TLS_DATA_DEF(scope, type, name, init) \
+ _TLS_DEFINE_INIT(scope, type, name) = init; \
+ _TLS_DEFINE_NO_INIT(scope, type, name)
+
+ #define _TLS_DEFINE_INIT_DT(scope, type, name) \
+ _TLS_DEFINE_INIT(scope, type, name)
+
+ #define _TLS_DEFINE_NO_INIT_DT(scope, type, name, dtor) \
+ static _Once_t _XTLS_ONCE(name) = _ONCE_T_INIT; \
+ static void _XTLS_DTOR(name)(void) \
+ { \
+ dtor(&(name)); \
+ } \
+ static void _XTLS_REG(name)(void) \
+ { \
+ _CLEANUP(_XTLS_DTOR(name)); \
+ } \
+ static int _XTLS_SETUPX(name)(void) \
+ { \
+ _Once(&_XTLS_ONCE(name), _XTLS_REG(name)); \
+ return 1; \
+ } \
+ scope int (*_XTLS_SETUP(name))(void) = _XTLS_SETUPX(name)
+
+ #define _TLS_DATA_DEF_DT(scope, type, name, init, dtor) \
+ _TLS_DEFINE_INIT_DT(scope, type, name) = init; \
+ _TLS_DEFINE_NO_INIT_DT(scope, type, name, dtor)
+
+ #define _TLS_DATA_PTR(name) \
+ ((_XTLS_SETUP(name) && _XTLS_SETUP(name)()), (&(name)))
+
+ #define _TLS_ARR_DECL(type, name) \
+ extern type name[]
+
+ #define _XTLS_ARR_DEF_INIT(scope, type, name, elts) \
+ scope _XTLS_QUAL type name[elts]
+
+ #define _TLS_ARR_DEF(scope, type, name, elts) \
+ _XTLS_ARR_DEF_INIT(scope, type, name, elts); \
+ _TLS_DEFINE_NO_INIT(scope, type, name)
+
+ #define _TLS_ARR_DEF_DT(scope, type, name, elts, dtor) \
+ _XTLS_ARR_DEF_INIT(scope, type, name, elts); \
+ _TLS_DEFINE_NO_INIT_DT(scope, type, name, dtor)
+
+ #define _TLS_ARR(name) \
+ ((_XTLS_SETUP(name) && _XTLS_SETUP(name)()), (&(name[0])))
+
+#else /* !_MULTI_THREAD || _GLOBAL_LOCALE || _COMPILER_TLS */
+
+ #define _TLS_DATA_DECL(type, name) \
+ extern type *_XTLS_GET(name)(void)
+
+ #define _TLS_DEFINE_INIT(scope, type, name) \
+ static const type _XTLS_INIT(name)
+
+ #define _XTLS_DEFINE_NO_INIT(scope, type, name, elts, dtor) \
+ static _Once_t _XTLS_ONCE(name) = _ONCE_T_INIT; \
+ static _Tlskey_t _XTLS_KEY(name); \
+ static void _XTLS_SETUP(name)(void) \
+ { \
+ _Tlsalloc(&_XTLS_KEY(name), dtor); \
+ } \
+ scope type *_XTLS_GET(name)(void) \
+ { \
+ type *_Ptr; \
+ _Once(&_XTLS_ONCE(name), _XTLS_SETUP(name)); \
+ if ((_Ptr = (type *)_Tlsget(_XTLS_KEY(name))) != 0) \
+ ; \
+ else if ((_Ptr = (type *)calloc(elts, sizeof(type))) == 0) \
+ ; \
+ else if (_Tlsset(_XTLS_KEY(name), (void*)_Ptr) != 0) \
+ free((void*)_Ptr), _Ptr = 0; \
+ else \
+ *_Ptr = _XTLS_INIT(name); \
+ return _Ptr; \
+ } \
+ extern int _TLS_Dummy
+
+ #define _TLS_DEFINE_NO_INIT(scope, type, name) \
+ _XTLS_DEFINE_NO_INIT(scope, type, name, 1, free)
+
+ #define _TLS_DATA_DEF(scope, type, name, init) \
+ _TLS_DEFINE_INIT(scope, type, name) = init; \
+ _XTLS_DEFINE_NO_INIT(scope, type, name, 1, free)
+
+ #define _TLS_DEFINE_INIT_DT(scope, type, name) \
+ _TLS_DEFINE_INIT(scope, type, name)
+
+ #define _XTLS_DEFINE_NO_INIT_DT(scope, type, name, elts, dtor) \
+ static void _XTLS_DTOR(name)(void* _Ptr) \
+ { \
+ (dtor)(_Ptr); \
+ free(_Ptr); \
+ } \
+ _XTLS_DEFINE_NO_INIT(scope, type, name, elts, _XTLS_DTOR(name))
+
+ #define _TLS_DEFINE_NO_INIT_DT(scope, type, name, dtor) \
+ _XTLS_DEFINE_NO_INIT_DT(scope, type, name, 1, dtor)
+
+ #define _TLS_DATA_DEF_DT(scope, type, name, init, dtor) \
+ _TLS_DEFINE_INIT_DT(scope, type, name) = init; \
+ _TLS_DEFINE_NO_INIT_DT(scope, type, name, dtor)
+
+ #define _TLS_DATA_PTR(name) _XTLS_GET(name)()
+
+ #define _TLS_ARR_DECL(type, name) \
+ _TLS_DATA_DECL(type, name)
+
+ #define _TLS_ARR_DEF(scope, type, name, elts) \
+ _TLS_DEFINE_INIT(scope, type, name) = {0}; \
+ _XTLS_DEFINE_NO_INIT(scope, type, name, elts, free)
+
+ #define _TLS_ARR_DEF_DT(scope, type, name, elts, dtor) \
+ _TLS_DEFINE_INIT(scope, type, name) = {0}; \
+ _XTLS_DEFINE_NO_INIT_DT(scope, type, name, elts, dtor)
+
+ #define _TLS_ARR(name) \
+ _XTLS_GET(name)()
+#endif /* !_MULTI_THREAD || _GLOBAL_LOCALE || _COMPILER_TLS */
+_END_C_LIB_DECL
+#endif /* _XTLS */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Include/ymath.h b/AT91SAM7S256/SAM7S256/Include/ymath.h
new file mode 100644
index 0000000..c8d3587
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/ymath.h
@@ -0,0 +1,91 @@
+/* ymath.h internal header */
+#ifndef _YMATH
+#define _YMATH
+
+#ifndef _SYSTEM_BUILD
+#pragma system_include
+#endif
+
+#include <yvals.h>
+_C_STD_BEGIN
+_C_LIB_DECL
+
+ /* MACROS FOR _Dtest RETURN (0 => ZERO) */
+#define _DENORM (-2) /* C9X only */
+#define _FINITE (-1)
+#define _INFCODE 1
+#define _NANCODE 2
+
+ /* TYPE DEFINITIONS */
+
+#if __SHORT_SIZE__ != 2
+#error "Float implementation assumes short is 2 bytes"
+#endif
+
+typedef union
+{ /* pun float types as integer array */
+ unsigned short _Word[__LONG_DOUBLE_SIZE__ / 2];
+ float _Float;
+ double _Double;
+ long double _Long_double;
+} _Dconst;
+
+ /* double DECLARATIONS */
+__INTRINSIC double _Cosh(double, double);
+__INTRINSIC short _Dtest(double);
+__INTRINSIC short _Exp(double *, double, short);
+__INTRINSIC double _Log(double, int);
+__INTRINSIC double _Sin(double, unsigned int);
+__INTRINSIC double _Sinh(double, double);
+extern const _Dconst _Denorm, _Hugeval, _Inf, _Nan, _Snan;
+
+ /* float DECLARATIONS */
+#ifndef _FLOAT_IS_DOUBLE
+ __INTRINSIC float _FCosh(float, float);
+ __INTRINSIC short _FDtest(float);
+ __INTRINSIC short _FExp(float *, float, short);
+ __INTRINSIC float _FLog(float, int);
+ __INTRINSIC float _FSin(float, unsigned int);
+ __INTRINSIC float _FSinh(float, float);
+ extern const _Dconst _FDenorm, _FHugeval, _FInf, _FNan, _FSnan;
+#endif /* _FLOAT_IS_DOUBLE */
+
+ /* long double DECLARATIONS */
+#ifndef _LONG_DOUBLE_IS_DOUBLE
+ __INTRINSIC long double _LCosh(long double, long double);
+ __INTRINSIC short _LDtest(long double);
+ __INTRINSIC short _LExp(long double *, long double, short);
+ __INTRINSIC long double _LLog(long double, int);
+ __INTRINSIC long double _LSin(long double, unsigned int);
+ __INTRINSIC long double _LSinh(long double, long double);
+ extern const _Dconst _LDenorm, _LInf, _LNan, _LSnan;
+#endif /* _LONG_DOUBLE_IS_DOUBLE */
+
+ /* long double ADDITIONS TO math.h NEEDED FOR complex */
+__INTRINSIC long double (atan2l)(long double, long double);
+__INTRINSIC long double (cosl)(long double);
+__INTRINSIC long double (expl)(long double);
+__INTRINSIC long double (ldexpl)(long double, int);
+__INTRINSIC long double (logl)(long double);
+__INTRINSIC long double (powl)(long double, long double);
+__INTRINSIC long double (sinl)(long double);
+__INTRINSIC long double (sqrtl)(long double);
+__INTRINSIC long double (tanl)(long double);
+ /* float ADDITIONS TO math.h NEEDED FOR complex */
+__INTRINSIC float (atan2f)(float, float);
+__INTRINSIC float (cosf)(float);
+__INTRINSIC float (expf)(float);
+__INTRINSIC float (ldexpf)(float, int);
+__INTRINSIC float (logf)(float);
+__INTRINSIC float (powf)(float, float);
+__INTRINSIC float (sinf)(float);
+__INTRINSIC float (sqrtf)(float);
+__INTRINSIC float (tanf)(float);
+_END_C_LIB_DECL
+_C_STD_END
+#endif /* _YMATH */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Include/ysizet.h b/AT91SAM7S256/SAM7S256/Include/ysizet.h
new file mode 100644
index 0000000..e3f9989
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/ysizet.h
@@ -0,0 +1,37 @@
+/* ysizet.h internal header file. */
+/* Copyright (C) 2003 IAR Systems. All rights reserved. */
+
+#ifndef _YSIZET_H
+#define _YSIZET_H
+
+#ifndef _SYSTEM_BUILD
+#pragma system_include
+#endif
+
+#ifndef _YVALS
+ #include <yvals.h>
+#endif
+
+_C_STD_BEGIN
+ /* type definitions */
+#if !defined(_SIZE_T) && !defined(_SIZET)
+ #define _SIZE_T
+ #define _SIZET
+ #define _STD_USING_SIZE_T
+typedef _Sizet size_t;
+#endif /* !defined(_SIZE_T) && !defined(_SIZET) */
+
+#define __DATA_PTR_MEM_HELPER1__(M, I) \
+typedef __DATA_MEM##I##_SIZE_TYPE__ M##_size_t;
+__DATA_PTR_MEMORY_LIST1__()
+#undef __DATA_PTR_MEM_HELPER1__
+
+_C_STD_END
+
+#if defined(_STD_USING) && defined(__cplusplus)
+ #ifdef _STD_USING_SIZE_T
+using _CSTD size_t;
+ #endif /* _STD_USING_SIZE_T */
+#endif /* defined(_STD_USING) && defined(__cplusplus) */
+
+#endif /* _YSIZET_H */
diff --git a/AT91SAM7S256/SAM7S256/Include/yvals.h b/AT91SAM7S256/SAM7S256/Include/yvals.h
new file mode 100644
index 0000000..78e90b7
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Include/yvals.h
@@ -0,0 +1,549 @@
+/* yvals.h internal configuration header file. */
+/* Copyright (c) 2001-2003 IAR Systems. All rights reserved. */
+
+/* __INTRINSIC
+ *
+ * Note: Redefined each time yvals.h is included to ensure that intrinsic
+ * support could be turned off individually for each system header file.
+ */
+#ifdef __INTRINSIC
+ #undef __INTRINSIC
+#endif /* __INTRINSIC */
+
+#ifndef __NO_INTRINSIC
+ #define __INTRINSIC __intrinsic
+#else
+ #define __INTRINSIC
+#endif
+
+
+#ifndef _YVALS
+#define _YVALS
+
+#ifndef _SYSTEM_BUILD
+#pragma system_include
+#endif
+
+ /* Convenience macros */
+#define _GLUE_B(x,y) x##y
+#define _GLUE(x,y) _GLUE_B(x,y)
+
+#define _GLUE3_B(x,y,z) x##y##z
+#define _GLUE3(x,y,z) _GLUE3_B(x,y,z)
+
+#define _STRINGIFY_B(x) #x
+#define _STRINGIFY(x) _STRINGIFY_B(x)
+
+ /* Versions */
+#define _CPPLIB_VER 312
+
+#ifndef __IAR_SYSTEMS_LIB__
+ #define __IAR_SYSTEMS_LIB__ 3
+#endif
+
+#if (__IAR_SYSTEMS_ICC__ < 6) || (__IAR_SYSTEMS_ICC__ > 6)
+ #error "<yvals.h> compiled with wrong (version of IAR) compiler"
+#endif
+
+/*
+ * Support for some C99 or other symbols
+ *
+ * This setting makes available some macros, functions, etc that are
+ * beneficial.
+ *
+ * Default is to include them.
+ */
+
+#ifndef _DLIB_ADD_C99_SYMBOLS
+ #define _DLIB_ADD_C99_SYMBOLS 1
+#endif /* _DLIB_ADD_C99_SYMBOLS */
+
+#ifndef _DLIB_ADD_EXTRA_SYMBOLS
+ #define _DLIB_ADD_EXTRA_SYMBOLS 1
+#endif /* _DLIB_ADD_EXTRA_SYMBOLS */
+
+
+ /* Configuration */
+#include <DLib_Defaults.h>
+
+#define _HAS_PRAGMA_PRINTF_ARGS
+
+#ifndef _NO_RETURN
+ #define _NO_RETURN
+#endif /* _NO_RETURN */
+
+ /* Floating-point */
+#ifndef _NO_FLOAT_FOLDING
+ #if __FLOAT_SIZE__ == __DOUBLE_SIZE__
+ #define _FLOAT_IS_DOUBLE
+ #define _F_FNAME(fun) _##fun
+ #define _F_FUN(fun) fun
+ #define _F_CTYPE _Dcomplex
+ #define _F_CONST(obj) _##obj._Double
+ #define _F_PTRCAST (double *)
+ #define _F_CAST (double)
+ #else
+ #define _F_FNAME(fun) _F##fun
+ #define _F_FUN(fun) fun##f
+ #define _F_CTYPE _Fcomplex
+ #define _F_CONST(obj) _F##obj._Float
+ #define _F_PTRCAST
+ #define _F_CAST
+ #endif
+ #if __LONG_DOUBLE_SIZE__ == __DOUBLE_SIZE__
+ #define _LONG_DOUBLE_IS_DOUBLE
+ #define _L_FNAME(fun) _##fun
+ #define _L_FUN(fun) fun
+ #define _L_CTYPE _Dcomplex
+ #define _L_CONST(obj) _##obj._Double
+ #define _L_PTRCAST (double *)
+ #define _L_CAST (double)
+ #else
+ #define _L_FNAME(fun) _L##fun
+ #define _L_FUN(fun) fun##l
+ #define _L_CTYPE _Lcomplex
+ #define _L_CONST(obj) _L##obj._Long_double
+ #define _L_PTRCAST
+ #define _L_CAST
+ #endif
+#else /* _NO_FLOAT_FOLDING */
+ #define _F_FNAME(fun) _F##fun
+ #define _F_FUN(fun) fun##f
+ #define _F_CTYPE _Fcomplex
+ #define _F_CONST(obj) _F##obj._Float
+ #define _F_PTRCAST
+ #define _F_CAST
+ #define _L_FNAME(fun) _L##fun
+ #define _L_FUN(fun) fun##l
+ #define _L_CTYPE _Lcomplex
+ #define _L_CONST(obj) _L##obj._Long_double
+ #define _L_PTRCAST
+ #define _L_CAST
+#endif /* !_NO_FLOAT_FOLDING */
+
+ /* NAMING PROPERTIES */
+/* #define _STD_LINKAGE defines C names as extern "C++" */
+/* #define _STD_USING exports C names from std to global, else reversed */
+#define _HAS_STRICT_LINKAGE 0 /* extern "C" in function type */
+
+ /* THREAD AND LOCALE CONTROL */
+#ifndef _MULTI_THREAD
+ #define _MULTI_THREAD 0 /* 0 for no locks, 1 for multithreaded library */
+#else
+ #error "IARs specific library routines can't do this currently."
+#endif /* _MULTI_THREAD */
+#define _GLOBAL_LOCALE 0 /* 0 for per-thread locales, 1 for shared */
+#define _FILE_OP_LOCKS 0 /* 0 for no file atomic locks, 1 for atomic */
+
+ /* THREAD-LOCAL STORAGE */
+#define _COMPILER_TLS 0 /* 1 if compiler supports TLS directly */
+#define _TLS_QUAL /* TLS qualifier, such as __declspec(thread), if any */
+
+#define _HAS_EXCEPTIONS 0
+#define _HAS_NAMESPACE 0
+#ifdef __WCHAR_T
+ #define _HAS_WCHAR_TYPE 1
+#endif /* __WCHAR_T */
+
+#if defined(__cplusplus)
+ #ifndef __ARRAY_OPERATORS
+ #error "<yvals.h> __ARRAY_OPERATORS not defined (c++)"
+ #endif /* __ARRAY_OPERATORS */
+#endif /* __cplusplus */
+
+ /* NAMESPACE CONTROL */
+#if defined(__cplusplus)
+ #if _HAS_NAMESPACE
+ #define _STD_BEGIN namespace std {
+ #define _STD_END }
+ #define _STD std::
+
+ #ifdef _STD_USING
+ #define _C_STD_BEGIN namespace std { /* only if *.c compiled as C++ */
+ #define _C_STD_END }
+ #define _CSTD std::
+ {
+ __dtor_rec const * * pp = (__dtor_rec const * *) (rec + 1);
+ /* Point to pointer */
+ rec->next = pp;
+ rec->object = NULL;
+
+ #else /* _STD_USING */
+ #define _GLOBAL_USING /* *.h in global namespace, c* imports to std */
+
+ #define _C_STD_BEGIN
+ #define _C_STD_END
+ #define _CSTD ::
+ #endif /* _STD_USING */
+
+ #define _C_LIB_DECL extern "C" { /* C has extern "C" linkage */
+ #define _END_C_LIB_DECL }
+ #define _EXTERN_C extern "C" {
+ #define _END_EXTERN_C }
+ #else /* _HAS_NAMESPACE */
+ #define _STD_BEGIN
+ #define _STD_END
+ #define _STD ::
+
+ #define _C_STD_BEGIN
+ #define _C_STD_END
+ #define _CSTD ::
+
+ #define _C_LIB_DECL extern "C" {
+ #define _END_C_LIB_DECL }
+ #define _EXTERN_C extern "C" {
+ #define _END_EXTERN_C }
+ #endif /* _HAS_NAMESPACE */
+
+#else /* __cplusplus */
+ #define _STD_BEGIN
+ #define _STD_END
+ #define _STD
+
+ #define _C_STD_BEGIN
+ #define _C_STD_END
+ #define _CSTD
+
+ #define _C_LIB_DECL
+ #define _END_C_LIB_DECL
+ #define _EXTERN_C
+ #define _END_EXTERN_C
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+ _STD_BEGIN
+ typedef bool _Bool;
+ _STD_END
+#endif /* __cplusplus */
+
+
+/* Map IAR compiler interface for long longs */
+#define __LONGLONG_SIZE__ __LONG_LONG_SIZE__
+#define __SIGNED_LONGLONG_MAX__ __SIGNED_LONG_LONG_MAX__
+#define __SIGNED_LONGLONG_MIN__ __SIGNED_LONG_LONG_MIN__
+#define __UNSIGNED_LONGLONG_MAX__ __UNSIGNED_LONG_LONG_MAX__
+
+#ifdef __LONG_LONG_SIZE__
+ #define _LONGLONG long long
+ #define _ULONGLONG unsigned long long
+ #define _LLONG_MAX __SIGNED_LONGLONG_MAX__
+ #define _ULLONG_MAX __UNSIGNED_LONGLONG_MAX__
+#endif /* __LONGLONG_SIZE__ */
+
+_C_STD_BEGIN
+ /* errno PROPERTIES */
+#define _EDOM 33
+#define _ERANGE 34
+#define _EFPOS 35
+#define _EILSEQ 36
+#define _ERRMAX 37
+
+ /* FLOATING-POINT PROPERTIES */
+#if __FLOAT_SIZE__ == 4
+ #define _FBIAS 0x7e /* IEEE 754 float properties */
+ #define _FOFF 7
+ #define _FMANTISSA 23
+ #if __LITTLE_ENDIAN__
+ #define _F0 1
+ #else
+ #define _F0 0
+ #endif
+#else
+ #error "<yvals.h> __FLOAT_SIZE__ not 4"
+#endif /* __FLOAT_SIZE__ */
+
+ /* double properties */
+#if __DOUBLE_SIZE__ == 8
+ #define _DBIAS 0x3fe /* IEEE 754 double properties */
+ #define _DOFF 4
+ #define _DMANTISSA 52
+ #if __LITTLE_ENDIAN__
+ #define _D0 3
+ #else
+ #define _D0 0
+ #endif
+#elif __DOUBLE_SIZE__ == 4
+ #define _DBIAS 0x7e
+ #define _DOFF 7
+ #define _DMANTISSA 23
+ #if __LITTLE_ENDIAN__
+ #define _D0 1
+ #else
+ #define _D0 0
+ #endif
+#else
+ #error "<yvals.h> __DOUBLE_SIZE__ not 4 or 8"
+#endif /* __DOUBLE_SIZE__ */
+
+ /* long double properties */
+#if __LONG_DOUBLE_SIZE__ == 10
+ #define _DLONG 1 /* IEEE 754 long double properties */
+ #define _LBIAS 0x3ffe
+ #define _LOFF 15
+ #define _LMANTISSA 63
+ #if __LITTLE_ENDIAN__
+ #define _L0 4
+ #else
+ #define _L0 0
+ #endif
+#elif __LONG_DOUBLE_SIZE__ == 16
+ #define _LMANTISSA 112
+ #error "<yvals.h> __LONG_DOUBLE_SIZE__ 16 isn't supported yet"
+#elif __LONG_DOUBLE_SIZE__ == 8
+ #define _DLONG 0
+ #define _LBIAS 0x3fe
+ #define _LOFF 4
+ #define _LMANTISSA 52
+ #if __LITTLE_ENDIAN__
+ #define _L0 3
+ #else
+ #define _L0 0
+ #endif
+#elif __LONG_DOUBLE_SIZE__ == 4
+ #define _DLONG 0
+ #define _LBIAS 0x7e
+ #define _LOFF 7
+ #define _LMANTISSA 23
+ #if __LITTLE_ENDIAN__
+ #define _L0 1
+ #else
+ #define _L0 0
+ #endif
+#else
+ #error "<yvals.h> __LONG_DOUBLE_SIZE__ not 4, 8 or 10"
+#endif /* __LONG_DOUBLE_SIZE__ */
+
+#include <xencoding_limits.h>
+
+ /* INTEGER PROPERTIES */
+#define _C2 1 /* 0 if not 2's complement */
+ /* MB_LEN_MAX */
+#define _MBMAX _ENCODING_LEN_MAX
+
+#define _MAX_EXP_DIG 8 /* for parsing numerics */
+#define _MAX_INT_DIG 32
+#define _MAX_SIG_DIG 36
+
+#ifdef _LONGLONG
+ typedef _LONGLONG _Longlong;
+ typedef _ULONGLONG _ULonglong;
+#else /* _LONGLONG */
+ typedef long _Longlong;
+ typedef unsigned long _ULonglong;
+ #define _LLONG_MAX __SIGNED_LONG_MAX__
+ #define _ULLONG_MAX __UNSIGNED_LONG_MAX__
+#endif /* _LONGLONG */
+
+#ifdef __cplusplus
+ #define _WCHART
+ typedef wchar_t _Wchart;
+ typedef wchar_t _Wintt;
+#else
+ typedef __WCHAR_T_TYPE__ _Wchart;
+ typedef __WCHAR_T_TYPE__ _Wintt;
+#endif
+
+#ifdef __SIGNED_WCHAR_T__
+ #define _WCMIN __WCHAR_T_MIN__
+ #define _WIMIN __WCHAR_T_MIN__
+#else
+ #define _WCMIN 0
+ #define _WIMIN 0
+#endif
+#define _WCMAX __WCHAR_T_MAX__
+#define _WIMAX __WCHAR_T_MAX__
+
+#if __INT_SIZE__ == 2
+ #define _ILONG 0
+#elif __INT_SIZE__ == 4
+ #define _ILONG 1
+#else
+ #error "__INT_SIZE__ must be 2 or 4"
+#endif /* __INT_SIZE__ */
+
+ /* POINTER PROPERTIES */
+#define _NULL 0 /* 0L if pointer same as long */
+
+typedef __PTRDIFF_T_TYPE__ _Ptrdifft;
+typedef __SIZE_T_TYPE__ _Sizet;
+
+ /* signal PROPERTIES */
+#define _SIGABRT 22
+#define _SIGMAX 32
+
+ /* stdarg PROPERTIES */
+#ifndef _VA_DEFINED
+ #ifndef _VA_LIST_STACK_MEMORY_ATTRIBUTE
+ #define _VA_LIST_STACK_MEMORY_ATTRIBUTE
+ #endif
+
+ typedef struct
+ {
+ char _VA_LIST_STACK_MEMORY_ATTRIBUTE *_Ap;
+ } __Va_list;
+#else /* _VA_DEFINED */
+ typedef _VA_LIST __Va_list;
+#endif /* !_VA_DEFINED */
+
+ /* stdlib PROPERTIES */
+#define _EXFAIL 1 /* EXIT_FAILURE */
+
+_EXTERN_C
+__INTRINSIC void _Atexit(void (*)(void));
+_END_EXTERN_C
+
+typedef struct _Mbstatet
+{ /* state of a multibyte translation */
+ unsigned long _Wchar;
+ unsigned short _Byte, _State;
+} _Mbstatet;
+
+ /* stdio PROPERTIES */
+#define _FNAMAX 260
+#define _FOPMAX 20
+#define _TNAMAX 16
+
+#if _DLIB_FILE_DESCRIPTOR
+#define _Filet FILE
+#endif
+
+typedef struct _Fpost
+{ /* file position */
+ long _Off; /* can be system dependent */
+ _Mbstatet _Wstate;
+} _Fpost;
+
+#ifndef _FPOSOFF
+ #define _FPOSOFF(fp) ((fp)._Off)
+#endif
+
+#define _FD_VALID(fd) (0 <= (fd)) /* fd is signed integer */
+#define _FD_INVALID (-1)
+
+ /* time PROPERTIES */
+#define _CPS 1
+/* Bias between 1900 (struct tm) and 1970 time_t. */
+#define _TBIAS_DAYS (70 * 365L + 17)
+#define _TBIAS (_TBIAS_DAYS * 86400LU)
+_C_STD_END
+
+ /* MULTITHREAD PROPERTIES */
+#if _MULTI_THREAD
+ _C_STD_BEGIN
+ _EXTERN_C
+ __INTRINSIC void _Locksyslock(unsigned int);
+ __INTRINSIC void _Unlocksyslock(unsigned int);
+ _END_EXTERN_C
+ _C_STD_END
+
+#else /* _MULTI_THREAD */
+ #define _Locksyslock(x) (void)0
+ #define _Unlocksyslock(x) (void)0
+#endif /* _MULTI_THREAD */
+
+ /* LOCK MACROS */
+#define _LOCK_LOCALE 0
+#define _LOCK_MALLOC 1
+#define _LOCK_STREAM 2
+#define _MAX_LOCK 3 /* one more than highest lock number */
+
+#ifdef __cplusplus
+ _STD_BEGIN
+ // CLASS _Lockit
+ class _Lockit
+ { // lock while object in existence -- MUST NEST
+ public:
+ #if _MULTI_THREAD
+ #define _LOCKIT(x) lockit x
+ explicit _Lockit()
+ : _Locktype(0)
+ { // set default lock
+ _Locksyslock(_Locktype);
+ }
+
+ explicit _Lockit(int _Type)
+ : _Locktype(_Type)
+ { // set the lock
+ _Locksyslock(_Locktype);
+ }
+
+ ~_Lockit()
+ { // clear the lock
+ _Unlocksyslock(_Locktype);
+ }
+
+ private:
+ _Lockit(const _Lockit&); // not defined
+ _Lockit& operator=(const _Lockit&); // not defined
+
+ int _Locktype;
+ #else /* _MULTI_THREAD */
+ #define _LOCKIT(x)
+ explicit _Lockit()
+ { // do nothing
+ }
+
+ explicit _Lockit(int)
+ { // do nothing
+ }
+
+ ~_Lockit()
+ { // do nothing
+ }
+ #endif /* _MULTI_THREAD */
+ };
+
+ class _Mutex
+ { // lock under program control
+ public:
+ #if _MULTI_THREAD
+ _Mutex();
+ ~_Mutex();
+ void _Lock();
+ void _Unlock();
+
+ private:
+ _Mutex(const _Mutex&); // not defined
+ _Mutex& operator=(const _Mutex&); // not defined
+ void *_Mtx;
+ #else /* _MULTI_THREAD */
+ void _Lock()
+ { // do nothing
+ }
+
+ void _Unlock()
+ { // do nothing
+ }
+ #endif /* _MULTI_THREAD */
+ };
+_STD_END
+#endif /* __cplusplus */
+
+ /* MISCELLANEOUS MACROS AND FUNCTIONS*/
+/* #define _ATEXIT_T void */
+#define _Mbstinit(x) mbstate_t x = {0, 0}
+
+#define _MAX max
+#define _MIN min
+
+#pragma inline
+static char _LC(char _C)
+{ /* Convert character to lower case. */
+ return ((_C) | ('a' - 'A'));
+}
+
+#if _HAS_NAMESPACE
+ #if defined(__cplusplus)
+ _STD_BEGIN
+ typedef ::va_list va_list;
+ _STD_END
+ #endif /* __cplusplus */
+#else
+#endif /* _HAS_NAMESPACE */
+
+#endif /* _YVALS */
+
+/*
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.
+ * Consult your license regarding permissions and restrictions.
+V3.12:0576 */
diff --git a/AT91SAM7S256/SAM7S256/Lib/dl4tptinl8n.h b/AT91SAM7S256/SAM7S256/Lib/dl4tptinl8n.h
new file mode 100644
index 0000000..008dce6
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Lib/dl4tptinl8n.h
@@ -0,0 +1,9 @@
+/* Customer-specific DLib configuration. */
+/* Copyright (C) 2003 IAR Systems. All rights reserved. */
+
+#ifndef _DLIB_CONFIG_H
+#define _DLIB_CONFIG_H
+
+/* No changes to the defaults. */
+
+#endif /* _DLIB_CONFIG_H */
diff --git a/AT91SAM7S256/SAM7S256/Lib/dl4tptinl8n.r79 b/AT91SAM7S256/SAM7S256/Lib/dl4tptinl8n.r79
new file mode 100644
index 0000000..8403996
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Lib/dl4tptinl8n.r79
Binary files differ
diff --git a/AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.d79 b/AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.d79
new file mode 100644
index 0000000..10dd62a
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.d79
Binary files differ
diff --git a/AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.mac b/AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.mac
new file mode 100644
index 0000000..6e30936
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Tools/FlashAT91SAM7Sxx.mac
@@ -0,0 +1,143 @@
+// ---------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+// File: SAM7_RAM.mac
+//
+// User setup file for CSPY debugger to simulate interrupt
+// driven Fibonacchi data input.
+// 1.1 18/Aug/04 JPP : Creation
+// 1.2 27/Aug/04 JPP : PLL setting
+// 1.3 04/Apr/05 JPP : Change variable name
+//
+// $Revision: 1.2 $
+//
+// ---------------------------------------------------------
+
+__var __mac_i;
+__var __mac_pt;
+
+execUserFlashInit()
+{
+ __message " ---------------------------------------- FLASH Download V1.1";
+ PllSetting();
+ execUserPreload();
+ execUserSetup();
+}
+execUserPreload()
+{
+//*
+ __message "-------------------------------Set CPSR ----------------------------------";
+ __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
+ __writeMemory32(0xD3,0x98,"Register");
+ __mac_i=__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X;
+
+//* Init AIC
+
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
+ __writeMemory32(0xffffffff,0xFFFFF124,"Memory");
+ __writeMemory32(0xffffffff,0xFFFFF128,"Memory");
+
+// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+ __readMemory32(0xFFFA0020,"Memory");
+ __readMemory32(0xFFFA0060,"Memory");
+ __readMemory32(0xFFFA00A0,"Memory");
+// disable peripheral clock Peripheral Clock Disable Register
+ __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
+
+ for (__mac_i=0;__mac_i < 8; __mac_i++)
+ {
+ // AT91C_BASE_AIC->AIC_EOICR
+ __mac_pt = __readMemory32(0xFFFFF130,"Memory");
+
+ }
+
+ PllSetting();
+//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
+ CheckNoRemap();
+//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
+ __mac_i=__readMemory32(0xFFFFF240,"Memory");
+ __message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
+ __mac_i=__readMemory32(0xFFFFF244,"Memory");
+ __message " ---------------------------------------- Extention 0x",__mac_i:%X;
+ __mac_i=__readMemory32(0xFFFFFF6C,"Memory");
+ __message " ---------------------------------------- Flash Version 0x",__mac_i:%X;
+//* Get the chip status
+
+//* Watchdog Disable
+// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
+ __writeMemory32(0x00008000,0xFFFFFD44,"Memory");
+}
+//-----------------------------------------------------------------------------
+// PllSetting
+//-------------------------------
+// Set PLL
+//-----------------------------------------------------------------------------
+PllSetting()
+{
+// -1- Enabling the Main Oscillator:
+//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
+//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+
+//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600
+// AT91C_CKGR_MOSCEN )); //0x0000 0001
+__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
+
+// -2- Wait
+// -3- Setting PLL and divider:
+// - div by 5 Fin = 3,6864 =(18,432 / 5)
+// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
+// for 96 MHz the erroe is 0.16%
+// Field out NOT USED = 0
+// PLLCOUNT pll startup time esrtimate at : 0.844 ms
+// PLLCOUNT 28 = 0.000844 /(1/32768)
+// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005
+// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
+// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000
+__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
+// -2- Wait
+// -5- Selection of Master Clock and Processor Clock
+// select the PLL clock divided by 2
+// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003
+// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004
+__writeMemory32(0x00000007,0xFFFFFC30,"Memory");
+
+ __message " ---------------------------------------- PLL Enable ";
+}
+
+CheckNoRemap()
+{
+//* Read the value at 0x0
+ __mac_i=__readMemory32(0x00000000,"Memory");
+ __mac_i=__mac_i+1;
+ __writeMemory32(__mac_i,0x00,"Memory");
+ __mac_pt=__readMemory32(0x00000000,"Memory");
+
+ if (__mac_i == __mac_pt)
+ {
+ __message "------------------------------- The Remap is done ----------------------------------------";
+
+ } else {
+ __message "------------------------------- The Remap is NOT -----------------------------------------";
+//* Toggel RESET The remap
+ __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
+ }
+
+}
+
+execUserSetup()
+{
+ __writeMemory32(0x0D3,0x98,"Register");
+ __message "-------------------------------Set PC ----------------------------------------";
+ __writeMemory32(0x00000000,0xB4,"Register");
+}
+
diff --git a/AT91SAM7S256/SAM7S256/Tools/LMS_V02.dep b/AT91SAM7S256/SAM7S256/Tools/LMS_V02.dep
new file mode 100644
index 0000000..f926153
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Tools/LMS_V02.dep
@@ -0,0 +1,3943 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+ <fileVersion>1</fileVersion>
+ <configuration>
+ <name>Binary Output</name>
+ <file>
+ <name>$PROJ_DIR$\..\Object\LMS_V02.d79</name>
+ <outputs>
+ <tool>
+ <name>XLINK</name>
+ <file>$PROJ_DIR$\..\Object\LMS_V02.map</file>
+ <file>$PROJ_DIR$\..\Object\LMS_V02.a79</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>XLINK</name>
+ <file>$PROJ_DIR$\at91SAM7S256_Remap.xcl</file>
+ <file>$PROJ_DIR$\..\Object\Cstartup.r79</file>
+ <file>$PROJ_DIR$\..\Object\Cstartup_SAM7.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_button.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_cmd.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_comm.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_display.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_input.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_ioctrl.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_loader.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_lowspeed.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_output.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_sound.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_ui.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_bt.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_button.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_display.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_hispeed.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_input.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_ioctrl.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_loader.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_lowspeed.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_output.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_sound.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_timer.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_usb.r79</file>
+ <file>$PROJ_DIR$\..\Object\m_sched.r79</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.r79</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_cmd.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_cmd.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_cmd.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\math.h</file>
+ <file>$PROJ_DIR$\..\Include\ymath.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_drawing.inc</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_drawing.inc</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_button.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_button.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_button.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_comm.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_comm.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_comm.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_display.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_display.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_display.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_input.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_input.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_input.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_ioctrl.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_ioctrl.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_ioctrl.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_loader.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_loader.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_loader.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_lowspeed.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_lowspeed.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_lowspeed.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_output.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_output.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_output.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\stdbool.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\stdbool.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_sound.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_sound.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_sound.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>[ROOT_NODE]</name>
+ <outputs>
+ <tool>
+ <name>XLINK</name>
+ <file>$PROJ_DIR$\..\Object\LMS_V02.map</file>
+ <file>$PROJ_DIR$\..\Object\LMS_V02.a79</file>
+ <file>$PROJ_DIR$\..\Object\LMS_V02.d79</file>
+ </tool>
+ </outputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_bt.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_bt.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_bt.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.r</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.r</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_ui.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_ui.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_ui.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\Display.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\LowBattery.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Font.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Step.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Cursor.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Running.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Port.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ok.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Wait.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Fail.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Info.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Icons.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_2.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_3.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_4.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_5.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_6.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_7.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_8.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_9.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_10.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_11.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_12.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_13.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_14.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_15.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_16.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Status.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Devices.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Connections.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ui.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Mainmenu.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu01.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu02.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu03.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu04.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu05.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu06.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu07.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Functions.inl</file>
+ <file>$PROJ_DIR$\..\..\Source\BtTest.inc</file>
+ <file>$PROJ_DIR$\..\..\Source\Test1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Test2.txt</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\Display.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\LowBattery.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Font.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Step.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Cursor.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Running.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Port.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ok.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Wait.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Fail.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Info.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Icons.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_2.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_3.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_4.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_5.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_6.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_7.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_8.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_9.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_10.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_11.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_12.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_13.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_14.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_15.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_16.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Status.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Devices.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Connections.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ui.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Mainmenu.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu01.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu02.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu04.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu05.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu06.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu07.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Functions.inl</file>
+ <file>$PROJ_DIR$\..\..\Source\BtTest.inc</file>
+ <file>$PROJ_DIR$\..\..\Source\Test1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Test2.txt</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\Include\Cstartup.s79</name>
+ <outputs>
+ <tool>
+ <name>AARM</name>
+ <file>$PROJ_DIR$\..\Object\Cstartup.r79</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>AARM</name>
+ <file>$PROJ_DIR$\..\Include\AT91SAM7S256_inc.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\Include\Cstartup_SAM7.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\Cstartup_SAM7.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\Cstartup_SAM7.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\AT91SAM7S256.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\AT91SAM7S256.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_button.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_button.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_button.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_display.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_display.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_display.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_hispeed.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_hispeed.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_hispeed.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_input.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_input.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_input.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_ioctrl.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_ioctrl.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_ioctrl.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_loader.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_loader.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_loader.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.r</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.r</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_lowspeed.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_lowspeed.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_lowspeed.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_output.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_output.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_output.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_sound.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_sound.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_sound.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.r</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound_adpcm.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.r</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound_adpcm.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_timer.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_timer.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_timer.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_usb.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_usb.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_usb.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\m_sched.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\m_sched.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\m_sched.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.c</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.c</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\Object\LMS_V02.pbd</name>
+ <inputs>
+ <tool>
+ <name>BILINK</name>
+ <file>$PROJ_DIR$\..\Object\Cstartup_SAM7.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_button.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_cmd.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_comm.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_display.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_input.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_ioctrl.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_loader.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_lowspeed.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_output.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_sound.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_ui.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_bt.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_button.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_display.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_hispeed.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_input.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_ioctrl.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_loader.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_lowspeed.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_output.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_sound.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_timer.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_usb.pbi</file>
+ <file>$PROJ_DIR$\..\Object\m_sched.pbi</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\Binary Output\Obj\LMS_V02.pbd</name>
+ <inputs>
+ <tool>
+ <name>BILINK</name>
+ <file>$PROJ_DIR$\Binary Output\Obj\Cstartup_SAM7.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_button.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_cmd.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_comm.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_display.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_input.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_ioctrl.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_loader.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_lowspeed.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_output.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_sound.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_ui.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_bt.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_button.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_display.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_hispeed.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_input.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_ioctrl.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_loader.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_lowspeed.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_output.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_sound.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_timer.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_usb.pbi</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\m_sched.pbi</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\Binary Output\Exe\LMS_V02.d79</name>
+ <inputs>
+ <tool>
+ <name>XLINK</name>
+ <file>$PROJ_DIR$\at91SAM7S256_Remap.xcl</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\Cstartup.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\Cstartup_SAM7.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_button.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_cmd.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_comm.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_display.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_input.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_ioctrl.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_loader.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_lowspeed.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_output.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_sound.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\c_ui.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_bt.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_button.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_display.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_hispeed.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_input.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_ioctrl.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_loader.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_lowspeed.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_output.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_sound.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_timer.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\d_usb.r79</file>
+ <file>$PROJ_DIR$\Binary Output\Obj\m_sched.r79</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.r79</file>
+ </tool>
+ </inputs>
+ </file>
+ <forcedrebuild>
+ <name>[REBUILD_ALL]</name>
+ </forcedrebuild>
+ </configuration>
+ <configuration>
+ <name>Debug</name>
+ <file>
+ <name>$PROJ_DIR$\..\Object\LMS_V02.d79</name>
+ <outputs>
+ <tool>
+ <name>XLINK</name>
+ <file>$PROJ_DIR$\..\Object\LMS_V02.map</file>
+ <file>$PROJ_DIR$\..\Object\LMS_V02.sim</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>XLINK</name>
+ <file>$PROJ_DIR$\at91SAM7S256_Remap.xcl</file>
+ <file>$PROJ_DIR$\..\Object\Cstartup.r79</file>
+ <file>$PROJ_DIR$\..\Object\Cstartup_SAM7.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_button.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_cmd.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_comm.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_display.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_input.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_ioctrl.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_loader.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_lowspeed.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_output.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_sound.r79</file>
+ <file>$PROJ_DIR$\..\Object\c_ui.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_bt.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_button.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_display.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_hispeed.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_input.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_ioctrl.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_loader.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_lowspeed.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_output.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_sound.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_timer.r79</file>
+ <file>$PROJ_DIR$\..\Object\d_usb.r79</file>
+ <file>$PROJ_DIR$\..\Object\m_sched.r79</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.r79</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_cmd.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_cmd.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_cmd.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\math.h</file>
+ <file>$PROJ_DIR$\..\Include\ymath.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_drawing.inc</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_drawing.inc</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_button.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_button.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_button.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_comm.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_comm.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_comm.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_display.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_display.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_display.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_input.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_input.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_input.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_ioctrl.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_ioctrl.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_ioctrl.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_loader.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_loader.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_loader.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_lowspeed.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_lowspeed.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_lowspeed.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_output.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_output.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_output.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\stdbool.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\stdbool.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_sound.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_sound.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_sound.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>[ROOT_NODE]</name>
+ <outputs>
+ <tool>
+ <name>XLINK</name>
+ <file>$PROJ_DIR$\..\Object\LMS_V02.map</file>
+ <file>$PROJ_DIR$\..\Object\LMS_V02.d79</file>
+ <file>$PROJ_DIR$\..\Object\LMS_V02.sim</file>
+ </tool>
+ </outputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_bt.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_bt.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_bt.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.r</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.r</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_ui.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\c_ui.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\c_ui.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\Display.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\LowBattery.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Font.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Step.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Cursor.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Running.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Port.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ok.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Wait.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Fail.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Info.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Icons.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_2.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_3.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_4.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_5.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_6.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_7.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_8.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_9.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_10.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_11.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_12.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_13.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_14.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_15.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_16.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Status.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Devices.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Connections.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ui.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Mainmenu.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu01.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu02.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu03.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu04.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu05.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu06.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu07.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Functions.inl</file>
+ <file>$PROJ_DIR$\..\..\Source\BtTest.inc</file>
+ <file>$PROJ_DIR$\..\..\Source\Test1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Test2.txt</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\stdio.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\Display.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\LowBattery.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Font.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Step.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Cursor.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Running.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Port.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ok.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Wait.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Fail.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Info.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Icons.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_2.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_3.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_4.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_5.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_6.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_7.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_8.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_9.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_10.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_11.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_12.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_13.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_14.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_15.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_16.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Status.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Devices.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Connections.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ui.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Mainmenu.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu01.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu02.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu04.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu05.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu06.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu07.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Functions.inl</file>
+ <file>$PROJ_DIR$\..\..\Source\BtTest.inc</file>
+ <file>$PROJ_DIR$\..\..\Source\Test1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Test2.txt</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\Include\Cstartup.s79</name>
+ <outputs>
+ <tool>
+ <name>AARM</name>
+ <file>$PROJ_DIR$\..\Object\Cstartup.r79</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>AARM</name>
+ <file>$PROJ_DIR$\..\Include\AT91SAM7S256_inc.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\Include\Cstartup_SAM7.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\Cstartup_SAM7.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\Cstartup_SAM7.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\AT91SAM7S256.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\AT91SAM7S256.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_button.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_button.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_button.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_display.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_display.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_display.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_hispeed.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_hispeed.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_hispeed.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_input.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_input.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_input.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_ioctrl.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_ioctrl.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_ioctrl.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_loader.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_loader.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_loader.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.r</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.r</file>
+ <file>$PROJ_DIR$\..\Include\string.h</file>
+ <file>$PROJ_DIR$\..\Include\yvals.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Defaults.h</file>
+ <file>$PROJ_DIR$\..\Include\DLib_Product.h</file>
+ <file>$PROJ_DIR$\..\Include\xencoding_limits.h</file>
+ <file>$PROJ_DIR$\..\Include\ysizet.h</file>
+ <file>$PROJ_DIR$\..\Include\ctype.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale.h</file>
+ <file>$PROJ_DIR$\..\Include\xtls.h</file>
+ <file>$PROJ_DIR$\..\Include\xmtx.h</file>
+ <file>$PROJ_DIR$\..\Include\stdlib.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocaleuse.h</file>
+ <file>$PROJ_DIR$\..\Include\xlocale_c.h</file>
+ <file>$PROJ_DIR$\..\Include\xtinfo.h</file>
+ <file>$PROJ_DIR$\..\Include\time.h</file>
+ <file>$PROJ_DIR$\..\Include\wchar.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_lowspeed.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_lowspeed.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_lowspeed.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_output.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_output.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_output.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_sound.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_sound.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_sound.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.r</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound_adpcm.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.r</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound_adpcm.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_timer.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_timer.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_timer.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_usb.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\d_usb.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\d_usb.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\m_sched.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Object\m_sched.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Object\m_sched.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.c</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.c</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\Object\LMS_V02.pbd</name>
+ <inputs>
+ <tool>
+ <name>BILINK</name>
+ <file>$PROJ_DIR$\..\Object\Cstartup_SAM7.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_button.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_cmd.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_comm.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_display.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_input.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_ioctrl.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_loader.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_lowspeed.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_output.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_sound.pbi</file>
+ <file>$PROJ_DIR$\..\Object\c_ui.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_bt.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_button.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_display.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_hispeed.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_input.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_ioctrl.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_loader.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_lowspeed.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_output.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_sound.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_timer.pbi</file>
+ <file>$PROJ_DIR$\..\Object\d_usb.pbi</file>
+ <file>$PROJ_DIR$\..\Object\m_sched.pbi</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\Debug\Obj\LMS_V02.pbd</name>
+ <inputs>
+ <tool>
+ <name>BILINK</name>
+ <file>$PROJ_DIR$\Debug\Obj\Cstartup_SAM7.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\c_button.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\c_cmd.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\c_comm.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\c_display.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\c_input.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\c_ioctrl.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\c_loader.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\c_lowspeed.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\c_output.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\c_sound.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\c_ui.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_bt.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_button.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_display.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_hispeed.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_input.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_ioctrl.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_loader.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_lowspeed.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_output.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_sound.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_timer.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\d_usb.pbi</file>
+ <file>$PROJ_DIR$\Debug\Obj\m_sched.pbi</file>
+ </tool>
+ </inputs>
+ </file>
+ </configuration>
+ <configuration>
+ <name>Release</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_cmd.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\c_cmd.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\c_cmd.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdio.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_drawing.inc</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdio.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_drawing.inc</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_button.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\c_button.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\c_button.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_comm.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\c_comm.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\c_comm.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\ctype.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtls.h</file>
+ <file>$TOOLKIT_DIR$\inc\xmtx.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocaleuse.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale_c.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtinfo.h</file>
+ <file>$TOOLKIT_DIR$\inc\time.h</file>
+ <file>$TOOLKIT_DIR$\inc\wchar.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\ctype.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtls.h</file>
+ <file>$TOOLKIT_DIR$\inc\xmtx.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocaleuse.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale_c.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtinfo.h</file>
+ <file>$TOOLKIT_DIR$\inc\time.h</file>
+ <file>$TOOLKIT_DIR$\inc\wchar.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_display.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\c_display.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\c_display.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_input.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\c_input.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\c_input.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_ioctrl.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\c_ioctrl.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\c_ioctrl.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_loader.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\c_loader.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\c_loader.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_lowspeed.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\c_lowspeed.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\c_lowspeed.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_output.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\c_output.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\c_output.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$TOOLKIT_DIR$\inc\stdio.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdbool.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$TOOLKIT_DIR$\inc\stdio.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdbool.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_sound.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\c_sound.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\c_sound.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>[ROOT_NODE]</name>
+ <outputs>
+ <tool>
+ <name>XLINK</name>
+ <file>$PROJ_DIR$\Release\Exe\LMS_V02.elf</file>
+ </tool>
+ </outputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\Release\Obj\LMS_V02.pbd</name>
+ <inputs>
+ <tool>
+ <name>BILINK</name>
+ <file>$PROJ_DIR$\Release\Obj\Cstartup_SAM7.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\c_button.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\c_cmd.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\c_comm.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\c_display.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\c_input.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\c_ioctrl.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\c_loader.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\c_lowspeed.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\c_output.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\c_sound.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\c_ui.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_bt.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_button.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_display.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_hispeed.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_input.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_ioctrl.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_loader.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_lowspeed.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_output.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_sound.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_timer.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\d_usb.pbi</file>
+ <file>$PROJ_DIR$\Release\Obj\m_sched.pbi</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_bt.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_bt.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_bt.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.r</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_bt.r</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_ui.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\c_ui.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\c_ui.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$TOOLKIT_DIR$\inc\stdio.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\ctype.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtls.h</file>
+ <file>$TOOLKIT_DIR$\inc\xmtx.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocaleuse.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale_c.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtinfo.h</file>
+ <file>$TOOLKIT_DIR$\inc\time.h</file>
+ <file>$TOOLKIT_DIR$\inc\wchar.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\Display.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\LowBattery.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Font.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Step.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Cursor.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Running.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Port.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ok.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Wait.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Fail.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Info.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Icons.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_2.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_3.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_4.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_5.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_6.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_7.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_8.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_9.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_10.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_11.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_12.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_13.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_14.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_15.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_16.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Status.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Devices.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Connections.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ui.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Mainmenu.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu01.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu02.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu03.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu04.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu05.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu06.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu07.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Functions.inl</file>
+ <file>$PROJ_DIR$\..\..\Source\BtTest.inc</file>
+ <file>$PROJ_DIR$\..\..\Source\Test1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Test2.txt</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$TOOLKIT_DIR$\inc\stdio.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\ctype.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtls.h</file>
+ <file>$TOOLKIT_DIR$\inc\xmtx.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocaleuse.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale_c.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtinfo.h</file>
+ <file>$TOOLKIT_DIR$\inc\time.h</file>
+ <file>$TOOLKIT_DIR$\inc\wchar.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\Display.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\LowBattery.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Font.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Step.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Cursor.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Running.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Port.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ok.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Wait.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Fail.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Info.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Icons.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_2.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_3.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_4.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_5.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_6.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_7.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_8.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_9.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_10.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_11.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_12.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_13.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_14.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_15.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\RCXintro_16.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Status.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Devices.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Connections.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Ui.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Mainmenu.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu01.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu02.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu04.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu05.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu06.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Submenu07.rms</file>
+ <file>$PROJ_DIR$\..\..\Source\Functions.inl</file>
+ <file>$PROJ_DIR$\..\..\Source\BtTest.inc</file>
+ <file>$PROJ_DIR$\..\..\Source\Test1.txt</file>
+ <file>$PROJ_DIR$\..\..\Source\Test2.txt</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\Include\Cstartup.s79</name>
+ <outputs>
+ <tool>
+ <name>AARM</name>
+ <file>$PROJ_DIR$\Release\Obj\Cstartup.r79</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>AARM</name>
+ <file>$PROJ_DIR$\..\Include\AT91SAM7S256_inc.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\Include\Cstartup_SAM7.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\Cstartup_SAM7.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\Cstartup_SAM7.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\Include\AT91SAM7S256.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\Include\AT91SAM7S256.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_button.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_button.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_button.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_button.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_display.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_display.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_display.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_display.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_hispeed.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_hispeed.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_hispeed.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_hispeed.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_input.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_input.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_input.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_input.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_ioctrl.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_ioctrl.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_ioctrl.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_ioctrl.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_loader.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_loader.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_loader.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.r</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\lib\dl4tptinl8n.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\ctype.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtls.h</file>
+ <file>$TOOLKIT_DIR$\inc\xmtx.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocaleuse.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale_c.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtinfo.h</file>
+ <file>$TOOLKIT_DIR$\inc\time.h</file>
+ <file>$TOOLKIT_DIR$\inc\wchar.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_loader.r</file>
+ <file>$TOOLKIT_DIR$\inc\string.h</file>
+ <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+ <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+ <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+ <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+ <file>$TOOLKIT_DIR$\inc\ctype.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtls.h</file>
+ <file>$TOOLKIT_DIR$\inc\xmtx.h</file>
+ <file>$TOOLKIT_DIR$\inc\stdlib.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocaleuse.h</file>
+ <file>$TOOLKIT_DIR$\inc\xlocale_c.h</file>
+ <file>$TOOLKIT_DIR$\inc\xtinfo.h</file>
+ <file>$TOOLKIT_DIR$\inc\time.h</file>
+ <file>$TOOLKIT_DIR$\inc\wchar.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_lowspeed.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_lowspeed.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_lowspeed.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_lowspeed.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_output.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_output.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_output.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_output.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_sound.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_sound.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_sound.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.r</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound_adpcm.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound.r</file>
+ <file>$PROJ_DIR$\..\..\Source\d_sound_adpcm.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_timer.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_timer.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_timer.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_timer.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_usb.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\d_usb.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\d_usb.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.r</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.h</file>
+ <file>$PROJ_DIR$\..\..\Source\d_usb.r</file>
+ </tool>
+ </inputs>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\m_sched.c</name>
+ <outputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\Release\Obj\m_sched.r79</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\Release\Obj\m_sched.pbi</file>
+ </tool>
+ </outputs>
+ <inputs>
+ <tool>
+ <name>ICCARM</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.c</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ </tool>
+ <tool>
+ <name>BICOMP</name>
+ <file>$PROJ_DIR$\..\..\Source\stdconst.h</file>
+ <file>$PROJ_DIR$\..\..\Source\modules.h</file>
+ <file>$PROJ_DIR$\..\..\Source\m_sched.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\ioat91sam7s256.h</file>
+ <file>$PROJ_DIR$\..\Include\sam7s256.c</file>
+ <file>$PROJ_DIR$\..\..\Source\c_comm.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_input.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_button.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_loader.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_sound.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_display.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_lowspeed.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_output.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd_bytecodes.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_cmd.iom</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ioctrl.h</file>
+ <file>$PROJ_DIR$\..\..\Source\c_ui.h</file>
+ </tool>
+ </inputs>
+ </file>
+ <forcedrebuild>
+ <name>[MULTI_TOOL]</name>
+ <tool>XLINK</tool>
+ </forcedrebuild>
+ </configuration>
+</project>
+
+
diff --git a/AT91SAM7S256/SAM7S256/Tools/LMS_V02.ewd b/AT91SAM7S256/SAM7S256/Tools/LMS_V02.ewd
new file mode 100644
index 0000000..2697e49
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Tools/LMS_V02.ewd
@@ -0,0 +1,1354 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+ <fileVersion>1</fileVersion>
+ <configuration>
+ <name>Debug</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>C-SPY</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>12</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCVariant</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacFile</name>
+ <state>$PROJ_DIR$\SAM7.mac</state>
+ </option>
+ <option>
+ <name>MemOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MemFile</name>
+ <state>$PROJ_DIR$\ioat91sam7s256.ddf</state>
+ </option>
+ <option>
+ <name>RunToEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RunToName</name>
+ <state>main</state>
+ </option>
+ <option>
+ <name>CExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDDFArgumentProducer</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadSuppressDownload</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDownloadVerifyAll</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashDownload</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashLoader</name>
+ <state>$PROJ_DIR$\FlashAT91SAM7Sxx.d79</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashLoaderSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCProductVersion</name>
+ <state>4.20A</state>
+ </option>
+ <option>
+ <name>OCDynDriverList</name>
+ <state>JLINK_ID</state>
+ </option>
+ <option>
+ <name>OCLastSavedByProductVersion</name>
+ <state>4.20A</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashLoaderArgs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadFlashBaseAddrOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashBaseAddr</name>
+ <state>0x00100000</state>
+ </option>
+ <option>
+ <name>OCDownloadAttachToProgram</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ARMSIM_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>OCSimDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ANGEL_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCAngelHeartbeat</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CAngelCommunication</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CAngelCommBaud</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CAngelCommPort</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ANGELTCPIP</name>
+ <state>aaa.bbb.ccc.ddd</state>
+ </option>
+ <option>
+ <name>DoAngelLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AngelLogFile</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IARROM_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CRomLogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRomLogFileEditB</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CRomCommunication</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRomCommPort</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRomCommBaud</name>
+ <version>0</version>
+ <state>7</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>JLINK_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>JLinkSpeed</name>
+ <state>32</state>
+ </option>
+ <option>
+ <name>CCJLinkHWReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkTRSTReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDoJlinkMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkLogFile</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCJLinkHWResetDelay</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkSpeedRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>JLinkInitialSpeed</name>
+ <state>32</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>MACRAIGOR_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>jtag</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>EmuSpeed</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>TCPIP</name>
+ <state>aaa.bbb.ccc.ddd</state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>DoEmuMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>EmuMultiTarget</name>
+ <state>0@ARM7TDMI</state>
+ </option>
+ <option>
+ <name>EmuHWReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CEmuCommBaud</name>
+ <version>0</version>
+ <state>4</state>
+ </option>
+ <option>
+ <name>CEmuCommPort</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>jtago</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UnusedAddr</name>
+ <state>0x00800000</state>
+ </option>
+ <option>
+ <name>CCMacraigorHWResetDelay</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>RDI_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CRDIDriverDll</name>
+ <state>Browse to your RDI driver</state>
+ </option>
+ <option>
+ <name>CRDILogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRDILogFileEdit</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCRDIHWReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchUndef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchData</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchPrefetch</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDIUseETM</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>THIRDPARTY_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CThirdPartyDriverDll</name>
+ <state>Browse to your third-party driver</state>
+ </option>
+ <option>
+ <name>CThirdPartyLogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CThirdPartyLogFileEditB</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <debuggerPlugins>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
+ <loadFlag>1</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
+ <loadFlag>1</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>
+ <loadFlag>1</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ </debuggerPlugins>
+ </configuration>
+ <configuration>
+ <name>Release</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>0</debug>
+ <settings>
+ <name>C-SPY</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>12</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCVariant</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>MemOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MemFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>RunToEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RunToName</name>
+ <state>main</state>
+ </option>
+ <option>
+ <name>CExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDDFArgumentProducer</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadSuppressDownload</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDownloadVerifyAll</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashDownload</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashLoader</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadFlashLoaderSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCProductVersion</name>
+ <state>4.20A</state>
+ </option>
+ <option>
+ <name>OCDynDriverList</name>
+ <state>ARMSIM_ID</state>
+ </option>
+ <option>
+ <name>OCLastSavedByProductVersion</name>
+ <state>4.20A</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashLoaderArgs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadFlashBaseAddrOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashBaseAddr</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadAttachToProgram</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ARMSIM_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OCSimDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ANGEL_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CCAngelHeartbeat</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CAngelCommunication</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CAngelCommBaud</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CAngelCommPort</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ANGELTCPIP</name>
+ <state>aaa.bbb.ccc.ddd</state>
+ </option>
+ <option>
+ <name>DoAngelLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AngelLogFile</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IARROM_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CRomLogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRomLogFileEditB</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CRomCommunication</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRomCommPort</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRomCommBaud</name>
+ <version>0</version>
+ <state>7</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>JLINK_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>JLinkSpeed</name>
+ <state>32</state>
+ </option>
+ <option>
+ <name>CCJLinkHWReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkTRSTReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDoJlinkMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkLogFile</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCJLinkHWResetDelay</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkSpeedRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>JLinkInitialSpeed</name>
+ <state>32</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>MACRAIGOR_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>jtag</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>EmuSpeed</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>TCPIP</name>
+ <state>aaa.bbb.ccc.ddd</state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>DoEmuMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>EmuMultiTarget</name>
+ <state>0@ARM7TDMI</state>
+ </option>
+ <option>
+ <name>EmuHWReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CEmuCommBaud</name>
+ <version>0</version>
+ <state>4</state>
+ </option>
+ <option>
+ <name>CEmuCommPort</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>jtago</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UnusedAddr</name>
+ <state>0x00800000</state>
+ </option>
+ <option>
+ <name>CCMacraigorHWResetDelay</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>RDI_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CRDIDriverDll</name>
+ <state>Browse to your RDI driver</state>
+ </option>
+ <option>
+ <name>CRDILogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRDILogFileEdit</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCRDIHWReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchUndef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchData</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchPrefetch</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDIUseETM</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>THIRDPARTY_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CThirdPartyDriverDll</name>
+ <state>Browse to your third-party driver</state>
+ </option>
+ <option>
+ <name>CThirdPartyLogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CThirdPartyLogFileEditB</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <debuggerPlugins>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
+ <loadFlag>1</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
+ <loadFlag>1</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>
+ <loadFlag>1</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ </debuggerPlugins>
+ </configuration>
+ <configuration>
+ <name>Binary Output</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>C-SPY</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>12</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCVariant</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacFile</name>
+ <state>$PROJ_DIR$\SAM7.mac</state>
+ </option>
+ <option>
+ <name>MemOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MemFile</name>
+ <state>$PROJ_DIR$\ioat91sam7s256.ddf</state>
+ </option>
+ <option>
+ <name>RunToEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RunToName</name>
+ <state>main</state>
+ </option>
+ <option>
+ <name>CExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDDFArgumentProducer</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadSuppressDownload</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDownloadVerifyAll</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashDownload</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashLoader</name>
+ <state>$PROJ_DIR$\FlashAT91SAM7Sxx.d79</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashLoaderSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCProductVersion</name>
+ <state>4.20A</state>
+ </option>
+ <option>
+ <name>OCDynDriverList</name>
+ <state>JLINK_ID</state>
+ </option>
+ <option>
+ <name>OCLastSavedByProductVersion</name>
+ <state>4.20A</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashLoaderArgs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>OCDownloadFlashBaseAddrOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OCDownloadFlashBaseAddr</name>
+ <state>0x00100000</state>
+ </option>
+ <option>
+ <name>OCDownloadAttachToProgram</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ARMSIM_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>OCSimDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ANGEL_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCAngelHeartbeat</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CAngelCommunication</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CAngelCommBaud</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CAngelCommPort</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ANGELTCPIP</name>
+ <state>aaa.bbb.ccc.ddd</state>
+ </option>
+ <option>
+ <name>DoAngelLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AngelLogFile</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IARROM_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CRomLogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRomLogFileEditB</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CRomCommunication</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRomCommPort</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRomCommBaud</name>
+ <version>0</version>
+ <state>7</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>JLINK_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>JLinkSpeed</name>
+ <state>32</state>
+ </option>
+ <option>
+ <name>CCJLinkHWReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkTRSTReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDoJlinkMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkDoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkLogFile</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCJLinkHWResetDelay</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCJLinkSpeedRadio</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>JLinkInitialSpeed</name>
+ <state>32</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>MACRAIGOR_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>jtag</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>EmuSpeed</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>TCPIP</name>
+ <state>aaa.bbb.ccc.ddd</state>
+ </option>
+ <option>
+ <name>DoLogfile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>LogFile</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>DoEmuMultiTarget</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>EmuMultiTarget</name>
+ <state>0@ARM7TDMI</state>
+ </option>
+ <option>
+ <name>EmuHWReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CEmuCommBaud</name>
+ <version>0</version>
+ <state>4</state>
+ </option>
+ <option>
+ <name>CEmuCommPort</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>jtago</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UnusedAddr</name>
+ <state>0x00800000</state>
+ </option>
+ <option>
+ <name>CCMacraigorHWResetDelay</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>RDI_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CRDIDriverDll</name>
+ <state>Browse to your RDI driver</state>
+ </option>
+ <option>
+ <name>CRDILogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CRDILogFileEdit</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>CCRDIHWReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchReset</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchUndef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchSWI</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchData</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchPrefetch</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchIRQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDICatchFIQ</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCRDIUseETM</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>THIRDPARTY_ID</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CThirdPartyDriverDll</name>
+ <state>Browse to your third-party driver</state>
+ </option>
+ <option>
+ <name>CThirdPartyLogFileCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CThirdPartyLogFileEditB</name>
+ <state>$TOOLKIT_DIR$\cspycomm.log</state>
+ </option>
+ <option>
+ <name>OCDriverInfo</name>
+ <state>1</state>
+ </option>
+ </data>
+ </settings>
+ <debuggerPlugins>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
+ <loadFlag>1</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
+ <loadFlag>1</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$EW_DIR$\common\plugins\Trace\Trace.ewplugin</file>
+ <loadFlag>1</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ <plugin>
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>
+ <loadFlag>0</loadFlag>
+ </plugin>
+ </debuggerPlugins>
+ </configuration>
+</project>
+
+
diff --git a/AT91SAM7S256/SAM7S256/Tools/LMS_V02.ewp b/AT91SAM7S256/SAM7S256/Tools/LMS_V02.ewp
new file mode 100644
index 0000000..91ec93f
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Tools/LMS_V02.ewp
@@ -0,0 +1,2531 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+ <fileVersion>1</fileVersion>
+ <configuration>
+ <name>Debug</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>GProcessorMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ExePath</name>
+ <state>..\Object</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>..\Object</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>..\Object</state>
+ </option>
+ <option>
+ <name>Variant</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GInterwork</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GStackAlign</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input variant</name>
+ <version>1</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Full formatting.</state>
+ </option>
+ <option>
+ <name>Output variant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Full formatting.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FPU</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGChipSelect</name>
+ <state>$PROJ_DIR$\AT91SAM7S256.i79</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>Use a customized C/C++ runtime library.</state>
+ </option>
+ <option>
+ <name>RTConfigPath</name>
+ <state>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</state>
+ </option>
+ <option>
+ <name>RTLibraryPath</name>
+ <state>$PROJ_DIR$\..\Lib\dl4tptinl8n.r79</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>4.20A</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>4.20A</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>11</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCIncludePaths</name>
+ <state>$PROJ_DIR$\..\..\</state>
+ <state>$PROJ_DIR$\..\Include\</state>
+ </option>
+ <option>
+ <name>CCDefines</name>
+ <state>PROTOTYPE_PCB_4</state>
+ <state>NEW_MENU</state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptSizeSpeed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptimization</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>1111111</state>
+ </option>
+ <option>
+ <name>CCMakeLibraryModule</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCObjUseModuleName</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCObjModuleName</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessorMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IStackAlign</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IInterwork</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.r79</state>
+ </option>
+ <option>
+ <name>CCLangSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptSizeSpeedSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptimizationSlave</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CCCodeFunctions</name>
+ <state>CODE</state>
+ </option>
+ <option>
+ <name>CCData</name>
+ <state>DATA</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraRules</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>5</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MakeLibrary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>UndefAsm</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefLine</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefTime</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefDate</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefTid</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefVer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AIncludes</name>
+ <state>$TOOLKIT_DIR$\INC\</state>
+ </option>
+ <option>
+ <name>AProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefLittleEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AOutputFile</name>
+ <state>$FILE_BNAME$.r79</state>
+ </option>
+ <option>
+ <name>AMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CUSTOM</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <extensions></extensions>
+ <cmdline></cmdline>
+ </data>
+ </settings>
+ <settings>
+ <name>BICOMP</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ <settings>
+ <name>BUILDACTION</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <prebuild></prebuild>
+ <postbuild></postbuild>
+ </data>
+ </settings>
+ <settings>
+ <name>XLINK</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>17</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>XOutOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>LMS_V02.d79</state>
+ </option>
+ <option>
+ <name>OutputFormat</name>
+ <version>10</version>
+ <state>16</state>
+ </option>
+ <option>
+ <name>FormatVariant</name>
+ <version>6</version>
+ <state>15</state>
+ </option>
+ <option>
+ <name>SecondaryOutputFile</name>
+ <state>(None for the selected format)</state>
+ </option>
+ <option>
+ <name>XDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AlwaysOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OverlapWarnings</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>NoGlobalCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XList</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>SegmentMap</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ListSymbols</name>
+ <state>2</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>XIncludes</name>
+ <state>$TOOLKIT_DIR$\LIB\</state>
+ </option>
+ <option>
+ <name>ModuleStatus</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XclOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XclFile</name>
+ <state>$PROJ_DIR$\at91SAM7S256_Remap.xcl</state>
+ </option>
+ <option>
+ <name>XclFileSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>DoFill</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FillerByte</name>
+ <state>0xFF</state>
+ </option>
+ <option>
+ <name>DoCrc</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcSize</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlgo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcPoly</name>
+ <state>0x11021</state>
+ </option>
+ <option>
+ <name>CrcCompl</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RangeCheckAlternatives</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>SuppressAllWarn</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>SuppressDiags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>TreatAsWarn</name>
+ <state></state>
+ </option>
+ <option>
+ <name>TreatAsErr</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ModuleLocalSym</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcBitOrder</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IncludeSuppressed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OXLibIOConfig</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ModuleSummary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>xcProgramEntryLabel</name>
+ <state>__program_start</state>
+ </option>
+ <option>
+ <name>DebugInformation</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RuntimeControl</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IoEmulation</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XcRTLibraryFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AllowExtraOutput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GenerateExtraOutput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XExtraOutOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ExtraOutputFile</name>
+ <state>LMS_V02.sim</state>
+ </option>
+ <option>
+ <name>ExtraOutputFormat</name>
+ <version>10</version>
+ <state>60</state>
+ </option>
+ <option>
+ <name>ExtraFormatVariant</name>
+ <version>6</version>
+ <state>2</state>
+ </option>
+ <option>
+ <name>xcOverrideProgramEntryLabel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>xcProgramEntryLabelSelect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ListOutputFormat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>BufferedTermOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OverlaySystemMap</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RawBinaryFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>RawBinarySymbol</name>
+ <state></state>
+ </option>
+ <option>
+ <name>RawBinarySegment</name>
+ <state></state>
+ </option>
+ <option>
+ <name>RawBinaryAlign</name>
+ <state></state>
+ </option>
+ <option>
+ <name>XLinkMisraHandler</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>XAR</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>XARInputs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>XAROverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XAROutput</name>
+ <state>###Unitialized###</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>BILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ </configuration>
+ <configuration>
+ <name>Release</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>0</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>GProcessorMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ExePath</name>
+ <state>Release\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>Release\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>Release\List</state>
+ </option>
+ <option>
+ <name>Variant</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GInterwork</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GStackAlign</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input variant</name>
+ <version>1</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state></state>
+ </option>
+ <option>
+ <name>Output variant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state></state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FPU</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelect</name>
+ <state>$TOOLKIT_DIR$\config\chip\</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state></state>
+ </option>
+ <option>
+ <name>RTConfigPath</name>
+ <state>$TOOLKIT_DIR$\LIB\dl4tptinl8n.h</state>
+ </option>
+ <option>
+ <name>RTLibraryPath</name>
+ <state>dl-stnl0.r79</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>4.20A</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state></state>
+ </option>
+ <option>
+ <name>GeneralMisraRules</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>11</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CCIncludePaths</name>
+ <state>$TOOLKIT_DIR$\INC\</state>
+ </option>
+ <option>
+ <name>CCDefines</name>
+ <state>NDEBUG</state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptSizeSpeed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptimization</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>1111111</state>
+ </option>
+ <option>
+ <name>CCMakeLibraryModule</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCObjUseModuleName</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCObjModuleName</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IProcessorMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IStackAlign</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IInterwork</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.r79</state>
+ </option>
+ <option>
+ <name>CCLangSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptSizeSpeedSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptimizationSlave</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CCCodeFunctions</name>
+ <state>CODE</state>
+ </option>
+ <option>
+ <name>CCData</name>
+ <state>DATA</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraRules</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>5</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MakeLibrary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>UndefAsm</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefLine</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefTime</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefDate</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefTid</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefVer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AIncludes</name>
+ <state>$TOOLKIT_DIR$\INC\</state>
+ </option>
+ <option>
+ <name>AProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefLittleEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AOutputFile</name>
+ <state>$FILE_BNAME$.r79</state>
+ </option>
+ <option>
+ <name>AMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CUSTOM</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <extensions></extensions>
+ <cmdline></cmdline>
+ </data>
+ </settings>
+ <settings>
+ <name>BICOMP</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ <settings>
+ <name>BUILDACTION</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <prebuild></prebuild>
+ <postbuild></postbuild>
+ </data>
+ </settings>
+ <settings>
+ <name>XLINK</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>17</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>XOutOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>LMS_V02.elf</state>
+ </option>
+ <option>
+ <name>OutputFormat</name>
+ <version>10</version>
+ <state>16</state>
+ </option>
+ <option>
+ <name>FormatVariant</name>
+ <version>6</version>
+ <state>15</state>
+ </option>
+ <option>
+ <name>SecondaryOutputFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>XDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AlwaysOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OverlapWarnings</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>NoGlobalCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>SegmentMap</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ListSymbols</name>
+ <state>2</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>XIncludes</name>
+ <state>###Uninitialized###</state>
+ </option>
+ <option>
+ <name>ModuleStatus</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XclOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XclFile</name>
+ <state>lnk0t.xcl</state>
+ </option>
+ <option>
+ <name>XclFileSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>DoFill</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FillerByte</name>
+ <state>0xFF</state>
+ </option>
+ <option>
+ <name>DoCrc</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcSize</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlgo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcPoly</name>
+ <state>0x11021</state>
+ </option>
+ <option>
+ <name>CrcCompl</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RangeCheckAlternatives</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>SuppressAllWarn</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>SuppressDiags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>TreatAsWarn</name>
+ <state></state>
+ </option>
+ <option>
+ <name>TreatAsErr</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ModuleLocalSym</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcBitOrder</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IncludeSuppressed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OXLibIOConfig</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ModuleSummary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>xcProgramEntryLabel</name>
+ <state></state>
+ </option>
+ <option>
+ <name>DebugInformation</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RuntimeControl</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IoEmulation</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XcRTLibraryFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AllowExtraOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenerateExtraOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XExtraOutOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ExtraOutputFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ExtraOutputFormat</name>
+ <version>10</version>
+ <state>60</state>
+ </option>
+ <option>
+ <name>ExtraFormatVariant</name>
+ <version>6</version>
+ <state>2</state>
+ </option>
+ <option>
+ <name>xcOverrideProgramEntryLabel</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>xcProgramEntryLabelSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ListOutputFormat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>BufferedTermOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OverlaySystemMap</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RawBinaryFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>RawBinarySymbol</name>
+ <state></state>
+ </option>
+ <option>
+ <name>RawBinarySegment</name>
+ <state></state>
+ </option>
+ <option>
+ <name>RawBinaryAlign</name>
+ <state></state>
+ </option>
+ <option>
+ <name>XLinkMisraHandler</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>XAR</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>XARInputs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>XAROverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XAROutput</name>
+ <state>###Unitialized###</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>BILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ </configuration>
+ <configuration>
+ <name>Binary Output</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>GProcessorMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ExePath</name>
+ <state>..\Object</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>..\Object</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>..\Object</state>
+ </option>
+ <option>
+ <name>Variant</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GInterwork</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GStackAlign</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input variant</name>
+ <version>1</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Full formatting.</state>
+ </option>
+ <option>
+ <name>Output variant</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Full formatting.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FPU</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGChipSelect</name>
+ <state>$PROJ_DIR$\AT91SAM7S256.i79</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>Use a customized C/C++ runtime library.</state>
+ </option>
+ <option>
+ <name>RTConfigPath</name>
+ <state>$PROJ_DIR$\..\Lib\dl4tptinl8n.h</state>
+ </option>
+ <option>
+ <name>RTLibraryPath</name>
+ <state>$PROJ_DIR$\..\Lib\dl4tptinl8n.r79</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>4.20A</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>4.20A</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>11</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCIncludePaths</name>
+ <state>$PROJ_DIR$\..\..\</state>
+ <state>$PROJ_DIR$\..\Include\</state>
+ </option>
+ <option>
+ <name>CCDefines</name>
+ <state>PROTOTYPE_PCB_4</state>
+ <state>NEW_MENU</state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptSizeSpeed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptimization</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>1111111</state>
+ </option>
+ <option>
+ <name>CCMakeLibraryModule</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCObjUseModuleName</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCObjModuleName</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessorMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IStackAlign</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IInterwork</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.r79</state>
+ </option>
+ <option>
+ <name>CCLangSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptSizeSpeedSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptimizationSlave</name>
+ <version>0</version>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CCCodeFunctions</name>
+ <state>CODE</state>
+ </option>
+ <option>
+ <name>CCData</name>
+ <state>DATA</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraRules</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>5</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MakeLibrary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>UndefAsm</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefLine</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefTime</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefDate</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefTid</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefVer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AIncludes</name>
+ <state>$TOOLKIT_DIR$\INC\</state>
+ </option>
+ <option>
+ <name>AProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>UndefLittleEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AOutputFile</name>
+ <state>$FILE_BNAME$.r79</state>
+ </option>
+ <option>
+ <name>AMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CUSTOM</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <extensions></extensions>
+ <cmdline></cmdline>
+ </data>
+ </settings>
+ <settings>
+ <name>BICOMP</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ <settings>
+ <name>BUILDACTION</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <prebuild></prebuild>
+ <postbuild></postbuild>
+ </data>
+ </settings>
+ <settings>
+ <name>XLINK</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>17</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>XOutOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>LMS_V02.d79</state>
+ </option>
+ <option>
+ <name>OutputFormat</name>
+ <version>10</version>
+ <state>16</state>
+ </option>
+ <option>
+ <name>FormatVariant</name>
+ <version>6</version>
+ <state>15</state>
+ </option>
+ <option>
+ <name>SecondaryOutputFile</name>
+ <state>(None for the selected format)</state>
+ </option>
+ <option>
+ <name>XDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AlwaysOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OverlapWarnings</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>NoGlobalCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XList</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>SegmentMap</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ListSymbols</name>
+ <state>2</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>XIncludes</name>
+ <state>$TOOLKIT_DIR$\LIB\</state>
+ </option>
+ <option>
+ <name>ModuleStatus</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XclOverride</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XclFile</name>
+ <state>$PROJ_DIR$\at91SAM7S256_Remap.xcl</state>
+ </option>
+ <option>
+ <name>XclFileSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>DoFill</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FillerByte</name>
+ <state>0xFF</state>
+ </option>
+ <option>
+ <name>DoCrc</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcSize</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlgo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcPoly</name>
+ <state>0x11021</state>
+ </option>
+ <option>
+ <name>CrcCompl</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RangeCheckAlternatives</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>SuppressAllWarn</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>SuppressDiags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>TreatAsWarn</name>
+ <state></state>
+ </option>
+ <option>
+ <name>TreatAsErr</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ModuleLocalSym</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcBitOrder</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IncludeSuppressed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OXLibIOConfig</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ModuleSummary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>xcProgramEntryLabel</name>
+ <state>__program_start</state>
+ </option>
+ <option>
+ <name>DebugInformation</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RuntimeControl</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IoEmulation</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XcRTLibraryFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AllowExtraOutput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GenerateExtraOutput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XExtraOutOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ExtraOutputFile</name>
+ <state>LMS_V02.a79</state>
+ </option>
+ <option>
+ <name>ExtraOutputFormat</name>
+ <version>10</version>
+ <state>57</state>
+ </option>
+ <option>
+ <name>ExtraFormatVariant</name>
+ <version>6</version>
+ <state>2</state>
+ </option>
+ <option>
+ <name>xcOverrideProgramEntryLabel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>xcProgramEntryLabelSelect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ListOutputFormat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>BufferedTermOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OverlaySystemMap</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>RawBinaryFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>RawBinarySymbol</name>
+ <state></state>
+ </option>
+ <option>
+ <name>RawBinarySegment</name>
+ <state></state>
+ </option>
+ <option>
+ <name>RawBinaryAlign</name>
+ <state></state>
+ </option>
+ <option>
+ <name>XLinkMisraHandler</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>XAR</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>XARInputs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>XAROverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>XAROutput</name>
+ <state>###Unitialized###</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>BILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ </configuration>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_button.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_cmd.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_comm.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_display.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_input.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_ioctrl.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_loader.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_lowspeed.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_output.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_sound.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\c_ui.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\Include\Cstartup.s79</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\Include\Cstartup_SAM7.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_bt.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_button.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_display.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_hispeed.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_input.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_ioctrl.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_loader.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_lowspeed.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_output.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_sound.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_timer.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\d_usb.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\..\Source\m_sched.c</name>
+ </file>
+</project>
+
+
diff --git a/AT91SAM7S256/SAM7S256/Tools/LMS_V02.eww b/AT91SAM7S256/SAM7S256/Tools/LMS_V02.eww
new file mode 100644
index 0000000..9993f4f
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Tools/LMS_V02.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+ <project>
+ <path>$WS_DIR$\LMS_V02.ewp</path>
+ </project>
+ <batchBuild/>
+</workspace>
+
+
diff --git a/AT91SAM7S256/SAM7S256/Tools/at91SAM7S256_64KRAM.xcl b/AT91SAM7S256/SAM7S256/Tools/at91SAM7S256_64KRAM.xcl
new file mode 100644
index 0000000..610e114
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Tools/at91SAM7S256_64KRAM.xcl
@@ -0,0 +1,136 @@
+// ---------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+// File: at91SAM7S256_64KRAM.xlc
+//
+// 1.1 24/Feb/05 JPP : Creation for 4.11A
+// $Revision: 1.1 $
+//
+// ---------------------------------------------------------
+
+//*************************************************************************
+// XLINK command file template for EWARM/ICCARM
+//
+// Usage: xlink -f lnkarm <your_object_file(s)>
+// -s <program start label> <C/C++ runtime library>
+//
+// $Revision: 1.1 $
+//*************************************************************************
+
+//************************************************
+// Inform the linker about the CPU family used.
+// AT91SAM7S256 Memory mapping
+// No remap
+// ROMSTART
+// Start address 0x0000 0000
+// Size 256 Kbo 0x0004 0000
+// RAMSTART
+// Start address 0x0020 0000
+// Size 64 Kbo 0x0001 0000
+// Remap done
+// RAMSTART
+// Start address 0x0000 0000
+// Size 64 Kbo 0x0001 0000
+// ROMSTART
+// Start address 0x0010 0000
+// Size 256 Kbo 0x0004 0000
+
+//************************************************
+-carm
+
+//*************************************************************************
+// Internal Ram segments mapped AFTER REMAP 64 K.
+//*************************************************************************
+// Use these addresses for the .
+-Z(CONST)INTRAMSTART_REMAP=00000000
+-Z(CONST)INTRAMEND_REMAP=0000FFFF
+
+//*************************************************************************
+// Read-only segments mapped to Flash 256 K.
+//*************************************************************************
+-DROMSTART=00000000
+-DROMEND=0003FFFF
+//*************************************************************************
+// Read/write segments mapped to 64 K RAM.
+//*************************************************************************
+-DRAMSTART=00000000
+-DRAMEND=0000FFFF
+
+//************************************************
+// Address range for reset and exception
+// vectors (INTVEC).
+// The vector area is 32 bytes,
+// an additional 32 bytes is allocated for the
+// constant table used by ldr PC in cstartup.s79.
+//************************************************
+-Z(CODE)INTVEC=00-3F
+
+//************************************************
+// Startup code and exception routines (ICODE).
+//************************************************
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
+-Z(CODE)SWITAB=ROMSTART-ROMEND
+
+//************************************************
+// Code segments may be placed anywhere.
+//************************************************
+-Z(CODE)CODE=ROMSTART-ROMEND
+
+//************************************************
+// Various constants and initializers.
+//************************************************
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND
+
+//************************************************
+// Data segments.
+//************************************************
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
+
+//************************************************
+// __ramfunc code copied to and executed from RAM.
+//************************************************
+-Z(DATA)CODE_I=RAMSTART-RAMEND
+-Z(CONST)CODE_ID=ROMSTART-ROMEND // Initializer for
+-QCODE_I=CODE_ID
+
+//************************************************
+// ICCARM produces code for __ramfunc functions in
+// CODE_I segments. The -Q XLINK command line
+// option redirects XLINK to emit the code in the
+// debug information associated with the CODE_I
+// segment, where the code will execute.
+//************************************************
+
+//*************************************************************************
+// Stack and heap segments.
+//*************************************************************************
+-D_CSTACK_SIZE=(100*4)
+-D_IRQ_STACK_SIZE=(3*8*4)
+
+-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
+-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
+
+//*************************************************************************
+// ELF/DWARF support.
+//
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.
+// Available format specifiers are:
+//
+// "-yn": Suppress DWARF debug output
+// "-yp": Multiple ELF program sections
+// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
+//
+// "-Felf" and the format specifiers can also be supplied directly as
+// command line options, or selected from the Xlink Output tab in the
+// IAR Embedded Workbench.
+//*************************************************************************
+
+// -Felf
diff --git a/AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.dbgdt b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.dbgdt
new file mode 100644
index 0000000..f01f0da
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.dbgdt
@@ -0,0 +1,96 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<Project>
+ <Desktop>
+ <Static>
+ <Debug-Log><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Build</Factory></Window><Window><Factory>Breakpoints</Factory></Window><Window><Factory>Watch</Factory></Window><Window><Factory>Find-in-Files</Factory></Window><Window><Factory>Register</Factory></Window><Window><Factory>Disassembly</Factory></Window></Windows></PreferedWindows></Debug-Log>
+ <Workspace>
+ <ColumnWidths>
+
+
+
+
+ <Column0>257</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
+ </Workspace>
+ <Disassembly>
+ <PreferedWindows>
+
+
+
+
+ <Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>
+
+
+
+ <MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>
+ <Build>
+
+
+
+
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>915</ColumnWidth1><ColumnWidth2>244</ColumnWidth2><ColumnWidth3>61</ColumnWidth3><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window><Window><Factory>Breakpoints</Factory></Window><Window><Factory>Watch</Factory></Window><Window><Factory>Find-in-Files</Factory></Window><Window><Factory>Register</Factory></Window><Window><Factory>Disassembly</Factory></Window></Windows></PreferedWindows></Build>
+ <Watch>
+ <Format>
+ <struct_types/>
+ <watch_formats>
+
+ <Fmt><Key>{W}Watch-0:FILEVERSION</Key><Value>4</Value></Fmt><Fmt><Key>{W}Watch-0:TimerValue</Key><Value>4</Value></Fmt><Fmt><Key>{W}Watch-1:AT91C_PITC_CPIV</Key><Value>4</Value></Fmt><Fmt><Key>{W}Watch-1:I2CTimerValue</Key><Value>4</Value></Fmt><Fmt><Key>{W}Watch-2:ErrorCode</Key><Value>4</Value></Fmt><Fmt><Key>{W}Watch-2:FileSize</Key><Value>4</Value></Fmt><Fmt><Key>{W}Watch-2:Handle</Key><Value>4</Value></Fmt></watch_formats>
+ </Format>
+ <PreferedWindows>
+
+
+
+
+ <Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window><Window><Factory>Build</Factory></Window><Window><Factory>Breakpoints</Factory></Window><Window><Factory>Find-in-Files</Factory></Window><Window><Factory>Register</Factory></Window><Window><Factory>Disassembly</Factory></Window></Windows></PreferedWindows>
+
+
+
+
+ <Column0>113</Column0><Column1>156</Column1><Column2>100</Column2><Column3>100</Column3></Watch>
+ <Memory>
+ <PreferedWindows>
+
+
+
+
+ <Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>
+
+
+ <FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory>
+ <Register><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window><Window><Factory>Build</Factory></Window><Window><Factory>Breakpoints</Factory></Window><Window><Factory>Watch</Factory></Window><Window><Factory>Find-in-Files</Factory></Window><Window><Factory>Disassembly</Factory></Window></Windows></PreferedWindows></Register>
+ <Breakpoints><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window><Window><Factory>Build</Factory></Window><Window><Factory>Watch</Factory></Window><Window><Factory>Find-in-Files</Factory></Window><Window><Factory>Register</Factory></Window><Window><Factory>Disassembly</Factory></Window></Windows></PreferedWindows></Breakpoints><CallStack><PreferedWindows><Position>1</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ViewArgs>1</ViewArgs></CallStack><Find-in-Files><ColumnWidth0>440</ColumnWidth0><ColumnWidth1>62</ColumnWidth1><ColumnWidth2>754</ColumnWidth2><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window><Window><Factory>Build</Factory></Window><Window><Factory>Breakpoints</Factory></Window><Window><Factory>Watch</Factory></Window><Window><Factory>Register</Factory></Window><Window><Factory>Disassembly</Factory></Window></Windows></PreferedWindows></Find-in-Files></Static>
+ <Windows>
+
+
+
+
+ <Wnd1>
+ <Tabs>
+ <Tab>
+ <Identity>TabID-4195-23593</Identity>
+ <TabName>Workspace</TabName>
+ <Factory>Workspace</Factory>
+ <Session>
+
+ <NodeDict><ExpandedNode>LMS_V02</ExpandedNode></NodeDict></Session>
+ </Tab>
+ </Tabs>
+
+ <SelectedTab>0</SelectedTab></Wnd1><Wnd0><Tabs><Tab><Identity>TabID-11197-31354</Identity><TabName>Disassembly</TabName><Factory>Disassembly</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd0></Windows>
+ <Editor>
+
+
+
+
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_display.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>668</SelStart><SelEnd>668</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_display.r</Filename><XPos>0</XPos><YPos>259</YPos><SelStart>11363</SelStart><SelEnd>11363</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\c_ioctrl.c</Filename><XPos>0</XPos><YPos>36</YPos><SelStart>1417</SelStart><SelEnd>1417</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\m_sched.c</Filename><XPos>0</XPos><YPos>39</YPos><SelStart>1211</SelStart><SelEnd>1211</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_bt.c</Filename><XPos>0</XPos><YPos>117</YPos><SelStart>2429</SelStart><SelEnd>2429</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_input.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>603</SelStart><SelEnd>603</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\c_ui.c</Filename><XPos>0</XPos><YPos>1375</YPos><SelStart>36567</SelStart><SelEnd>36567</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\c_sound.c</Filename><XPos>0</XPos><YPos>62</YPos><SelStart>1914</SelStart><SelEnd>1914</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_loader.r</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>638</SelStart><SelEnd>638</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\c_output.c</Filename><XPos>0</XPos><YPos>133</YPos><SelStart>4839</SelStart><SelEnd>4839</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_button.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>632</SelStart><SelEnd>632</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\c_display.c</Filename><XPos>0</XPos><YPos>801</YPos><SelStart>19634</SelStart><SelEnd>19634</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\c_input.c</Filename><XPos>1</XPos><YPos>185</YPos><SelStart>6947</SelStart><SelEnd>6947</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\SAM7S256\include\sam7s256.c</Filename><XPos>0</XPos><YPos>30</YPos><SelStart>994</SelStart><SelEnd>994</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_ioctrl.r</Filename><XPos>0</XPos><YPos>133</YPos><SelStart>10772</SelStart><SelEnd>10772</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_timer.c</Filename><XPos>0</XPos><YPos>24</YPos><SelStart>574</SelStart><SelEnd>574</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_ioctrl.c</Filename><XPos>0</XPos><YPos>6</YPos><SelStart>711</SelStart><SelEnd>711</SelEnd></Tab><ActiveTab>16</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\c_cmd.c</Filename><XPos>0</XPos><YPos>1116</YPos><SelStart>33574</SelStart><SelEnd>33574</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_output.c</Filename><XPos>0</XPos><YPos>225</YPos><SelStart>9950</SelStart><SelEnd>9950</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\SAM7S256\Include\Cstartup.s79</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\c_loader.c</Filename><XPos>0</XPos><YPos>92</YPos><SelStart>2451</SelStart><SelEnd>2460</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\c_comm.c</Filename><XPos>0</XPos><YPos>575</YPos><SelStart>16718</SelStart><SelEnd>16718</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_loader.c</Filename><XPos>0</XPos><YPos>349</YPos><SelStart>10885</SelStart><SelEnd>10893</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\SAM7S256\Include\ctype.h</Filename><XPos>0</XPos><YPos>83</YPos><SelStart>2117</SelStart><SelEnd>2117</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\SAM7S256\Include\xlocale_c.h</Filename><XPos>0</XPos><YPos>79</YPos><SelStart>2124</SelStart><SelEnd>2124</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Projects\LMS2006\Sys01\Main_V02\Firmware\Source\d_loader.h</Filename><XPos>0</XPos><YPos>41</YPos><SelStart>1537</SelStart><SelEnd>1547</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
+ <Positions>
+
+
+
+
+
+ <Top><Row0><Sizes><Toolbar-003be838><key>iaridepm1</key></Toolbar-003be838></Sizes></Row0><Row1><Sizes><Toolbar-037fec88><key>debuggergui1</key></Toolbar-037fec88></Sizes></Row1></Top><Left><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>682</Bottom><Right>331</Right><x>-2</x><y>-2</y><xscreen>0</xscreen><yscreen>0</yscreen><sizeHorzCX>0</sizeHorzCX><sizeHorzCY>0</sizeHorzCY><sizeVertCX>260156</sizeVertCX><sizeVertCY>721518</sizeVertCY></Rect></Wnd1></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1282</Right><x>-2</x><y>-2</y><xscreen>1284</xscreen><yscreen>200</yscreen><sizeHorzCX>1003125</sizeHorzCX><sizeHorzCY>210970</sizeHorzCY><sizeVertCX>156250</sizeVertCX><sizeVertCY>210970</sizeVertCY></Rect></Wnd0></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
+ </Desktop>
+</Project>
+
+
diff --git a/AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.dni b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.dni
new file mode 100644
index 0000000..66e9fea
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.dni
@@ -0,0 +1,33 @@
+[JLinkDriver]
+WatchVectorCatch=_ 0
+WatchCond=_ 0
+Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+[Interrupts]
+Enabled=1
+[MemoryMap]
+Enabled=0
+TypeVolition=1
+UnspecRange=1
+ActionState=1
+[TraceHelper]
+Enabled=0
+ShowSource=1
+[DisAssemblyWindow]
+NumStates=_ 2
+State 1=_ 1
+State 2=_ 1
+[Log file]
+LoggingEnabled=_ 0
+LogFile=_ ""
+Category=_ 0
+[TermIOLog]
+LoggingEnabled=_ 0
+LogFile=_ ""
+[Low Level]
+Pipeline mode=0
+Initialized=1
+[Disassemble mode]
+mode=0
+[Breakpoints]
+Count=0
diff --git a/AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.wsdt b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.wsdt
new file mode 100644
index 0000000..224de7b
--- /dev/null
+++ b/AT91SAM7S256/SAM7S256/Tools/settings/LMS_V02.wsdt
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<Workspace>
+ <ConfigDictionary>
+
+ <CurrentConfigs><Project>LMS_V02/Debug</Project></CurrentConfigs></ConfigDictionary>
+ <Desktop>
+ <Static>
+ <Workspace>
+ <ColumnWidths>
+
+
+
+
+ <Column0>195</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
+ </Workspace>
+ <Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>915</ColumnWidth1><ColumnWidth2>244</ColumnWidth2><ColumnWidth3>61</ColumnWidth3></Build><Find-in-Files><ColumnWidth0>440</ColumnWidth0><ColumnWidth1>62</ColumnWidth1><ColumnWidth2>754</ColumnWidth2></Find-in-Files><TerminalIO/><Profiling/><Breakpoints/><Debug-Log/></Static>
+ <Windows>
+
+ <Wnd0>
+ <Tabs>
+ <Tab>
+ <Identity>TabID-29459-4824</Identity>
+ <TabName>Workspace</TabName>
+ <Factory>Workspace</Factory>
+ <Session>
+
+ <NodeDict><ExpandedNode>LMS_V02</ExpandedNode></NodeDict></Session>
+ </Tab>
+ </Tabs>
+
+ <SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-23961-16799</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-20756-18779</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab><Tab><Identity>TabID-17651-16550</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory><Session/></Tab><Tab><Identity>TabID-5818-583</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1></Windows>
+ <Editor>
+
+
+
+
+ <Pane/><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
+ <Positions>
+
+
+
+
+
+ <Top><Row0><Sizes><Toolbar-003be838><key>iaridepm1</key></Toolbar-003be838></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>753</Bottom><Right>269</Right><x>-2</x><y>-2</y><xscreen>0</xscreen><yscreen>0</yscreen><sizeHorzCX>0</sizeHorzCX><sizeHorzCY>0</sizeHorzCY><sizeVertCX>211718</sizeVertCX><sizeVertCY>796413</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>151</Bottom><Right>1282</Right><x>-2</x><y>-2</y><xscreen>1284</xscreen><yscreen>153</yscreen><sizeHorzCX>1003125</sizeHorzCX><sizeHorzCY>161392</sizeHorzCY><sizeVertCX>0</sizeVertCX><sizeVertCY>0</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
+ </Desktop>
+</Workspace>
+
+