From 4695b47da68a5b2f75270bea21e15b8f1b9fd6ff Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Mon, 25 Jul 2016 15:18:40 +0200 Subject: Switch to CMSIS --- ucoo/hal/sdram/sdram.stm32f4.cc | 94 ++++++++++++++++--------------- ucoo/hal/sdram/sdram.stm32f4.hh | 3 +- ucoo/hal/sdram/test/test_sdram.stm32f4.cc | 39 +++++++------ 3 files changed, 69 insertions(+), 67 deletions(-) (limited to 'ucoo/hal/sdram') diff --git a/ucoo/hal/sdram/sdram.stm32f4.cc b/ucoo/hal/sdram/sdram.stm32f4.cc index 07baf54..4c224c0 100644 --- a/ucoo/hal/sdram/sdram.stm32f4.cc +++ b/ucoo/hal/sdram/sdram.stm32f4.cc @@ -22,12 +22,9 @@ // // }}} #include "ucoo/hal/sdram/sdram.hh" +#include "ucoo/arch/rcc.stm32.hh" #include "ucoo/utils/delay.hh" -#include -#include -#include - namespace ucoo { Sdram::Sdram (std::initializer_list ios, const Param ¶ms) @@ -41,20 +38,25 @@ Sdram::enable () // Setup GPIO, turn controller on. for (auto io : ios_) { - gpio_mode_setup (io.gpio, GPIO_MODE_AF, GPIO_PUPD_NONE, io.pins); - gpio_set_output_options (io.gpio, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, - io.pins); - gpio_set_af (io.gpio, GPIO_AF12, io.pins); + for (int i = 0; i < 16; i++) + { + if (io.pins & (1 << i)) + { + Gpio gpio (io.port[i]); + gpio.af (12); + gpio.speed (Gpio::Speed::SPEED_50MHZ); + } + } } - rcc_periph_clock_enable (RCC_FSMC); + rcc_peripheral_clock_enable (Rcc::FMC); // Prepare SDRAM clock, can only be HCLK/2 or HCLK/3. Can go slower than // requested, but not faster. - int clock_div = (rcc_ahb_frequency + params_.clock_hz - 1) + int clock_div = (rcc_ahb_freq_hz + params_.clock_hz - 1) / params_.clock_hz; if (clock_div < 2) clock_div = 2; assert (clock_div <= 3); - int clock_hz = rcc_ahb_frequency / clock_div; + int clock_hz = rcc_ahb_freq_hz / clock_div; int clock_ns = 1000000000 / clock_hz; // Prepare and set parameters. assert (params_.bank == 1 || params_.bank == 2); @@ -64,50 +66,50 @@ Sdram::enable () assert (params_.row_bits >= 11 && params_.row_bits <= 13); assert (params_.col_bits >= 8 && params_.col_bits <= 11); uint32_t sdcr = - FMC_SDCR_RPIPE_NONE + FMC_SDCR_RPIPE_None | FMC_SDCR_RBURST - | (clock_div == 2 ? FMC_SDCR_SDCLK_2HCLK : FMC_SDCR_SDCLK_3HCLK) - | (params_.cas << FMC_SDCR_CAS_SHIFT) - | (params_.banks == 2 ? FMC_SDCR_NB2 : FMC_SDCR_NB4) - | (params_.bits == 8 ? FMC_SDCR_MWID_8b - : (params_.bits == 16 ? FMC_SDCR_MWID_16b : FMC_SDCR_MWID_32b)) - | ((params_.row_bits - 11) << FMC_SDCR_NR_SHIFT) - | ((params_.col_bits - 8) << FMC_SDCR_NC_SHIFT); + | (clock_div == 2 ? FMC_SDCR_SDCLK_2Hclk : FMC_SDCR_SDCLK_3Hclk) + | (params_.cas << FMC_SDCR_CAS_Pos) + | (params_.banks == 2 ? 0 : FMC_SDCR_NB) + | (params_.bits == 8 ? FMC_SDCR_MWID_8B + : (params_.bits == 16 ? FMC_SDCR_MWID_16B : FMC_SDCR_MWID_32B)) + | ((params_.row_bits - 11) << FMC_SDCR_NR_Pos) + | ((params_.col_bits - 8) << FMC_SDCR_NC_Pos); uint32_t sdtr = - ((params_.trcd - 1) << FMC_SDTR_TRCD_SHIFT) - | ((params_.trp - 1) << FMC_SDTR_TRP_SHIFT) - | ((params_.twr - 1) << FMC_SDTR_TWR_SHIFT) - | ((params_.trc - 1) << FMC_SDTR_TRC_SHIFT) - | ((params_.tras - 1) << FMC_SDTR_TRAS_SHIFT) - | ((params_.txsr - 1) << FMC_SDTR_TXSR_SHIFT) - | ((params_.tmrd - 1) << FMC_SDTR_TMRD_SHIFT); + ((params_.trcd - 1) << FMC_SDTR_TRCD_Pos) + | ((params_.trp - 1) << FMC_SDTR_TRP_Pos) + | ((params_.twr - 1) << FMC_SDTR_TWR_Pos) + | ((params_.trc - 1) << FMC_SDTR_TRC_Pos) + | ((params_.tras - 1) << FMC_SDTR_TRAS_Pos) + | ((params_.txsr - 1) << FMC_SDTR_TXSR_Pos) + | ((params_.tmrd - 1) << FMC_SDTR_TMRD_Pos); if (params_.bank == 1) { - FMC_SDCR1 = sdcr; - FMC_SDTR1 = sdtr; + reg::FMC_Bank5_6->SDCR[0] = sdcr; + reg::FMC_Bank5_6->SDTR[0] = sdtr; } else { - FMC_SDCR1 = sdcr & FMC_SDCR_DNC_MASK; - FMC_SDCR2 = sdcr; - FMC_SDTR1 = sdtr & FMC_SDTR_DNC_MASK; - FMC_SDTR2 = sdtr; + reg::FMC_Bank5_6->SDCR[0] = sdcr & FMC_SDCR_DNC_Mask; + reg::FMC_Bank5_6->SDCR[1] = sdcr; + reg::FMC_Bank5_6->SDTR[0] = sdtr & FMC_SDTR_DNC_Mask; + reg::FMC_Bank5_6->SDTR[1] = sdtr; } // Initialise SDRAM. uint32_t bank = params_.bank == 1 ? FMC_SDCMR_CTB1 : FMC_SDCMR_CTB2; - while (FMC_SDSR & FMC_SDSR_BUSY) + while (reg::FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; - FMC_SDCMR = bank | FMC_SDCMR_MODE_CLOCK_CONFIG_ENA; + reg::FMC_Bank5_6->SDCMR = bank | FMC_SDCMR_MODE_ClockConfigEna; delay_us (params_.init_clock_delay_us); - while (FMC_SDSR & FMC_SDSR_BUSY) + while (reg::FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; - FMC_SDCMR = bank | FMC_SDCMR_MODE_PALL; - while (FMC_SDSR & FMC_SDSR_BUSY) + reg::FMC_Bank5_6->SDCMR = bank | FMC_SDCMR_MODE_Pall; + while (reg::FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; - FMC_SDCMR = bank | ((params_.init_auto_refresh - 1) - << FMC_SDCMR_NRFS_SHIFT) - | FMC_SDCMR_MODE_AUTO_REFRESH; - while (FMC_SDSR & FMC_SDSR_BUSY) + reg::FMC_Bank5_6->SDCMR = bank + | ((params_.init_auto_refresh - 1) << FMC_SDCMR_NRFS_Pos) + | FMC_SDCMR_MODE_AutoRefresh; + while (reg::FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; uint32_t sdram_mode = SDRAM_MODE_BURST_LENGTH_1 @@ -116,19 +118,19 @@ Sdram::enable () : SDRAM_MODE_CAS_LATENCY_3) | SDRAM_MODE_OPERATING_MODE_STANDARD | SDRAM_MODE_WRITEBURST_MODE_SINGLE; - FMC_SDCMR = bank | (sdram_mode << FMC_SDCMR_MRD_SHIFT) - | FMC_SDCMR_MODE_LOAD_MODE_REGISTER; + reg::FMC_Bank5_6->SDCMR = bank | (sdram_mode << FMC_SDCMR_MRD_Pos) + | FMC_SDCMR_MODE_LoadModeRegister; // Set refresh rate. int refresh_interval_ns = params_.tref_ms * 1000000 / (1 << params_.row_bits); - FMC_SDRTR = refresh_interval_ns / clock_ns - 20; + reg::FMC_Bank5_6->SDRTR = refresh_interval_ns / clock_ns - 20; } void * Sdram::addr () const { - return params_.bank == 1 ? reinterpret_cast (FMC_BANK7_BASE) - : reinterpret_cast (FMC_BANK8_BASE); + return params_.bank == 1 ? reinterpret_cast (FMC_BANK5_BASE) + : reinterpret_cast (FMC_BANK6_BASE); } int diff --git a/ucoo/hal/sdram/sdram.stm32f4.hh b/ucoo/hal/sdram/sdram.stm32f4.hh index fbeefe0..aac82e0 100644 --- a/ucoo/hal/sdram/sdram.stm32f4.hh +++ b/ucoo/hal/sdram/sdram.stm32f4.hh @@ -23,6 +23,7 @@ // DEALINGS IN THE SOFTWARE. // // }}} +#include "ucoo/hal/gpio/gpio.hh" #include "ucoo/common.hh" #include @@ -34,7 +35,7 @@ class Sdram { public: struct Io { - uint32_t gpio; + GpioPort &port; uint16_t pins; }; struct Param { diff --git a/ucoo/hal/sdram/test/test_sdram.stm32f4.cc b/ucoo/hal/sdram/test/test_sdram.stm32f4.cc index 841d486..17ed1b4 100644 --- a/ucoo/hal/sdram/test/test_sdram.stm32f4.cc +++ b/ucoo/hal/sdram/test/test_sdram.stm32f4.cc @@ -25,9 +25,7 @@ #include "ucoo/arch/arch.hh" #include "ucoo/base/test/test.hh" - -#include -#include +#include "ucoo/utils/bits.hh" #include #include @@ -65,24 +63,25 @@ main (int argc, const char **argv) { ucoo::arch_init (argc, argv); ucoo::test_stream_setup (); - rcc_periph_clock_enable (RCC_GPIOD); - rcc_periph_clock_enable (RCC_GPIOE); - rcc_periph_clock_enable (RCC_GPIOF); - rcc_periph_clock_enable (RCC_GPIOG); - rcc_periph_clock_enable (RCC_GPIOH); - rcc_periph_clock_enable (RCC_GPIOI); + ucoo::GPIOD.enable (); + ucoo::GPIOE.enable (); + ucoo::GPIOF.enable (); + ucoo::GPIOG.enable (); + ucoo::GPIOH.enable (); + ucoo::GPIOI.enable (); std::initializer_list sdram_ios { - { GPIOD, GPIO0 | GPIO1 | GPIO8 | GPIO9 | GPIO10 | GPIO14 | GPIO15 }, - { GPIOE, GPIO0 | GPIO1 | GPIO7 | GPIO8 | GPIO9 | GPIO10 | GPIO11 - | GPIO12 | GPIO13 | GPIO14 | GPIO15 }, - { GPIOF, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 | GPIO5 | GPIO11 - | GPIO12 | GPIO13 | GPIO14 | GPIO15 }, - { GPIOG, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 | GPIO5 | GPIO8 - | GPIO15 }, - { GPIOH, GPIO2 | GPIO3 | GPIO5 | GPIO8 | GPIO9 | GPIO10 | GPIO11 - | GPIO12 | GPIO13 | GPIO14 | GPIO15 }, - { GPIOI, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 | GPIO5 | GPIO6 | GPIO7 - | GPIO9 | GPIO10 }, + { ucoo::GPIOD, ucoo::bits ( + 0, 1, 8, 9, 10, 14, 15) }, + { ucoo::GPIOE, ucoo::bits ( + 0, 1, 7, 8, 9, 10, 11, 12, 13, 14, 15) }, + { ucoo::GPIOF, ucoo::bits ( + 0, 1, 2, 3, 4, 5, 11, 12, 13, 14, 15) }, + { ucoo::GPIOG, ucoo::bits ( + 0, 1, 2, 3, 4, 5, 8, 15) }, + { ucoo::GPIOH, ucoo::bits ( + 2, 3, 5, 8, 9, 10, 11, 12, 13, 14, 15) }, + { ucoo::GPIOI, ucoo::bits ( + 0, 1, 2, 3, 4, 5, 6, 7, 9, 10) }, }; ucoo::Sdram::Param sdram_param { .bank = 1, -- cgit v1.2.3