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Diffstat (limited to 'ucoo/hal/sdram/sdram.stm32f4.cc')
-rw-r--r--ucoo/hal/sdram/sdram.stm32f4.cc94
1 files changed, 48 insertions, 46 deletions
diff --git a/ucoo/hal/sdram/sdram.stm32f4.cc b/ucoo/hal/sdram/sdram.stm32f4.cc
index 07baf54..4c224c0 100644
--- a/ucoo/hal/sdram/sdram.stm32f4.cc
+++ b/ucoo/hal/sdram/sdram.stm32f4.cc
@@ -22,12 +22,9 @@
//
// }}}
#include "ucoo/hal/sdram/sdram.hh"
+#include "ucoo/arch/rcc.stm32.hh"
#include "ucoo/utils/delay.hh"
-#include <libopencm3/stm32/rcc.h>
-#include <libopencm3/stm32/gpio.h>
-#include <libopencm3/stm32/fsmc.h>
-
namespace ucoo {
Sdram::Sdram (std::initializer_list<Io> ios, const Param &params)
@@ -41,20 +38,25 @@ Sdram::enable ()
// Setup GPIO, turn controller on.
for (auto io : ios_)
{
- gpio_mode_setup (io.gpio, GPIO_MODE_AF, GPIO_PUPD_NONE, io.pins);
- gpio_set_output_options (io.gpio, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,
- io.pins);
- gpio_set_af (io.gpio, GPIO_AF12, io.pins);
+ for (int i = 0; i < 16; i++)
+ {
+ if (io.pins & (1 << i))
+ {
+ Gpio gpio (io.port[i]);
+ gpio.af (12);
+ gpio.speed (Gpio::Speed::SPEED_50MHZ);
+ }
+ }
}
- rcc_periph_clock_enable (RCC_FSMC);
+ rcc_peripheral_clock_enable (Rcc::FMC);
// Prepare SDRAM clock, can only be HCLK/2 or HCLK/3. Can go slower than
// requested, but not faster.
- int clock_div = (rcc_ahb_frequency + params_.clock_hz - 1)
+ int clock_div = (rcc_ahb_freq_hz + params_.clock_hz - 1)
/ params_.clock_hz;
if (clock_div < 2)
clock_div = 2;
assert (clock_div <= 3);
- int clock_hz = rcc_ahb_frequency / clock_div;
+ int clock_hz = rcc_ahb_freq_hz / clock_div;
int clock_ns = 1000000000 / clock_hz;
// Prepare and set parameters.
assert (params_.bank == 1 || params_.bank == 2);
@@ -64,50 +66,50 @@ Sdram::enable ()
assert (params_.row_bits >= 11 && params_.row_bits <= 13);
assert (params_.col_bits >= 8 && params_.col_bits <= 11);
uint32_t sdcr =
- FMC_SDCR_RPIPE_NONE
+ FMC_SDCR_RPIPE_None
| FMC_SDCR_RBURST
- | (clock_div == 2 ? FMC_SDCR_SDCLK_2HCLK : FMC_SDCR_SDCLK_3HCLK)
- | (params_.cas << FMC_SDCR_CAS_SHIFT)
- | (params_.banks == 2 ? FMC_SDCR_NB2 : FMC_SDCR_NB4)
- | (params_.bits == 8 ? FMC_SDCR_MWID_8b
- : (params_.bits == 16 ? FMC_SDCR_MWID_16b : FMC_SDCR_MWID_32b))
- | ((params_.row_bits - 11) << FMC_SDCR_NR_SHIFT)
- | ((params_.col_bits - 8) << FMC_SDCR_NC_SHIFT);
+ | (clock_div == 2 ? FMC_SDCR_SDCLK_2Hclk : FMC_SDCR_SDCLK_3Hclk)
+ | (params_.cas << FMC_SDCR_CAS_Pos)
+ | (params_.banks == 2 ? 0 : FMC_SDCR_NB)
+ | (params_.bits == 8 ? FMC_SDCR_MWID_8B
+ : (params_.bits == 16 ? FMC_SDCR_MWID_16B : FMC_SDCR_MWID_32B))
+ | ((params_.row_bits - 11) << FMC_SDCR_NR_Pos)
+ | ((params_.col_bits - 8) << FMC_SDCR_NC_Pos);
uint32_t sdtr =
- ((params_.trcd - 1) << FMC_SDTR_TRCD_SHIFT)
- | ((params_.trp - 1) << FMC_SDTR_TRP_SHIFT)
- | ((params_.twr - 1) << FMC_SDTR_TWR_SHIFT)
- | ((params_.trc - 1) << FMC_SDTR_TRC_SHIFT)
- | ((params_.tras - 1) << FMC_SDTR_TRAS_SHIFT)
- | ((params_.txsr - 1) << FMC_SDTR_TXSR_SHIFT)
- | ((params_.tmrd - 1) << FMC_SDTR_TMRD_SHIFT);
+ ((params_.trcd - 1) << FMC_SDTR_TRCD_Pos)
+ | ((params_.trp - 1) << FMC_SDTR_TRP_Pos)
+ | ((params_.twr - 1) << FMC_SDTR_TWR_Pos)
+ | ((params_.trc - 1) << FMC_SDTR_TRC_Pos)
+ | ((params_.tras - 1) << FMC_SDTR_TRAS_Pos)
+ | ((params_.txsr - 1) << FMC_SDTR_TXSR_Pos)
+ | ((params_.tmrd - 1) << FMC_SDTR_TMRD_Pos);
if (params_.bank == 1)
{
- FMC_SDCR1 = sdcr;
- FMC_SDTR1 = sdtr;
+ reg::FMC_Bank5_6->SDCR[0] = sdcr;
+ reg::FMC_Bank5_6->SDTR[0] = sdtr;
}
else
{
- FMC_SDCR1 = sdcr & FMC_SDCR_DNC_MASK;
- FMC_SDCR2 = sdcr;
- FMC_SDTR1 = sdtr & FMC_SDTR_DNC_MASK;
- FMC_SDTR2 = sdtr;
+ reg::FMC_Bank5_6->SDCR[0] = sdcr & FMC_SDCR_DNC_Mask;
+ reg::FMC_Bank5_6->SDCR[1] = sdcr;
+ reg::FMC_Bank5_6->SDTR[0] = sdtr & FMC_SDTR_DNC_Mask;
+ reg::FMC_Bank5_6->SDTR[1] = sdtr;
}
// Initialise SDRAM.
uint32_t bank = params_.bank == 1 ? FMC_SDCMR_CTB1 : FMC_SDCMR_CTB2;
- while (FMC_SDSR & FMC_SDSR_BUSY)
+ while (reg::FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)
;
- FMC_SDCMR = bank | FMC_SDCMR_MODE_CLOCK_CONFIG_ENA;
+ reg::FMC_Bank5_6->SDCMR = bank | FMC_SDCMR_MODE_ClockConfigEna;
delay_us (params_.init_clock_delay_us);
- while (FMC_SDSR & FMC_SDSR_BUSY)
+ while (reg::FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)
;
- FMC_SDCMR = bank | FMC_SDCMR_MODE_PALL;
- while (FMC_SDSR & FMC_SDSR_BUSY)
+ reg::FMC_Bank5_6->SDCMR = bank | FMC_SDCMR_MODE_Pall;
+ while (reg::FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)
;
- FMC_SDCMR = bank | ((params_.init_auto_refresh - 1)
- << FMC_SDCMR_NRFS_SHIFT)
- | FMC_SDCMR_MODE_AUTO_REFRESH;
- while (FMC_SDSR & FMC_SDSR_BUSY)
+ reg::FMC_Bank5_6->SDCMR = bank
+ | ((params_.init_auto_refresh - 1) << FMC_SDCMR_NRFS_Pos)
+ | FMC_SDCMR_MODE_AutoRefresh;
+ while (reg::FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)
;
uint32_t sdram_mode =
SDRAM_MODE_BURST_LENGTH_1
@@ -116,19 +118,19 @@ Sdram::enable ()
: SDRAM_MODE_CAS_LATENCY_3)
| SDRAM_MODE_OPERATING_MODE_STANDARD
| SDRAM_MODE_WRITEBURST_MODE_SINGLE;
- FMC_SDCMR = bank | (sdram_mode << FMC_SDCMR_MRD_SHIFT)
- | FMC_SDCMR_MODE_LOAD_MODE_REGISTER;
+ reg::FMC_Bank5_6->SDCMR = bank | (sdram_mode << FMC_SDCMR_MRD_Pos)
+ | FMC_SDCMR_MODE_LoadModeRegister;
// Set refresh rate.
int refresh_interval_ns = params_.tref_ms * 1000000
/ (1 << params_.row_bits);
- FMC_SDRTR = refresh_interval_ns / clock_ns - 20;
+ reg::FMC_Bank5_6->SDRTR = refresh_interval_ns / clock_ns - 20;
}
void *
Sdram::addr () const
{
- return params_.bank == 1 ? reinterpret_cast<void *> (FMC_BANK7_BASE)
- : reinterpret_cast<void *> (FMC_BANK8_BASE);
+ return params_.bank == 1 ? reinterpret_cast<void *> (FMC_BANK5_BASE)
+ : reinterpret_cast<void *> (FMC_BANK6_BASE);
}
int